pci: imx: Add DM and DT support
Add DM support and support for probing the iMX PCI driver from DT. The legacy non-DM support is retained, however shall be removed once DM PCI is the only option remaining. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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@ -16,6 +16,7 @@
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#include <asm/arch/crm_regs.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <dm.h>
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#include <linux/sizes.h>
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#include <errno.h>
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#include <asm/arch/sys_proto.h>
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@ -383,10 +384,9 @@ static void imx_pcie_fix_dabt_handler(bool set)
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}
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}
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static int imx_pcie_read_config(struct pci_controller *hose, pci_dev_t d,
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int where, u32 *val)
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static int imx_pcie_read_cfg(struct imx_pcie_priv *priv, pci_dev_t d,
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int where, u32 *val)
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{
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struct imx_pcie_priv *priv = hose->priv_data;
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void __iomem *va_address;
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int ret;
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@ -413,10 +413,9 @@ static int imx_pcie_read_config(struct pci_controller *hose, pci_dev_t d,
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return 0;
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}
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static int imx_pcie_write_config(struct pci_controller *hose, pci_dev_t d,
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int where, u32 val)
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static int imx_pcie_write_cfg(struct imx_pcie_priv *priv, pci_dev_t d,
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int where, u32 val)
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{
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struct imx_pcie_priv *priv = hose->priv_data;
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void __iomem *va_address = NULL;
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int ret;
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@ -668,6 +667,7 @@ static int imx_pcie_link_up(struct imx_pcie_priv *priv)
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return 0;
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}
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#if !CONFIG_IS_ENABLED(DM_PCI)
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static struct imx_pcie_priv imx_pcie_priv = {
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.dbi_base = (void __iomem *)MX6_DBI_ADDR,
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.cfg_base = (void __iomem *)MX6_ROOT_ADDR,
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@ -675,6 +675,22 @@ static struct imx_pcie_priv imx_pcie_priv = {
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static struct imx_pcie_priv *priv = &imx_pcie_priv;
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static int imx_pcie_read_config(struct pci_controller *hose, pci_dev_t d,
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int where, u32 *val)
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{
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struct imx_pcie_priv *priv = hose->priv_data;
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return imx_pcie_read_cfg(priv, d, where, val);
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}
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static int imx_pcie_write_config(struct pci_controller *hose, pci_dev_t d,
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int where, u32 val)
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{
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struct imx_pcie_priv *priv = hose->priv_data;
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return imx_pcie_write_cfg(priv, d, where, val);
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}
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void imx_pcie_init(void)
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{
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/* Static instance of the controller. */
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@ -730,3 +746,86 @@ void pci_init_board(void)
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{
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imx_pcie_init();
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}
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#else
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static int imx_pcie_dm_read_config(struct udevice *dev, pci_dev_t bdf,
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uint offset, ulong *value,
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enum pci_size_t size)
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{
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struct imx_pcie_priv *priv = dev_get_priv(dev);
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u32 tmpval;
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int ret;
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ret = imx_pcie_read_cfg(priv, bdf, offset, &tmpval);
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if (ret)
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return ret;
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*value = pci_conv_32_to_size(tmpval, offset, size);
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return 0;
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}
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static int imx_pcie_dm_write_config(struct udevice *dev, pci_dev_t bdf,
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uint offset, ulong value,
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enum pci_size_t size)
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{
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struct imx_pcie_priv *priv = dev_get_priv(dev);
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u32 tmpval, newval;
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int ret;
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ret = imx_pcie_read_cfg(priv, bdf, offset, &tmpval);
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if (ret)
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return ret;
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newval = pci_conv_size_to_32(tmpval, value, offset, size);
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return imx_pcie_write_cfg(priv, bdf, offset, newval);
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}
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static int imx_pcie_dm_probe(struct udevice *dev)
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{
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struct imx_pcie_priv *priv = dev_get_priv(dev);
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return imx_pcie_link_up(priv);
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}
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static int imx_pcie_dm_remove(struct udevice *dev)
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{
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struct imx_pcie_priv *priv = dev_get_priv(dev);
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imx6_pcie_assert_core_reset(priv, true);
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return 0;
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}
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static int imx_pcie_ofdata_to_platdata(struct udevice *dev)
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{
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struct imx_pcie_priv *priv = dev_get_priv(dev);
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priv->dbi_base = (void __iomem *)devfdt_get_addr_index(dev, 0);
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priv->cfg_base = (void __iomem *)devfdt_get_addr_index(dev, 1);
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if (!priv->dbi_base || !priv->cfg_base)
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return -EINVAL;
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return 0;
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}
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static const struct dm_pci_ops imx_pcie_ops = {
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.read_config = imx_pcie_dm_read_config,
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.write_config = imx_pcie_dm_write_config,
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};
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static const struct udevice_id imx_pcie_ids[] = {
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{ .compatible = "fsl,imx6q-pcie" },
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{ }
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};
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U_BOOT_DRIVER(imx_pcie) = {
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.name = "imx_pcie",
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.id = UCLASS_PCI,
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.of_match = imx_pcie_ids,
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.ops = &imx_pcie_ops,
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.probe = imx_pcie_dm_probe,
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.remove = imx_pcie_dm_remove,
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.ofdata_to_platdata = imx_pcie_ofdata_to_platdata,
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.priv_auto_alloc_size = sizeof(struct imx_pcie_priv),
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.flags = DM_FLAG_OS_PREPARE,
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};
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#endif
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