net: dwc_eth_qos: add Kconfig option to select supported configuration
Add configuration flag to select the supported dwc driver configuration: - CONFIG_DWC_ETH_QOS_TEGRA186 - CONFIG_DWC_ETH_QOS_IMX - CONFIG_DWC_ETH_QOS_STM32 See Linux driver ethernet/stmicro/stmmac and associated glue layers for other configuration examples. This patch removes the not-selected compatibles and lets the linker remove the unused functions to reduce the size of the driver. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
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@ -156,9 +156,30 @@ config DWC_ETH_QOS
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help
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help
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This driver supports the Synopsys Designware Ethernet QOS (Quality
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This driver supports the Synopsys Designware Ethernet QOS (Quality
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Of Service) IP block. The IP supports many options for bus type,
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Of Service) IP block. The IP supports many options for bus type,
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clocking/reset structure, and feature list. This driver currently
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clocking/reset structure, and feature list.
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supports the specific configuration used in NVIDIA's Tegra186 chip,
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but should be extensible to other combinations quite easily.
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config DWC_ETH_QOS_IMX
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bool "Synopsys DWC Ethernet QOS device support for IMX"
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depends on DWC_ETH_QOS
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help
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The Synopsys Designware Ethernet QOS IP block with the specific
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configuration used in IMX soc.
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config DWC_ETH_QOS_STM32
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bool "Synopsys DWC Ethernet QOS device support for STM32"
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depends on DWC_ETH_QOS
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default y if ARCH_STM32MP
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help
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The Synopsys Designware Ethernet QOS IP block with the specific
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configuration used in STM32MP soc.
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config DWC_ETH_QOS_TEGRA186
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bool "Synopsys DWC Ethernet QOS device support for TEGRA186"
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depends on DWC_ETH_QOS
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default y if TEGRA186
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help
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The Synopsys Designware Ethernet QOS IP block with specific
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configuration used in NVIDIA's Tegra186 chip.
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config E1000
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config E1000
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bool "Intel PRO/1000 Gigabit Ethernet support"
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bool "Intel PRO/1000 Gigabit Ethernet support"
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@ -2100,7 +2100,7 @@ static struct eqos_ops eqos_tegra186_ops = {
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.eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_tegra186
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.eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_tegra186
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};
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};
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static const struct eqos_config eqos_tegra186_config = {
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static const struct eqos_config __maybe_unused eqos_tegra186_config = {
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.reg_access_always_ok = false,
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.reg_access_always_ok = false,
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.mdio_wait = 10,
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.mdio_wait = 10,
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.swr_wait = 10,
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.swr_wait = 10,
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@ -2127,7 +2127,7 @@ static struct eqos_ops eqos_stm32_ops = {
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.eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_stm32
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.eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_stm32
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};
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};
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static const struct eqos_config eqos_stm32_config = {
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static const struct eqos_config __maybe_unused eqos_stm32_config = {
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.reg_access_always_ok = false,
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.reg_access_always_ok = false,
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.mdio_wait = 10000,
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.mdio_wait = 10000,
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.swr_wait = 50,
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.swr_wait = 50,
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@ -2154,7 +2154,7 @@ static struct eqos_ops eqos_imx_ops = {
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.eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_imx
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.eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_imx
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};
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};
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struct eqos_config eqos_imx_config = {
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struct eqos_config __maybe_unused eqos_imx_config = {
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.reg_access_always_ok = false,
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.reg_access_always_ok = false,
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.mdio_wait = 10000,
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.mdio_wait = 10000,
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.swr_wait = 50,
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.swr_wait = 50,
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@ -2165,18 +2165,24 @@ struct eqos_config eqos_imx_config = {
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};
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};
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static const struct udevice_id eqos_ids[] = {
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static const struct udevice_id eqos_ids[] = {
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#if IS_ENABLED(CONFIG_DWC_ETH_QOS_TEGRA186)
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{
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{
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.compatible = "nvidia,tegra186-eqos",
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.compatible = "nvidia,tegra186-eqos",
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.data = (ulong)&eqos_tegra186_config
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.data = (ulong)&eqos_tegra186_config
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},
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},
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#endif
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#if IS_ENABLED(CONFIG_DWC_ETH_QOS_STM32)
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{
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{
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.compatible = "st,stm32mp1-dwmac",
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.compatible = "st,stm32mp1-dwmac",
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.data = (ulong)&eqos_stm32_config
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.data = (ulong)&eqos_stm32_config
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},
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},
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#endif
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#if IS_ENABLED(CONFIG_DWC_ETH_QOS_IMX)
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{
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{
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.compatible = "fsl,imx-eqos",
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.compatible = "fsl,imx-eqos",
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.data = (ulong)&eqos_imx_config
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.data = (ulong)&eqos_imx_config
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},
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},
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#endif
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{ }
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{ }
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};
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};
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