Remove unused files
[1] arch/arm/include/asm/arch-at91/at91_shdwn.h The top9000 was the last board to use this header file. It was removed by commitd58a9451e7(ppc/arm: zap EMK boards). [2] board/matrix_vision/common/* Some Matrix Vision boards were dropped by commite7a565638a(powerpc: mpc83xx: remove board support for MERGERBOX and MVBLM7) and commitaf55e35d33(powerpc: mpc5xxx: remove board support for MVBC_P and MVSMR). Since then these files have been unused. [3] include/usb/omap1510_udc.h The omap5912osk was the last board to use this header file. It was removed by commit62d636aa2a(omap: remove omap5912osk board support). Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-By: Wolfgang Denk <wd@denx.de>
This commit is contained in:
Masahiro Yamada
Anatolij Gustschin
parent
2ed8c878eb
commit
9ea7f3a6d8
@ -1,35 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2010
|
||||
* Reinhard Meyer, reinhard.meyer@emk-elektronik.de
|
||||
*
|
||||
* Shutdown Controller
|
||||
* Based on AT91SAM9XE datasheet
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef AT91_SHDWN_H
|
||||
#define AT91_SHDWN_H
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
struct at91_shdwn {
|
||||
u32 cr; /* Control Rer. WO */
|
||||
u32 mr; /* Mode Register RW 0x00000003 */
|
||||
u32 sr; /* Status Register RO 0x00000000 */
|
||||
};
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#define AT91_SHDW_CR_KEY 0xa5000000
|
||||
#define AT91_SHDW_CR_SHDW 0x00000001
|
||||
|
||||
#define AT91_SHDW_MR_RTTWKEN 0x00010000
|
||||
#define AT91_SHDW_MR_CPTWK0 0x000000f0
|
||||
#define AT91_SHDW_MR_WKMODE0H2L 0x00000002
|
||||
#define AT91_SHDW_MR_WKMODE0L2H 0x00000001
|
||||
|
||||
#define AT91_SHDW_SR_RTTWK 0x00010000
|
||||
#define AT91_SHDW_SR_WAKEUP0 0x00000001
|
||||
|
||||
#endif
|
||||
@ -1,8 +0,0 @@
|
||||
#
|
||||
# (C) Copyright 2006
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
obj-y = mv_common.o
|
||||
@ -1,112 +0,0 @@
|
||||
/*
|
||||
* (C) Copyright 2008
|
||||
* Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <malloc.h>
|
||||
#include <environment.h>
|
||||
#include <fpga.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#ifndef CONFIG_ENV_IS_NOWHERE
|
||||
static char* entries_to_keep[] = {
|
||||
"serial#", "ethaddr", "eth1addr", "model_info", "sensor_cnt",
|
||||
"fpgadatasize", "ddr_size", "use_dhcp", "use_static_ipaddr",
|
||||
"static_ipaddr", "static_netmask", "static_gateway",
|
||||
"syslog", "watchdog", "netboot", "evo8serialnumber" };
|
||||
|
||||
#define MV_MAX_ENV_ENTRY_LENGTH 64
|
||||
#define MV_KEEP_ENTRIES ARRAY_SIZE(entries_to_keep)
|
||||
|
||||
void mv_reset_environment(void)
|
||||
{
|
||||
int i;
|
||||
char *s[MV_KEEP_ENTRIES];
|
||||
char entries[MV_KEEP_ENTRIES][MV_MAX_ENV_ENTRY_LENGTH];
|
||||
|
||||
printf("\n*** RESET ENVIRONMENT ***\n");
|
||||
|
||||
memset(entries, 0, MV_KEEP_ENTRIES * MV_MAX_ENV_ENTRY_LENGTH);
|
||||
for (i = 0; i < MV_KEEP_ENTRIES; i++) {
|
||||
s[i] = getenv(entries_to_keep[i]);
|
||||
if (s[i]) {
|
||||
printf("save '%s' : %s\n", entries_to_keep[i], s[i]);
|
||||
strncpy(entries[i], s[i], MV_MAX_ENV_ENTRY_LENGTH);
|
||||
}
|
||||
}
|
||||
|
||||
gd->env_valid = 0;
|
||||
env_relocate();
|
||||
|
||||
for (i = 0; i < MV_KEEP_ENTRIES; i++) {
|
||||
if (s[i]) {
|
||||
printf("restore '%s' : %s\n", entries_to_keep[i], s[i]);
|
||||
setenv(entries_to_keep[i], s[i]);
|
||||
}
|
||||
}
|
||||
|
||||
saveenv();
|
||||
}
|
||||
#endif
|
||||
|
||||
int mv_load_fpga(void)
|
||||
{
|
||||
int result;
|
||||
size_t data_size = 0;
|
||||
void *fpga_data = NULL;
|
||||
char *datastr = getenv("fpgadata");
|
||||
char *sizestr = getenv("fpgadatasize");
|
||||
|
||||
if (getenv("skip_fpga")) {
|
||||
printf("found 'skip_fpga' -> FPGA _not_ loaded !\n");
|
||||
return -1;
|
||||
}
|
||||
printf("loading FPGA\n");
|
||||
|
||||
if (datastr)
|
||||
fpga_data = (void *)simple_strtoul(datastr, NULL, 16);
|
||||
if (sizestr)
|
||||
data_size = (size_t)simple_strtoul(sizestr, NULL, 16);
|
||||
if (!data_size) {
|
||||
printf("fpgadatasize invalid -> FPGA _not_ loaded !\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
result = fpga_load(0, fpga_data, data_size, BIT_FULL);
|
||||
if (!result)
|
||||
bootstage_mark(BOOTSTAGE_ID_START);
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
u8 *dhcp_vendorex_prep(u8 *e)
|
||||
{
|
||||
char *ptr;
|
||||
|
||||
/* DHCP vendor-class-identifier = 60 */
|
||||
if ((ptr = getenv("dhcp_vendor-class-identifier"))) {
|
||||
*e++ = 60;
|
||||
*e++ = strlen(ptr);
|
||||
while (*ptr)
|
||||
*e++ = *ptr++;
|
||||
}
|
||||
/* DHCP_CLIENT_IDENTIFIER = 61 */
|
||||
if ((ptr = getenv("dhcp_client_id"))) {
|
||||
*e++ = 61;
|
||||
*e++ = strlen(ptr);
|
||||
while (*ptr)
|
||||
*e++ = *ptr++;
|
||||
}
|
||||
|
||||
return e;
|
||||
}
|
||||
|
||||
u8 *dhcp_vendorex_proc(u8 *popt)
|
||||
{
|
||||
return NULL;
|
||||
}
|
||||
@ -1,9 +0,0 @@
|
||||
/*
|
||||
* Copyright 2008 Matrix Vision GmbH
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
|
||||
extern int mv_load_fpga(void);
|
||||
extern void mv_reset_environment(void);
|
||||
@ -1,174 +0,0 @@
|
||||
/*
|
||||
* (C) Copyright 2003
|
||||
* Gerry Hamel, geh@ti.com, Texas Instruments
|
||||
*
|
||||
* Based on
|
||||
* linux/drivers/usb/device/bi/omap.h
|
||||
* Register definitions for TI OMAP1510 USB bus interface driver
|
||||
*
|
||||
* Author: MontaVista Software, Inc.
|
||||
* source@mvista.com
|
||||
*
|
||||
* 2003 (c) MontaVista Software, Inc. This file is licensed under
|
||||
* the terms of the GNU General Public License version 2. This program
|
||||
* is licensed "as is" without any warranty of any kind, whether express
|
||||
* or implied.
|
||||
*/
|
||||
|
||||
#ifndef __USBDCORE_OMAP1510_H__
|
||||
#define __USBDCORE_OMAP1510_H__
|
||||
|
||||
|
||||
/*
|
||||
* 13.2 MPU Register Map
|
||||
*/
|
||||
|
||||
/* Table 13-1. USB Function Module Registers (endpoint) */
|
||||
#define UDC_BASE 0xFFFB4000
|
||||
#define UDC_OFFSET(offset) (UDC_BASE + (offset))
|
||||
#define UDC_REV UDC_OFFSET(0x0) /* Revision */
|
||||
#define UDC_EP_NUM UDC_OFFSET(0x4) /* Endpoint selection */
|
||||
#define UDC_DATA UDC_OFFSET(0x08) /* Data */
|
||||
#define UDC_CTRL UDC_OFFSET(0x0C) /* Control */
|
||||
#define UDC_STAT_FLG UDC_OFFSET(0x10) /* Status flag */
|
||||
#define UDC_RXFSTAT UDC_OFFSET(0x14) /* Receive FIFO status */
|
||||
#define UDC_SYSCON1 UDC_OFFSET(0x18) /* System configuration 1 */
|
||||
#define UDC_SYSCON2 UDC_OFFSET(0x1C) /* System configuration 2 */
|
||||
#define UDC_DEVSTAT UDC_OFFSET(0x20) /* Device status */
|
||||
#define UDC_SOF UDC_OFFSET(0x24) /* Start of frame */
|
||||
#define UDC_IRQ_EN UDC_OFFSET(0x28) /* Interrupt enable */
|
||||
#define UDC_DMA_IRQ_EN UDC_OFFSET(0x2C) /* DMA interrupt enable */
|
||||
#define UDC_IRQ_SRC UDC_OFFSET(0x30) /* Interrupt source */
|
||||
#define UDC_EPN_STAT UDC_OFFSET(0x34) /* Endpoint interrupt status */
|
||||
#define UDC_DMAN_STAT UDC_OFFSET(0x3C) /* DMA endpoint interrupt status */
|
||||
|
||||
/* IRQ_EN register fields */
|
||||
#define UDC_Sof_IE (1 << 7) /* Start-of-frame interrupt enabled */
|
||||
#define UDC_EPn_RX_IE (1 << 5) /* Receive endpoint interrupt enabled */
|
||||
#define UDC_EPn_TX_IE (1 << 4) /* Transmit endpoint interrupt enabled */
|
||||
#define UDC_DS_Chg_IE (1 << 3) /* Device state changed interrupt enabled */
|
||||
#define UDC_EP0_IE (1 << 0) /* EP0 transaction interrupt enabled */
|
||||
|
||||
/* IRQ_SRC register fields */
|
||||
#define UDC_TXn_Done (1 << 10) /* Transmit DMA channel n done */
|
||||
#define UDC_RXn_Cnt (1 << 9) /* Receive DMA channel n transactions count */
|
||||
#define UDC_RXn_EOT (1 << 8) /* Receive DMA channel n end of transfer */
|
||||
#define UDC_SOF_Flg (1 << 7) /* Start-of-frame interrupt flag */
|
||||
#define UDC_EPn_RX (1 << 5) /* Endpoint n OUT transaction */
|
||||
#define UDC_EPn_TX (1 << 4) /* Endpoint n IN transaction */
|
||||
#define UDC_DS_Chg (1 << 3) /* Device state changed */
|
||||
#define UDC_Setup (1 << 2) /* Setup transaction */
|
||||
#define UDC_EP0_RX (1 << 1) /* EP0 OUT transaction */
|
||||
#define UDC_EP0_TX (1 << 0) /* EP0 IN transaction */
|
||||
|
||||
/* DEVSTAT register fields, 14.2.9 */
|
||||
#define UDC_R_WK_OK (1 << 6) /* Remote wakeup granted */
|
||||
#define UDC_USB_Reset (1 << 5) /* USB reset signalling is active */
|
||||
#define UDC_SUS (1 << 4) /* Suspended state */
|
||||
#define UDC_CFG (1 << 3) /* Configured state */
|
||||
#define UDC_ADD (1 << 2) /* Addressed state */
|
||||
#define UDC_DEF (1 << 1) /* Default state */
|
||||
#define UDC_ATT (1 << 0) /* Attached state */
|
||||
|
||||
/* SYSCON1 register fields */
|
||||
#define UDC_Cfg_Lock (1 << 8) /* Device configuration locked */
|
||||
#define UDC_Nak_En (1 << 4) /* NAK enable */
|
||||
#define UDC_Self_Pwr (1 << 2) /* Device is self-powered */
|
||||
#define UDC_Soff_Dis (1 << 1) /* Shutoff disabled */
|
||||
#define UDC_Pullup_En (1 << 0) /* External pullup enabled */
|
||||
|
||||
/* SYSCON2 register fields */
|
||||
#define UDC_Rmt_Wkp (1 << 6) /* Remote wakeup */
|
||||
#define UDC_Stall_Cmd (1 << 5) /* Stall endpoint */
|
||||
#define UDC_Dev_Cfg (1 << 3) /* Device configured */
|
||||
#define UDC_Clr_Cfg (1 << 2) /* Clear configured */
|
||||
|
||||
/*
|
||||
* Select and enable endpoints
|
||||
*/
|
||||
|
||||
/* Table 13-1. USB Function Module Registers (endpoint configuration) */
|
||||
#define UDC_EPBASE UDC_OFFSET(0x80) /* Endpoints base address */
|
||||
#define UDC_EP0 UDC_EPBASE /* Control endpoint configuration */
|
||||
#define UDC_EP_RX_BASE UDC_OFFSET(0x84) /* Receive endpoints base address */
|
||||
#define UDC_EP_RX(endpoint) (UDC_EP_RX_BASE + ((endpoint) - 1) * 4)
|
||||
#define UDC_EP_TX_BASE UDC_OFFSET(0xC4) /* Transmit endpoints base address */
|
||||
#define UDC_EP_TX(endpoint) (UDC_EP_TX_BASE + ((endpoint) - 1) * 4)
|
||||
|
||||
/* EP_NUM register fields */
|
||||
#define UDC_Setup_Sel (1 << 6) /* Setup FIFO select */
|
||||
#define UDC_EP_Sel (1 << 5) /* TX/RX FIFO select */
|
||||
#define UDC_EP_Dir (1 << 4) /* Endpoint direction */
|
||||
|
||||
/* CTRL register fields */
|
||||
#define UDC_Clr_Halt (1 << 7) /* Clear halt endpoint */
|
||||
#define UDC_Set_Halt (1 << 6) /* Set halt endpoint */
|
||||
#define UDC_Set_FIFO_En (1 << 2) /* Set FIFO enable */
|
||||
#define UDC_Clr_EP (1 << 1) /* Clear endpoint */
|
||||
#define UDC_Reset_EP (1 << 0) /* Reset endpoint */
|
||||
|
||||
/* STAT_FLG register fields */
|
||||
#define UDC_Miss_In (1 << 14)
|
||||
#define UDC_Data_Flush (1 << 13)
|
||||
#define UDC_ISO_Err (1 << 12)
|
||||
#define UDC_ISO_FIFO_Empty (1 << 9)
|
||||
#define UDC_ISO_FIFO_Full (1 << 8)
|
||||
#define UDC_EP_Halted (1 << 6)
|
||||
#define UDC_STALL (1 << 5)
|
||||
#define UDC_NAK (1 << 4)
|
||||
#define UDC_ACK (1 << 3)
|
||||
#define UDC_FIFO_En (1 << 2)
|
||||
#define UDC_Non_ISO_FIFO_Empty (1 << 1)
|
||||
#define UDC_Non_ISO_FIFO_Full (1 << 0)
|
||||
|
||||
/* EPn_RX register fields */
|
||||
#define UDC_EPn_RX_Valid (1 << 15) /* valid */
|
||||
#define UDC_EPn_RX_Db (1 << 14) /* double-buffer */
|
||||
#define UDC_EPn_RX_Iso (1 << 11) /* isochronous */
|
||||
|
||||
/* EPn_TX register fields */
|
||||
#define UDC_EPn_TX_Valid (1 << 15) /* valid */
|
||||
#define UDC_EPn_TX_Db (1 << 14) /* double-buffer */
|
||||
#define UDC_EPn_TX_Iso (1 << 11) /* isochronous */
|
||||
|
||||
#define EP0_PACKETSIZE 0x40
|
||||
|
||||
/* physical to logical endpoint mapping
|
||||
* Physical endpoints are an index into device->bus->endpoint_array.
|
||||
* Logical endpoints are endpoints 0 to 15 IN and OUT as defined in
|
||||
* the USB specification.
|
||||
*
|
||||
* physical ep logical ep direction endpoint_address
|
||||
* 0 0 IN and OUT 0x00
|
||||
* 1 to 15 1 to 15 OUT 0x01 to 0x0f
|
||||
* 16 to 30 1 to 15 IN 0x81 to 0x8f
|
||||
*/
|
||||
#define PHYS_EP_TO_EP_ADDR(ep) (((ep) < 16) ? (ep) : (((ep) - 15) | 0x80))
|
||||
#define EP_ADDR_TO_PHYS_EP(a) (((a) & 0x80) ? (((a) & ~0x80) + 15) : (a))
|
||||
|
||||
/* MOD_CONF_CTRL_0 bits (FIXME: move to board hardware.h ?) */
|
||||
#define CONF_MOD_USB_W2FC_VBUS_MODE_R (1 << 17)
|
||||
|
||||
/* Other registers (may be) related to USB */
|
||||
|
||||
#define CLOCK_CTRL (0xFFFE0830)
|
||||
#define APLL_CTRL (0xFFFE084C)
|
||||
#define DPLL_CTRL (0xFFFE083C)
|
||||
#define SOFT_REQ (0xFFFE0834)
|
||||
#define STATUS_REQ (0xFFFE0840)
|
||||
|
||||
/* FUNC_MUX_CTRL_0 bits related to USB */
|
||||
#define UDC_VBUS_CTRL (1 << 19)
|
||||
#define UDC_VBUS_MODE (1 << 18)
|
||||
|
||||
/* OMAP Endpoint parameters */
|
||||
#define UDC_OUT_PACKET_SIZE 64
|
||||
#define UDC_IN_PACKET_SIZE 64
|
||||
#define UDC_INT_PACKET_SIZE 16
|
||||
#define UDC_BULK_PACKET_SIZE 16
|
||||
|
||||
#define UDC_INT_ENDPOINT 5
|
||||
#define UDC_OUT_ENDPOINT 2
|
||||
#define UDC_IN_ENDPOINT 1
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user