ebony: Drop
This board has not compiled for me for quite some time due to size constraints, remove. Cc: Stefan Roese <sr@denx.de> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Tom Rini
Stefan Roese
parent
123b6cd7a4
commit
9d9e2f5daf
@ -1,16 +0,0 @@
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if TARGET_EBONY
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config SYS_BOARD
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default "ebony"
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config SYS_VENDOR
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default "amcc"
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config SYS_CONFIG_NAME
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default "ebony"
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config DISPLAY_BOARDINFO
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bool
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default y
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endif
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@ -1,6 +0,0 @@
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EBONY BOARD
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M: Stefan Roese <sr@denx.de>
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S: Maintained
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F: board/amcc/ebony/
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F: include/configs/ebony.h
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F: configs/ebony_defconfig
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@ -1,9 +0,0 @@
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#
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# (C) Copyright 2002-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y = ebony.o flash.o
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extra-y += init.o
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@ -1,136 +0,0 @@
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AMCC Ebony Board
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Last Update: September 12, 2002
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=======================================================================
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This file contains some handy info regarding U-Boot and the AMCC
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Ebony evaluation board. See the README.ppc440 for additional
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information.
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SWITCH SETTINGS & JUMPERS
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==========================
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Here's what I've been using successfully. If you feel inclined to
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change things ... please read the docs!
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DIPSW U46 U80
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------------------------
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SW 1 off on
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SW 2 on on
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SW 3 on on
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SW 4 off on
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SW 5 on off
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SW 6 on on
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SW 7 on off
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SW 8 on off
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J41: strapped
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J42: open
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All others are factory default.
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I2C probe
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=====================
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The i2c utilities have been tested on both Rev B. and Rev C. and
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look good. The CONFIG_SYS_I2C_NOPROBES macro is defined to prevent
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probing the CDCV850 clock controller at address 0x69 (since reading
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it causes the i2c implementation to misbehave. The output of
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'i2c probe' should look like this (assuming you are only using a single
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SO-DIMM:
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=> i2c probe
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Valid chip addresses: 50 53 54
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Excluded chip addresses: 69
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GETTING OUT OF I2C TROUBLE
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===========================
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If you're like me ... you may have screwed up your bootstrap serial
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eeprom ... or worse, your SPD eeprom when experimenting with the
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i2c commands. If so, here are some ideas on how to get out of
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trouble:
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Serial bootstrap eeprom corruption:
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-----------------------------------
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Power down the board and set the following straps:
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J41 - open
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J42 - strapped
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This will select the default sys0 and sys1 settings (the serial
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eeproms are not used). Then power up the board and fix the serial
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eeprom using the 'i2c mm' command. Here are the values I currently
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use:
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=> i2c md 50 0 10
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0000: bf a2 04 01 ae 94 11 00 00 00 00 00 00 00 00 00 ................
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=> i2c md 54 0 10
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0000: 8f b3 24 01 4d 14 11 00 00 00 00 00 00 00 00 00 ..$.M...........
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Once you have the eeproms set correctly change the
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J41/J42 straps as you desire.
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SPD eeprom corruption:
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------------------------
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I've corrupted the SPD eeprom several times ... perhaps too much coffee
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and not enough presence of mind ;-). By default, the ebony code uses
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the SPD to initialize the DDR SDRAM control registers. So if the SPD
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eeprom is corrupted, U-Boot will never get into ram. Here's how I got
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out of this situation:
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0. First, _before_ playing with the i2c utilities, do an 'i2c probe', then
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use 'i2c md' to capture the various device contents to a file. Some day
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you may be glad you did this ... trust me :-). Otherwise try the
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following:
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1. In the include/configs/EBONY.h file find the line that defines
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the CONFIG_SPD_EEPROM macro and undefine it. E.g:
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#undef CONFIG_SPD_EEPROM
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This will make the code use default SDRAM control register
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settings without using the SPD eeprom.
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2. Rebuild U-Boot
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3. Load the new U-Boot image and reboot ebony.
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4. Repair the SPD eeprom using the 'i2c mm' command. Here's the eeprom
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contents that work with the default SO-DIMM that comes with the
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ebony board (micron 8VDDT164AG-265A1). Note: these are probably
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_not_ the factory settings ... but they work.
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=> i2c md 53 0 10 80
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0000: 80 08 07 0c 0a 01 40 00 04 75 75 00 80 08 00 01 ......@..uu.....
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0010: 0e 04 0c 01 02 20 00 a0 75 00 00 50 3c 50 2d 20 ..... ..u..P<P-
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0020: 90 90 50 50 00 00 00 00 00 41 4b 34 32 75 00 00 ..PP.....AK42u..
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0030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 9c ................
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0040: 2c 00 00 00 00 00 00 00 08 38 56 44 44 54 31 36 ,........8VDDT16
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0050: 36 34 41 47 2d 32 36 35 41 31 20 01 00 01 2c 63 64AG-265A1 ...,c
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0060: 22 25 ab 00 00 00 00 00 00 00 00 00 00 00 00 00 "%..............
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0070: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
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PCI DOUBLE-ENUMERATION WOES
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===========================
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If you're not using PCI-X cards and are simply using 32-bit and/or
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33 MHz cards via extenders and the like, you may notice that the
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initial pci scan reports various devices twice ... and configuration
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does not succeed (one or more devices are enumerated twice). To correct
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this we replaced the 2K ohm resistor on the IDSEL line(s) with a
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22 ohm resistor and the problem went away. This change hasn't broken
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anything yet -- use at your own risk.
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We never tested anything other than 33 MHz/32-bit cards. If you have
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the chance to do this, please let me know how things turn out :-)
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Regards,
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--Scott
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<smcnutt@artesyncp.com>
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@ -1,16 +0,0 @@
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#
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# (C) Copyright 2002
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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PLATFORM_CPPFLAGS += -DCONFIG_440=1
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ifeq ($(debug),1)
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PLATFORM_CPPFLAGS += -DDEBUG
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endif
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ifeq ($(dbcr),1)
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PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
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endif
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@ -1,151 +0,0 @@
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/*
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* Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/processor.h>
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#include <spd_sdram.h>
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#define BOOT_SMALL_FLASH 32 /* 00100000 */
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#define FLASH_ONBD_N 2 /* 00000010 */
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#define FLASH_SRAM_SEL 1 /* 00000001 */
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DECLARE_GLOBAL_DATA_PTR;
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long int fixed_sdram(void);
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int board_early_init_f(void)
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{
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uint reg;
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unsigned char *fpga_base = (unsigned char *)CONFIG_SYS_FPGA_BASE;
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unsigned char status;
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/*--------------------------------------------------------------------
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* Setup the external bus controller/chip selects
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*-------------------------------------------------------------------*/
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mtdcr(EBC0_CFGADDR, EBC0_CFG);
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reg = mfdcr(EBC0_CFGDATA);
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mtdcr(EBC0_CFGDATA, reg | 0x04000000); /* Set ATC */
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mtebc(PB1AP, 0x02815480); /* NVRAM/RTC */
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mtebc(PB1CR, 0x48018000); /* BA=0x480 1MB R/W 8-bit */
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mtebc(PB7AP, 0x01015280); /* FPGA registers */
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mtebc(PB7CR, 0x48318000); /* BA=0x483 1MB R/W 8-bit */
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/* read FPGA_REG0 and set the bus controller */
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status = *fpga_base;
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if ((status & BOOT_SMALL_FLASH) && !(status & FLASH_ONBD_N)) {
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mtebc(PB0AP, 0x9b015480); /* FLASH/SRAM */
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mtebc(PB0CR, 0xfff18000); /* BAS=0xfff 1MB R/W 8-bit */
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mtebc(PB2AP, 0x9b015480); /* 4MB FLASH */
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mtebc(PB2CR, 0xff858000); /* BAS=0xff8 4MB R/W 8-bit */
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} else {
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mtebc(PB0AP, 0x9b015480); /* 4MB FLASH */
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mtebc(PB0CR, 0xffc58000); /* BAS=0xffc 4MB R/W 8-bit */
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/* set CS2 if FLASH_ONBD_N == 0 */
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if (!(status & FLASH_ONBD_N)) {
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mtebc(PB2AP, 0x9b015480); /* FLASH/SRAM */
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mtebc(PB2CR, 0xff818000); /* BAS=0xff8 4MB R/W 8-bit */
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}
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}
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/*--------------------------------------------------------------------
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* Setup the interrupt controller polarities, triggers, etc.
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*-------------------------------------------------------------------*/
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mtdcr(UIC0SR, 0xffffffff); /* clear all */
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mtdcr(UIC0ER, 0x00000000); /* disable all */
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mtdcr(UIC0CR, 0x00000009); /* SMI & UIC1 crit are critical */
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mtdcr(UIC0PR, 0xfffffe13); /* per ref-board manual */
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mtdcr(UIC0TR, 0x01c00008); /* per ref-board manual */
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mtdcr(UIC0VR, 0x00000001); /* int31 highest, base=0x000 */
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mtdcr(UIC0SR, 0xffffffff); /* clear all */
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mtdcr(UIC1SR, 0xffffffff); /* clear all */
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mtdcr(UIC1ER, 0x00000000); /* disable all */
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mtdcr(UIC1CR, 0x00000000); /* all non-critical */
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mtdcr(UIC1PR, 0xffffe0ff); /* per ref-board manual */
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mtdcr(UIC1TR, 0x00ffc000); /* per ref-board manual */
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mtdcr(UIC1VR, 0x00000001); /* int31 highest, base=0x000 */
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mtdcr(UIC1SR, 0xffffffff); /* clear all */
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return 0;
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}
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int checkboard(void)
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{
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char buf[64];
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int i = getenv_f("serial#", buf, sizeof(buf));
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printf("Board: Ebony - AMCC PPC440GP Evaluation Board");
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if (i > 0) {
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puts(", serial# ");
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puts(buf);
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}
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putc('\n');
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return (0);
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}
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phys_size_t initdram(int board_type)
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{
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long dram_size = 0;
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#if defined(CONFIG_SPD_EEPROM)
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dram_size = spd_sdram();
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#else
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dram_size = fixed_sdram();
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#endif
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return dram_size;
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}
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#if !defined(CONFIG_SPD_EEPROM)
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/*************************************************************************
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* fixed sdram init -- doesn't use serial presence detect.
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*
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* Assumes: 128 MB, non-ECC, non-registered
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* PLB @ 133 MHz
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*
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************************************************************************/
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long int fixed_sdram(void)
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{
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uint reg;
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/*--------------------------------------------------------------------
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* Setup some default
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*------------------------------------------------------------------*/
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mtsdram(SDRAM0_UABBA, 0x00000000); /* ubba=0 (default) */
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mtsdram(SDRAM0_SLIO, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
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mtsdram(SDRAM0_DEVOPT, 0x00000000); /* dll=0 ds=0 (normal) */
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mtsdram(SDRAM0_WDDCTR, 0x00000000); /* wrcp=0 dcd=0 */
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mtsdram(SDRAM0_CLKTR, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */
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/*--------------------------------------------------------------------
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* Setup for board-specific specific mem
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*------------------------------------------------------------------*/
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/*
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* Following for CAS Latency = 2.5 @ 133 MHz PLB
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*/
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mtsdram(SDRAM0_B0CR, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */
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mtsdram(SDRAM0_TR0, 0x410a4012); /* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */
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/* RA=10 RD=3 */
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mtsdram(SDRAM0_TR1, 0x8080082f); /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */
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mtsdram(SDRAM0_RTR, 0x08200000); /* Rate 15.625 ns @ 133 MHz PLB */
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mtsdram(SDRAM0_CFG1, 0x00000000); /* Self-refresh exit, disable PM */
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udelay(400); /* Delay 200 usecs (min) */
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/*--------------------------------------------------------------------
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* Enable the controller, then wait for DCEN to complete
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*------------------------------------------------------------------*/
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mtsdram(SDRAM0_CFG0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */
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for (;;) {
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mfsdram(SDRAM0_MCSTS, reg);
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if (reg & 0x80000000)
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break;
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}
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return (128 * 1024 * 1024); /* 128 MB */
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}
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#endif /* !defined(CONFIG_SPD_EEPROM) */
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@ -1,155 +0,0 @@
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/*
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* (C) Copyright 2002
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* (C) Copyright 2002 Jun Gu <jung@artesyncp.com>
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* Add support for Am29F016D and dynamic switch setting.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/*
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* Modified 4/5/2001
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* Wait for completion of each sector erase command issued
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* 4/5/2001
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* Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
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*/
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#include <common.h>
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#include <asm/ppc4xx.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#undef DEBUG
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#ifdef DEBUG
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#define DEBUGF(x...) printf(x)
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#else
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#define DEBUGF(x...)
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#endif /* DEBUG */
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#define BOOT_SMALL_FLASH 32 /* 00100000 */
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#define FLASH_ONBD_N 2 /* 00000010 */
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#define FLASH_SRAM_SEL 1 /* 00000001 */
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#define BOOT_SMALL_FLASH_VAL 4
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#define FLASH_ONBD_N_VAL 2
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#define FLASH_SRAM_SEL_VAL 1
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static unsigned long flash_addr_table[8][CONFIG_SYS_MAX_FLASH_BANKS] = {
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{0xffc00000, 0xffe00000, 0xff880000}, /* 0:000: configuraton 3 */
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{0xffc00000, 0xffe00000, 0xff800000}, /* 1:001: configuraton 4 */
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{0xffc00000, 0xffe00000, 0x00000000}, /* 2:010: configuraton 7 */
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{0xffc00000, 0xffe00000, 0x00000000}, /* 3:011: configuraton 8 */
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{0xff800000, 0xffa00000, 0xfff80000}, /* 4:100: configuraton 1 */
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{0xff800000, 0xffa00000, 0xfff00000}, /* 5:101: configuraton 2 */
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{0xffc00000, 0xffe00000, 0x00000000}, /* 6:110: configuraton 5 */
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{0xffc00000, 0xffe00000, 0x00000000} /* 7:111: configuraton 6 */
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};
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/*
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* include common flash code (for amcc boards)
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*/
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#include "../common/flash.c"
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/*-----------------------------------------------------------------------
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* Functions
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*/
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static ulong flash_get_size(vu_long * addr, flash_info_t * info);
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/*
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* Override the weak default mapping function with a board specific one
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*/
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u32 flash_get_bank_size(int cs, int idx)
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{
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u8 reg = in_8((void *)CONFIG_SYS_FPGA_BASE);
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if ((reg & BOOT_SMALL_FLASH) && !(reg & FLASH_ONBD_N)) {
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/*
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* cs0: small flash (512KiB)
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* cs2: 2 * big flash (2 * 2MiB)
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*/
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if (cs == 0)
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return flash_info[2].size;
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if (cs == 2)
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return flash_info[0].size + flash_info[1].size;
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} else {
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/*
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* cs0: 2 * big flash (2 * 2MiB)
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* cs2: small flash (512KiB)
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*/
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if (cs == 0)
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return flash_info[0].size + flash_info[1].size;
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if (cs == 2)
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return flash_info[2].size;
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}
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return 0;
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}
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unsigned long flash_init(void)
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{
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unsigned long total_b = 0;
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unsigned long size_b[CONFIG_SYS_MAX_FLASH_BANKS];
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unsigned char *fpga_base = (unsigned char *)CONFIG_SYS_FPGA_BASE;
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unsigned char switch_status;
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unsigned short index = 0;
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int i;
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/* read FPGA base register FPGA_REG0 */
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switch_status = *fpga_base;
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/* check the bitmap of switch status */
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if (switch_status & BOOT_SMALL_FLASH) {
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index += BOOT_SMALL_FLASH_VAL;
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}
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if (switch_status & FLASH_ONBD_N) {
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index += FLASH_ONBD_N_VAL;
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}
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if (switch_status & FLASH_SRAM_SEL) {
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index += FLASH_SRAM_SEL_VAL;
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}
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DEBUGF("\n");
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DEBUGF("FLASH: Index: %d\n", index);
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/* Init: no FLASHes known */
|
||||
for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
|
||||
flash_info[i].flash_id = FLASH_UNKNOWN;
|
||||
flash_info[i].sector_count = -1;
|
||||
flash_info[i].size = 0;
|
||||
|
||||
/* check whether the address is 0 */
|
||||
if (flash_addr_table[index][i] == 0) {
|
||||
continue;
|
||||
}
|
||||
|
||||
/* call flash_get_size() to initialize sector address */
|
||||
size_b[i] = flash_get_size((vu_long *)
|
||||
flash_addr_table[index][i],
|
||||
&flash_info[i]);
|
||||
flash_info[i].size = size_b[i];
|
||||
if (flash_info[i].flash_id == FLASH_UNKNOWN) {
|
||||
printf("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
|
||||
i, size_b[i], size_b[i] << 20);
|
||||
flash_info[i].sector_count = -1;
|
||||
flash_info[i].size = 0;
|
||||
}
|
||||
|
||||
/* Monitor protection ON by default */
|
||||
(void)flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE,
|
||||
CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1,
|
||||
&flash_info[2]);
|
||||
#ifdef CONFIG_ENV_IS_IN_FLASH
|
||||
(void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR,
|
||||
CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
|
||||
&flash_info[2]);
|
||||
(void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND,
|
||||
CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
|
||||
&flash_info[2]);
|
||||
#endif
|
||||
|
||||
total_b += flash_info[i].size;
|
||||
}
|
||||
|
||||
return total_b;
|
||||
}
|
||||
@ -1,41 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <ppc_asm.tmpl>
|
||||
#include <config.h>
|
||||
#include <asm/mmu.h>
|
||||
#include <asm/ppc4xx.h>
|
||||
|
||||
/**************************************************************************
|
||||
* TLB TABLE
|
||||
*
|
||||
* This table is used by the cpu boot code to setup the initial tlb
|
||||
* entries. Rather than make broad assumptions in the cpu source tree,
|
||||
* this table lets each board set things up however they like.
|
||||
*
|
||||
* Pointer to the table is returned in r1
|
||||
*
|
||||
*************************************************************************/
|
||||
|
||||
.section .bootpg,"ax"
|
||||
.globl tlbtab
|
||||
|
||||
tlbtab:
|
||||
tlbtab_start
|
||||
|
||||
tlbentry(0xf0000000, SZ_256M, 0xf0000000, 1, AC_RWX | SA_IG)
|
||||
|
||||
/*
|
||||
* TLB entries for SDRAM are not needed on this platform.
|
||||
* They are dynamically generated in the SPD DDR(2) detection
|
||||
* routine.
|
||||
*/
|
||||
|
||||
tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_RW | SA_IG)
|
||||
tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_RWX)
|
||||
tlbentry(CONFIG_SYS_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_RWX)
|
||||
tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_RW | SA_IG)
|
||||
tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_RW | SA_IG)
|
||||
tlbtab_end
|
||||
@ -1,3 +0,0 @@
|
||||
CONFIG_PPC=y
|
||||
CONFIG_4xx=y
|
||||
CONFIG_TARGET_EBONY=y
|
||||
@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order.
|
||||
|
||||
Board Arch CPU Commit Removed Last known maintainer/contact
|
||||
=================================================================================================
|
||||
ebony powerpc ppc4xx - - Stefan Roese <sr@denx.de>
|
||||
taihu powerpc ppc4xx - - John Otken <jotken@softadvances.com>
|
||||
lcd4_lwmon5 powerpc ppc4xx b6b5e394 2015-10-02 Stefan Roese <sr@denx.de>
|
||||
da830evm arm arm926ejs d7e8b2b9 2015-09-12 Nick Thompson <nick.thompson@gefanuc.com>
|
||||
|
||||
@ -1,174 +0,0 @@
|
||||
/*
|
||||
* (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
/************************************************************************
|
||||
* board/config_EBONY.h - configuration for AMCC 440GP Ref (Ebony)
|
||||
***********************************************************************/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* High Level Configuration Options
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CONFIG_EBONY 1 /* Board is ebony */
|
||||
#define CONFIG_440GP 1 /* Specifc GP support */
|
||||
#define CONFIG_440 1 /* ... PPC440 family */
|
||||
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
|
||||
#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
|
||||
|
||||
#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
|
||||
|
||||
/*
|
||||
* Include common defines/options for all AMCC eval boards
|
||||
*/
|
||||
#define CONFIG_HOSTNAME ebony
|
||||
#include "amcc-common.h"
|
||||
|
||||
/*
|
||||
* Define here the location of the environment variables (FLASH or NVRAM).
|
||||
* Note: DENX encourages to use redundant environment in FLASH. NVRAM is only
|
||||
* supported for backward compatibility.
|
||||
*/
|
||||
#if 1
|
||||
#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
|
||||
#else
|
||||
#define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Base addresses -- Note these are effective addresses where the
|
||||
* actual resources get mapped (not physical addresses)
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */
|
||||
#define CONFIG_SYS_FLASH_BASE 0xff800000 /* start of FLASH */
|
||||
#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */
|
||||
#define CONFIG_SYS_ISRAM_BASE 0xc0000000 /* internal SRAM */
|
||||
#define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */
|
||||
|
||||
#define CONFIG_SYS_NVRAM_BASE_ADDR (CONFIG_SYS_PERIPHERAL_BASE + 0x08000000)
|
||||
#define CONFIG_SYS_FPGA_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x08300000)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Initial RAM & stack pointer (placed in internal SRAM)
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE /* Initial RAM address */
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */
|
||||
|
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Serial Port
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CONFIG_CONS_INDEX 1 /* Use UART0 */
|
||||
#define CONFIG_SYS_EXT_SERIAL_CLOCK (1843200 * 6) /* Ext clk @ 11.059 MHz */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* NVRAM/RTC
|
||||
*
|
||||
* NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located.
|
||||
* The DS1743 code assumes this condition (i.e. -- it assumes the base
|
||||
* address for the RTC registers is:
|
||||
*
|
||||
* CONFIG_SYS_NVRAM_BASE_ADDR + CONFIG_SYS_NVRAM_SIZE
|
||||
*
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CONFIG_SYS_NVRAM_SIZE (0x2000 - 8) /* NVRAM size(8k)- RTC regs */
|
||||
#define CONFIG_RTC_DS174x 1 /* DS1743 RTC */
|
||||
|
||||
#ifdef CONFIG_ENV_IS_IN_NVRAM
|
||||
#define CONFIG_ENV_SIZE 0x1000 /* Size of Environment vars */
|
||||
#define CONFIG_ENV_ADDR \
|
||||
(CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE)
|
||||
#endif /* CONFIG_ENV_IS_IN_NVRAM */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH related
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 3 /* number of banks */
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 32 /* sectors per device */
|
||||
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
|
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
|
||||
|
||||
#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
|
||||
|
||||
#define CONFIG_SYS_FLASH_ADDR0 0x5555
|
||||
#define CONFIG_SYS_FLASH_ADDR1 0x2aaa
|
||||
#define CONFIG_SYS_FLASH_WORD_SIZE unsigned char
|
||||
|
||||
#ifdef CONFIG_ENV_IS_IN_FLASH
|
||||
#define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
|
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
|
||||
#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
|
||||
|
||||
/* Address and size of Redundant Environment Sector */
|
||||
#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
|
||||
#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
|
||||
#endif /* CONFIG_ENV_IS_IN_FLASH */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* DDR SDRAM
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */
|
||||
#define SPD_EEPROM_ADDRESS {0x53,0x52} /* SPD i2c spd addresses */
|
||||
#define CONFIG_PROG_SDRAM_TLB 1 /* setup SDRAM TLB's dynamically*/
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* I2C
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
|
||||
|
||||
#define CONFIG_SYS_I2C_MULTI_EEPROMS
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1)
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
|
||||
|
||||
/*
|
||||
* Default environment variables
|
||||
*/
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
CONFIG_AMCC_DEF_ENV \
|
||||
CONFIG_AMCC_DEF_ENV_POWERPC \
|
||||
CONFIG_AMCC_DEF_ENV_PPC_OLD \
|
||||
CONFIG_AMCC_DEF_ENV_NOR_UPD \
|
||||
"kernel_addr=ff800000\0" \
|
||||
"ramdisk_addr=ff810000\0" \
|
||||
""
|
||||
|
||||
#define CONFIG_PHY_ADDR 8 /* PHY address */
|
||||
#define CONFIG_HAS_ETH0
|
||||
#define CONFIG_HAS_ETH1
|
||||
#define CONFIG_PHY1_ADDR 9 /* EMAC1 PHY address */
|
||||
|
||||
/*
|
||||
* Commands additional to the ones defined in amcc-common.h
|
||||
*/
|
||||
#define CONFIG_CMD_DATE
|
||||
#define CONFIG_CMD_PCI
|
||||
#define CONFIG_CMD_SDRAM
|
||||
#define CONFIG_CMD_SNTP
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PCI stuff
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
/* General PCI */
|
||||
#define CONFIG_PCI /* include pci support */
|
||||
#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
|
||||
#define CONFIG_PCI_PNP /* do pci plug-and-play */
|
||||
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
|
||||
#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */
|
||||
|
||||
/* Board-specific PCI */
|
||||
#define CONFIG_SYS_PCI_TARGET_INIT /* let board init pci target */
|
||||
|
||||
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
|
||||
#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
Loading…
Reference in New Issue
Block a user