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First set of u-boot-atmel features and fixes for 2020.01 cycle

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Merge tag 'u-boot-atmel-2020.01-a' of https://gitlab.denx.de/u-boot/custodians/u-boot-atmel

First set of u-boot-atmel features and fixes for 2020.01 cycle

The feature set includes support for two new boards from Microchip AT91:
The sama5d27_wlsom1_ek , an evaluation kit which includes the SAMA5D2
SOC packaged in a 256 MB LPDDR2 SIP, on a SOM including wireless, which
is placed on evaluation kit with sd-card, ethernet, LCD, Camera sensor,
QSPI, etc
The sam9x60ek, an evaluation kit for the new SoC based on ARM926j , the
SAM9X60 . The evaluation kit includes NAND flash, QSPI, Ethernet, Audio,
Camera sensor connector, etc.
The full support for sam9x60ek will come at a later time. There are
still missing bits regarding the clock support and power management
controller.
This commit is contained in:
Tom Rini 2019-10-08 18:43:56 -04:00
commit 9d536fe8ae
42 changed files with 2386 additions and 16 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
arch/arm/dts/Makefile
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@ -691,6 +691,8 @@ dtb-$(CONFIG_TARGET_AT91SAM9X5EK) += \
at91sam9x25ek.dtb \
at91sam9x35ek.dtb
dtb-$(CONFIG_TARGET_SAM9X60EK) += sam9x60ek.dtb
dtb-$(CONFIG_TARGET_AT91SAM9N12EK) += at91sam9n12ek.dtb
dtb-$(CONFIG_TARGET_GARDENA_SMART_GATEWAY_AT91SAM) += \
@ -727,6 +729,9 @@ dtb-$(CONFIG_TARGET_SAMA5D2_XPLAINED) += \
dtb-$(CONFIG_TARGET_SAMA5D27_SOM1_EK) += \
at91-sama5d27_som1_ek.dtb
dtb-$(CONFIG_TARGET_SAMA5D27_WLSOM1_EK) += \
at91-sama5d27_wlsom1_ek.dtb
dtb-$(CONFIG_TARGET_SAMA5D2_ICP) += \
at91-sama5d2_icp.dtb

54
arch/arm/dts/at91-sama5d27_wlsom1_ek-u-boot.dtsi Normal file
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@ -0,0 +1,54 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* at91-sama5d27_wlsom1_ek-u-boot.dts - Device Tree file for SAMA5D27 WLSOM1 EK
*
* Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries
*
* Author: Eugen Hristev <eugen.hristev@microchip.com>
*/
/ {
chosen {
u-boot,dm-pre-reloc;
};
};
&hlcdc {
u-boot,dm-pre-reloc;
};
&qspi1 {
u-boot,dm-pre-reloc;
};
&qspi1_flash {
u-boot,dm-pre-reloc;
};
&sdmmc0 {
u-boot,dm-pre-reloc;
};
&uart0 {
u-boot,dm-pre-reloc;
};
&sfr {
u-boot,dm-pre-reloc;
};
&pinctrl_sdmmc0_cmd_dat_default {
u-boot,dm-pre-reloc;
};
&pinctrl_sdmmc0_ck_cd_default {
u-boot,dm-pre-reloc;
};
&pinctrl_uart0_default {
u-boot,dm-pre-reloc;
};
&pinctrl_qspi1_default {
u-boot,dm-pre-reloc;
};

148
arch/arm/dts/at91-sama5d27_wlsom1_ek.dts Normal file
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@ -0,0 +1,148 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* at91-sama5d27_wlsom1_ek.dts - Device Tree file for SAMA5D27 WLSOM1 EK
*
* Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries
*
* Author: Nicolas Ferre <nicolas.ferre@microcihp.com>
*/
/dts-v1/;
#include "sama5d27_wlsom1.dtsi"
/ {
model = "Microchip SAMA5D27 WLSOM1 EK";
compatible = "microchip,sama5d27-wlsom1-ek", "microchip,sama5d27-wlsom1", "atmel,sama5d2", "atmel,sama5";
chosen {
stdout-path = &uart0;
};
onewire_tm: onewire {
gpios = <&pioA PIN_PC9 0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_onewire_tm_default>;
status = "okay";
w1_eeprom: w1_eeprom@0 {
compatible = "maxim,ds24b33";
status = "okay";
};
};
ahb {
sdmmc0: sdio-host@a0000000 {
bus-width = <4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sdmmc0_cmd_dat_default &pinctrl_sdmmc0_ck_cd_default>;
status = "okay";
};
apb {
hlcdc: hlcdc@f0000000 {
atmel,vl-bpix = <4>;
atmel,output-mode = <24>;
atmel,guard-time = <1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_pwm &pinctrl_lcd_rgb666>;
status = "okay";
display-timings {
800x480 {
clock-frequency = <33300000>;
xres = <800>;
yres = <480>;
hactive = <800>;
vactive = <480>;
hsync-len = <64>;
hfront-porch = <1>;
hback-porch = <64>;
vfront-porch = <1>;
vback-porch = <22>;
vsync-len = <23>;
};
};
};
qspi1: spi@f0024000 {
status = "okay";
};
macb0: ethernet@f8008000 {
status = "okay";
};
uart0: serial@f801c000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0_default>;
status = "okay";
};
pioA: gpio@fc038000 {
pinctrl {
pinctrl_lcd_base: pinctrl_lcd_base {
pinmux = <PIN_PC30__LCDVSYNC>,
<PIN_PC31__LCDHSYNC>,
<PIN_PD1__LCDDEN>,
<PIN_PD0__LCDPCK>;
bias-disable;
};
pinctrl_lcd_pwm: pinctrl_lcd_pwm {
pinmux = <PIN_PC28__LCDPWM>;
bias-disable;
};
pinctrl_lcd_rgb666: pinctrl_lcd_rgb666 {
pinmux = <PIN_PC10__LCDDAT2>,
<PIN_PC11__LCDDAT3>,
<PIN_PC12__LCDDAT4>,
<PIN_PC13__LCDDAT5>,
<PIN_PC14__LCDDAT6>,
<PIN_PC15__LCDDAT7>,
<PIN_PC16__LCDDAT10>,
<PIN_PC17__LCDDAT11>,
<PIN_PC18__LCDDAT12>,
<PIN_PC19__LCDDAT13>,
<PIN_PC20__LCDDAT14>,
<PIN_PC21__LCDDAT15>,
<PIN_PC22__LCDDAT18>,
<PIN_PC23__LCDDAT19>,
<PIN_PC24__LCDDAT20>,
<PIN_PC25__LCDDAT21>,
<PIN_PC26__LCDDAT22>,
<PIN_PC27__LCDDAT23>;
bias-disable;
};
pinctrl_sdmmc0_cmd_dat_default: sdmmc0_cmd_dat_default {
pinmux = <PIN_PA1__SDMMC0_CMD>,
<PIN_PA2__SDMMC0_DAT0>,
<PIN_PA3__SDMMC0_DAT1>,
<PIN_PA4__SDMMC0_DAT2>,
<PIN_PA5__SDMMC0_DAT3>;
bias-disable;
};
pinctrl_sdmmc0_ck_cd_default: sdmmc0_ck_cd_default {
pinmux = <PIN_PA0__SDMMC0_CK>,
<PIN_PA11__SDMMC0_VDDSEL>,
<PIN_PA12__SDMMC0_WP>,
<PIN_PA13__SDMMC0_CD>;
bias-disable;
};
pinctrl_uart0_default: uart0_default {
pinmux = <PIN_PB26__URXD0>,
<PIN_PB27__UTXD0>;
bias-disable;
};
pinctrl_onewire_tm_default: onewire_tm_default {
pinmux = <PIN_PC9__GPIO>;
bias-pull-up;
};
};
};
};
};
};

304
arch/arm/dts/sam9x60.dtsi Normal file
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@ -0,0 +1,304 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* sam9x60.dtsi - Device Tree Include file for SAM9X60 SoC.
*
* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries
*
* Author: Sandeep Sheriker M <sandeepsheriker.mallikarjun@microchip.com>
*/
#include "skeleton.dtsi"
#include <dt-bindings/dma/at91.h>
#include <dt-bindings/pinctrl/at91.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clock/at91.h>
/{
model = "Microchip SAM9X60 SoC";
compatible = "microchip,sam9x60";
aliases {
serial0 = &dbgu;
gpio0 = &pioA;
gpio1 = &pioB;
gpio3 = &pioD;
spi0 = &qspi;
};
clocks {
slow_xtal: slow_xtal {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
main_xtal: main_xtal {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
};
ahb {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
sdhci0: sdhci-host@80000000 {
compatible = "microchip,sam9x60-sdhci";
reg = <0x80000000 0x300>;
clocks = <&sdhci0_clk>, <&sdhci0_gclk>, <&main>;
clock-names = "hclock", "multclk", "baseclk";
bus-width = <4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sdhci0>;
};
apb {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
qspi: spi@f0014000 {
compatible = "microchip,sam9x60-qspi";
reg = <0xf0014000 0x100>, <0x70000000 0x10000000>;
reg-names = "qspi_base", "qspi_mmap";
clocks = <&qspi_clk>, <&qspick>;
clock-names = "pclk", "qspick";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
macb0: ethernet@f802c000 {
compatible = "cdns,sam9x60-macb", "cdns,macb";
reg = <0xf802c000 0x100>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_macb0_rmii>;
clock-names = "hclk", "pclk";
clocks = <&macb0_clk>, <&macb0_clk>;
status = "disabled";
};
dbgu: serial@fffff200 {
compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
reg = <0xfffff200 0x200>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_dbgu>;
clocks = <&dbgu_clk>;
clock-names = "usart";
};
pinctrl {
#address-cells = <1>;
#size-cells = <1>;
compatible = "microchip,sam9x60-pinctrl", "simple-bus";
ranges = <0xfffff400 0xfffff400 0x800>;
reg = <0xfffff400 0x200 /* pioA */
0xfffff600 0x200 /* pioB */
0xfffff800 0x200 /* pioC */
0xfffffa00 0x200>; /* pioD */
/* shared pinctrl settings */
dbgu {
pinctrl_dbgu: dbgu-0 {
atmel,pins =
<AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE>;
};
};
macb0 {
pinctrl_macb0_rmii: macb0_rmii-0 {
atmel,pins =
<AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A */
AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A */
AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB2 periph A */
AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB3 periph A */
AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB4 periph A */
AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB5 periph A */
AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB6 periph A */
AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB7 periph A */
AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A */
AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB10 periph A */
};
};
sdhci0 {
pinctrl_sdhci0: sdhci0 {
atmel,pins =
<AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_DRIVE_STRENGTH_DEFAULT /* PA17 CK periph A with pullup */
AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA16 CMD periph A with pullup */
AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA15 DAT0 periph A */
AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA18 DAT1 periph A with pullup */
AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA19 DAT2 periph A with pullup */
AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA20 DAT3 periph A with pullup */
};
};
};
pioA: gpio@fffff400 {
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
reg = <0xfffff400 0x200>;
#gpio-cells = <2>;
gpio-controller;
clocks = <&pioA_clk>;
};
pioB: gpio@fffff600 {
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
reg = <0xfffff600 0x200>;
#gpio-cells = <2>;
gpio-controller;
clocks = <&pioB_clk>;
};
pioD: gpio@fffffa00 {
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
reg = <0xfffffa00 0x200>;
#gpio-cells = <2>;
gpio-controller;
clocks = <&pioD_clk>;
};
pmc: pmc@fffffc00 {
compatible = "atmel,at91sam9x5-pmc";
reg = <0xfffffc00 0x200>;
#address-cells = <1>;
#size-cells = <0>;
main: mainck {
compatible = "atmel,at91sam9x5-clk-main";
#clock-cells = <0>;
};
plla: pllack {
compatible = "microchip,sam9x60-clk-pll";
#clock-cells = <0>;
clocks = <&main>;
reg = <0>;
atmel,clk-input-range = <8000000 24000000>;
#atmel,pll-clk-output-range-cells = <4>;
atmel,pll-clk-output-ranges = <140000000 1200000000 0 0>;
};
mck: masterck {
compatible = "atmel,at91sam9x5-clk-master";
#clock-cells = <0>;
clocks = <&md_slck>, <&main>, <&plla>;
atmel,clk-output-range = <140000000 200000000>;
atmel,clk-divisors = <1 2 4 6>;
};
system: systemck {
compatible = "atmel,at91rm9200-clk-system";
#address-cells = <1>;
#size-cells = <0>;
qspick: qspick {
#clock-cells = <0>;
reg = <19>;
clocks = <&mck>;
};
};
periph: periphck {
compatible = "microchip,sam9x60-clk-peripheral";
#address-cells = <1>;
#size-cells = <0>;
clocks = <&mck>;
pioA_clk: pioA_clk {
#clock-cells = <0>;
reg = <2>;
};
pioB_clk: pioB_clk {
#clock-cells = <0>;
reg = <3>;
};
pioD_clk: pioD_clk {
#clock-cells = <0>;
reg = <44>;
};
sdhci0_clk: sdhci0_clk {
#clock-cells = <0>;
reg = <12>;
};
dbgu_clk: dbgu_clk {
#clock-cells = <0>;
reg = <47>;
};
macb0_clk: macb0_clk {
#clock-cells = <0>;
reg = <24>;
};
qspi_clk: qspi_clk {
#clock-cells = <0>;
reg = <35>;
};
};
generic: gck {
compatible = "microchip,sam9x60-clk-generated";
#address-cells = <1>;
#size-cells = <0>;
clocks = <&md_slck>, <&td_slck>, <&main>, <&mck>, <&plla>;
sdhci0_gclk: sdhci0_gclk {
#clock-cells = <0>;
reg = <12>;
};
};
};
pit: timer@fffffe40 {
compatible = "atmel,at91sam9260-pit";
reg = <0xfffffe40 0x10>;
clocks = <&mck>;
};
slowckc: sckc@fffffe50 {
compatible = "atmel,at91sam9x5-sckc";
reg = <0xfffffe50 0x4>;
slow_osc: slow_osc {
compatible = "atmel,at91sam9x5-clk-slow-osc";
#clock-cells = <0>;
clocks = <&slow_xtal>;
};
slow_rc_osc: slow_rc_osc {
compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
#clock-cells = <0>;
clock-frequency = <32768>;
};
td_slck: td_slck {
compatible = "atmel,at91sam9x5-clk-slow";
#clock-cells = <0>;
clocks = <&slow_rc_osc>, <&slow_osc>;
};
md_slck: md_slck {
compatible = "atmel,at91sam9x5-clk-slow";
#clock-cells = <0>;
clocks = <&slow_rc_osc>;
};
};
};
};
onewire_tm: onewire {
compatible = "w1-gpio";
status = "disabled";
};
};

132
arch/arm/dts/sam9x60ek-u-boot.dtsi Normal file
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@ -0,0 +1,132 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* sam9x60-u-boot.dts - Device Tree file for SAM9X60 SoC.
*
* Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries
*/
/ {
chosen {
u-boot,dm-pre-reloc;
};
ahb {
u-boot,dm-pre-reloc;
apb {
u-boot,dm-pre-reloc;
pinctrl {
u-boot,dm-pre-reloc;
};
};
};
};
&sdhci0 {
u-boot,dm-pre-reloc;
};
&dbgu {
u-boot,dm-pre-reloc;
};
&qspi {
u-boot,dm-pre-reloc;
};
&pinctrl_dbgu {
u-boot,dm-pre-reloc;
};
&pinctrl_sdhci0 {
u-boot,dm-pre-reloc;
};
&pinctrl_qspi {
u-boot,dm-pre-reloc;
};
&pioA {
u-boot,dm-pre-reloc;
};
&pioB {
u-boot,dm-pre-reloc;
};
&pmc {
u-boot,dm-pre-reloc;
};
&main {
u-boot,dm-pre-reloc;
};
&plla {
u-boot,dm-pre-reloc;
};
&mck {
u-boot,dm-pre-reloc;
};
&system {
u-boot,dm-pre-reloc;
};
&qspick {
u-boot,dm-pre-reloc;
};
&periph {
u-boot,dm-pre-reloc;
};
&pioA_clk {
u-boot,dm-pre-reloc;
};
&pioB_clk {
u-boot,dm-pre-reloc;
};
&sdhci0_clk {
u-boot,dm-pre-reloc;
};
&dbgu_clk {
u-boot,dm-pre-reloc;
};
&qspi_clk {
u-boot,dm-pre-reloc;
};
&generic {
u-boot,dm-pre-reloc;
};
&sdhci0_gclk {
u-boot,dm-pre-reloc;
};
&slowckc {
u-boot,dm-pre-reloc;
};
&slow_osc {
u-boot,dm-pre-reloc;
};
&slow_rc_osc {
u-boot,dm-pre-reloc;
};
&td_slck {
u-boot,dm-pre-reloc;
};
&md_slck {
u-boot,dm-pre-reloc;
};

72
arch/arm/dts/sam9x60ek.dts Normal file
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@ -0,0 +1,72 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* sam9x60ek.dts - Device Tree file for SAM9X60 EK board
*
* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries
*
* Author: Sandeep Sheriker M <Sandeepsheriker.mallikarjun@microchip.com>
*/
/dts-v1/;
#include "sam9x60.dtsi"
/ {
model = "Microchip SAM9X60-Ek";
compatible = "microchip,sam9x60ek", "microchip,sam9x60", "atmel,at91sam9";
chosen {
stdout-path = &dbgu;
};
onewire_tm: onewire {
gpios = <&pioD 14 0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_onewire_tm_default>;
status = "okay";
w1_eeprom: w1_eeprom@0 {
compatible = "maxim,ds24b33";
status = "okay";
};
};
ahb {
apb {
qspi: spi@f0014000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_qspi>;
status = "okay";
nor_flash: sst26vf064@0 {
compatible = "spi-flash";
reg = <0>;
spi-max-frequency = <80000000>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <4>;
};
};
pinctrl {
pinctrl_qspi: qspi {
atmel,pins =
<AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_NONE
AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_NONE
AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
AT91_PIOB 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
AT91_PIOB 23 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
};
pinctrl_onewire_tm_default: onewire_tm_default {
atmel,pins =
<AT91_PIOD 14 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
};
};
};
};
};
&macb0 {
phy-mode = "rmii";
status = "okay";
};

1
arch/arm/dts/sama5d2.dtsi
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@ -7,6 +7,7 @@
aliases {
spi0 = &spi0;
spi1 = &qspi0;
spi2 = &qspi1;
i2c0 = &i2c0;
i2c1 = &i2c1;
};

78
arch/arm/dts/sama5d27_wlsom1.dtsi Normal file
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@ -0,0 +1,78 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* sama5d27_wlsom1.dtsi - Device Tree file for SAMA5D27 WLSOM1
*
* Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries
*
* Author: Nicolas Ferre <nicolas.ferre@microcihp.com>
*/
#include "sama5d2.dtsi"
#include "sama5d2-pinfunc.h"
/ {
model = "Microchip SAMA5D27 WLSOM1";
compatible = "microchip,sama5d27-wlsom1", "atmel,sama5d2", "atmel,sama5";
memory {
reg = <0x20000000 0x10000000>;
};
ahb {
apb {
qspi1: spi@f0024000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_qspi1_default>;
qspi1_flash: spi_flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <50000000>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <4>;
};
};
macb0: ethernet@f8008000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_macb0_rmii &pinctrl_macb0_phy_irq>;
phy-mode = "rmii";
ethernet-phy@0 {
reg = <0x0>;
};
};
pioA: gpio@fc038000 {
pinctrl {
pinctrl_macb0_phy_irq: macb0_phy_irq {
pinmux = <PIN_PB24__GPIO>;
bias-disable;
};
pinctrl_macb0_rmii: macb0_rmii {
pinmux = <PIN_PB14__GTXCK>,
<PIN_PB15__GTXEN>,
<PIN_PB16__GRXDV>,
<PIN_PB17__GRXER>,
<PIN_PB18__GRX0>,
<PIN_PB19__GRX1>,
<PIN_PB20__GTX0>,
<PIN_PB21__GTX1>,
<PIN_PB22__GMDC>,
<PIN_PB23__GMDIO>;
bias-disable;
};
pinctrl_qspi1_default: qspi1_default {
pinmux = <PIN_PB5__QSPI1_SCK>,
<PIN_PB6__QSPI1_CS>,
<PIN_PB7__QSPI1_IO0>,
<PIN_PB8__QSPI1_IO1>,
<PIN_PB9__QSPI1_IO2>,
<PIN_PB10__QSPI1_IO3>;
bias-pull-up;
};
};
};
};
};
};

37
arch/arm/mach-at91/Kconfig
View File

@ -43,9 +43,14 @@ config AT91SAM9X5
bool
select CPU_ARM926EJS
config SAM9X60
bool
select CPU_ARM926EJS
config SAMA5D2
bool
select CPU_V7A
select ATMEL_SFR
config SAMA5D3
bool
@ -54,6 +59,7 @@ config SAMA5D3
config SAMA5D4
bool
select CPU_V7A
select ATMEL_SFR
choice
prompt "Atmel AT91 board select"
@ -154,6 +160,12 @@ config TARGET_GARDENA_SMART_GATEWAY_AT91SAM
select BOARD_LATE_INIT
select SUPPORT_SPL
config TARGET_SAM9X60EK
bool "SAM9X60-EK board"
select SAM9X60
select BOARD_EARLY_INIT_F
select BOARD_LATE_INIT
config TARGET_SAMA5D2_PTC_EK
bool "SAMA5D2 PTC EK board"
select BOARD_EARLY_INIT_F
@ -173,6 +185,7 @@ config TARGET_SAMA5D27_SOM1_EK
select BOARD_LATE_INIT
select CPU_V7A
select SUPPORT_SPL
select ATMEL_SFR
help
The SAMA5D27 SOM1 embeds SAMA5D2 SiP(System in Package),
a 64Mbit QSPI flash, KSZ8081 Phy and a Mac-address EEPROM
@ -180,9 +193,24 @@ config TARGET_SAMA5D27_SOM1_EK
processor-based SAMA5D2 MPU with up to 1 Gbit DDR2-SDRAM
in a single package.
config TARGET_SAMA5D27_WLSOM1_EK
bool "SAMA5D27 WLSOM1 EK board"
select SAMA5D2
select BOARD_EARLY_INIT_F
select BOARD_LATE_INIT
select CPU_V7A
select SUPPORT_SPL
help
The SAMA5D27 WLSOM1 embeds SAMA5D2 SiP (System in Package),
a 64Mbit QSPI flash with Mac-address, KSZ8081 Phy. A wireless
module providing bluetooth and wifi is also embedded.
The SAMA5D2 SiP integrates the ARM Cortex-A5
processor-based SAMA5D2 MPU with 2 Gbit LPDDR2-SDRAM
in a single package.
config TARGET_SAMA5D2_ICP
bool "SAMA5D2 Industrial Connectivity Platform (ICP)"
select CPU_V7A
select SAMA5D2
select SUPPORT_SPL
select BOARD_EARLY_INIT_F
select BOARD_LATE_INIT
@ -275,9 +303,14 @@ config TARGET_WB50N
select BOARD_LATE_INIT
select CPU_V7A
select SUPPORT_SPL
select ATMEL_SFR
endchoice
config ATMEL_SFR
bool
default n
config SYS_SOC
default "at91"
@ -289,9 +322,11 @@ source "board/atmel/at91sam9m10g45ek/Kconfig"
source "board/atmel/at91sam9n12ek/Kconfig"
source "board/atmel/at91sam9rlek/Kconfig"
source "board/atmel/at91sam9x5ek/Kconfig"
source "board/atmel/sam9x60ek/Kconfig"
source "board/atmel/sama5d2_ptc_ek/Kconfig"
source "board/atmel/sama5d2_xplained/Kconfig"
source "board/atmel/sama5d27_som1_ek/Kconfig"
source "board/atmel/sama5d27_wlsom1_ek/Kconfig"
source "board/atmel/sama5d2_icp/Kconfig"
source "board/atmel/sama5d3_xplained/Kconfig"
source "board/atmel/sama5d3xek/Kconfig"

5
arch/arm/mach-at91/Makefile
View File

@ -7,10 +7,11 @@ obj-$(CONFIG_AT91SAM9G20) += sdram.o spl_at91.o
obj-$(CONFIG_AT91SAM9M10G45) += mpddrc.o spl_at91.o
obj-$(CONFIG_AT91SAM9N12) += mpddrc.o spl_at91.o
obj-$(CONFIG_AT91SAM9X5) += mpddrc.o spl_at91.o
obj-$(CONFIG_SAMA5D2) += bootparams_atmel.o mpddrc.o spl_atmel.o matrix.o atmel_sfr.o
obj-$(CONFIG_SAMA5D2) += bootparams_atmel.o mpddrc.o spl_atmel.o matrix.o
obj-$(CONFIG_SAMA5D3) += bootparams_atmel.o mpddrc.o spl_atmel.o
obj-$(CONFIG_SAMA5D4) += bootparams_atmel.o mpddrc.o spl_atmel.o matrix.o atmel_sfr.o
obj-$(CONFIG_SAMA5D4) += bootparams_atmel.o mpddrc.o spl_atmel.o matrix.o
obj-y += spl.o
obj-$(CONFIG_ATMEL_SFR) += atmel_sfr.o
endif
obj-y += clock.o

1
arch/arm/mach-at91/arm926ejs/Makefile
View File

@ -14,6 +14,7 @@ obj-$(CONFIG_AT91SAM9M10G45) += at91sam9m10g45_devices.o
obj-$(CONFIG_AT91SAM9G45) += at91sam9m10g45_devices.o
obj-$(CONFIG_AT91SAM9N12) += at91sam9n12_devices.o
obj-$(CONFIG_AT91SAM9X5) += at91sam9x5_devices.o
obj-$(CONFIG_SAM9X60) += sam9x60_devices.o
obj-$(CONFIG_AT91_EFLASH) += eflash.o
obj-$(CONFIG_AT91_LED) += led.o
obj-y += clock.o

125
arch/arm/mach-at91/arm926ejs/sam9x60_devices.c Normal file
View File

@ -0,0 +1,125 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries
*/
#include <common.h>
#include <asm/arch/at91_common.h>
#include <asm/arch/clk.h>
#include <asm/arch/gpio.h>
#include <asm/io.h>
unsigned int get_chip_id(void)
{
/* The 0x40 is the offset of cidr in DBGU */
return readl(ATMEL_BASE_DBGU + 0x40) & ~ARCH_ID_VERSION_MASK;
}
unsigned int get_extension_chip_id(void)
{
/* The 0x44 is the offset of exid in DBGU */
return readl(ATMEL_BASE_DBGU + 0x44);
}
unsigned int has_emac1(void)
{
return cpu_is_sam9x60();
}
unsigned int has_emac0(void)
{
return cpu_is_sam9x60();
}
unsigned int has_lcdc(void)
{
return cpu_is_sam9x60();
}
char *get_cpu_name(void)
{
unsigned int extension_id = get_extension_chip_id();
if (cpu_is_sam9x60()) {
switch (extension_id) {
case ARCH_EXID_SAM9X60:
return "SAM9X60";
default:
return "Unknown CPU type";
}
} else {
return "Unknown CPU type";
}
}
void at91_seriald_hw_init(void)
{
at91_pio3_set_a_periph(AT91_PIO_PORTA, 9, 1); /* DRXD */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 10, 1); /* DTXD */
at91_periph_clk_enable(ATMEL_ID_DBGU);
}
void at91_mci_hw_init(void)
{
/* Initialize the SDMMC0 */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 17, 1); /* CLK */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 16, 1); /* CMD */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 15, 1); /* DAT0 */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 18, 1); /* DAT1 */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 19, 1); /* DAT2 */
at91_pio3_set_a_periph(AT91_PIO_PORTA, 20, 1); /* DAT3 */
at91_periph_clk_enable(ATMEL_ID_SDMMC0);
}
#ifdef CONFIG_MACB
void at91_macb_hw_init(void)
{
if (has_emac0()) {
/* Enable EMAC0 clock */
at91_periph_clk_enable(ATMEL_ID_EMAC0);
/* EMAC0 pins setup */
at91_pio3_set_a_periph(AT91_PIO_PORTB, 4, 0); /* ETXCK */
at91_pio3_set_a_periph(AT91_PIO_PORTB, 3, 0); /* ERXDV */
at91_pio3_set_a_periph(AT91_PIO_PORTB, 0, 0); /* ERX0 */
at91_pio3_set_a_periph(AT91_PIO_PORTB, 1, 0); /* ERX1 */
at91_pio3_set_a_periph(AT91_PIO_PORTB, 2, 0); /* ERXER */
at91_pio3_set_a_periph(AT91_PIO_PORTB, 7, 0); /* ETXEN */
at91_pio3_set_a_periph(AT91_PIO_PORTB, 9, 0); /* ETX0 */
at91_pio3_set_a_periph(AT91_PIO_PORTB, 10, 0); /* ETX1 */
at91_pio3_set_a_periph(AT91_PIO_PORTB, 5, 0); /* EMDIO */
at91_pio3_set_a_periph(AT91_PIO_PORTB, 6, 0); /* EMDC */
}
if (has_emac1()) {
/* Enable EMAC1 clock */
at91_periph_clk_enable(ATMEL_ID_EMAC1);
/* EMAC1 pins setup */
at91_pio3_set_b_periph(AT91_PIO_PORTC, 29, 0); /* ETXCK */
at91_pio3_set_b_periph(AT91_PIO_PORTC, 28, 0); /* ECRSDV */
at91_pio3_set_b_periph(AT91_PIO_PORTC, 20, 0); /* ERXO */
at91_pio3_set_b_periph(AT91_PIO_PORTC, 21, 0); /* ERX1 */
at91_pio3_set_b_periph(AT91_PIO_PORTC, 16, 0); /* ERXER */
at91_pio3_set_b_periph(AT91_PIO_PORTC, 27, 0); /* ETXEN */
at91_pio3_set_b_periph(AT91_PIO_PORTC, 18, 0); /* ETX0 */
at91_pio3_set_b_periph(AT91_PIO_PORTC, 19, 0); /* ETX1 */
at91_pio3_set_b_periph(AT91_PIO_PORTC, 31, 0); /* EMDIO */
at91_pio3_set_b_periph(AT91_PIO_PORTC, 30, 0); /* EMDC */
}
#ifndef CONFIG_RMII
/* Only emac0 support MII */
if (has_emac0()) {
at91_pio3_set_a_periph(AT91_PIO_PORTB, 16, 0); /* ECRS */
at91_pio3_set_a_periph(AT91_PIO_PORTB, 17, 0); /* ECOL */
at91_pio3_set_a_periph(AT91_PIO_PORTB, 13, 0); /* ERX2 */
at91_pio3_set_a_periph(AT91_PIO_PORTB, 14, 0); /* ERX3 */
at91_pio3_set_a_periph(AT91_PIO_PORTB, 15, 0); /* ERXCK */
at91_pio3_set_a_periph(AT91_PIO_PORTB, 11, 0); /* ETX2 */
at91_pio3_set_a_periph(AT91_PIO_PORTB, 12, 0); /* ETX3 */
at91_pio3_set_a_periph(AT91_PIO_PORTB, 8, 0); /* ETXER */
}
#endif
}
#endif

8
arch/arm/mach-at91/armv7/sama5d2_devices.c
View File

@ -57,8 +57,16 @@ char *get_cpu_name(void)
return "SAMA5D27 512M bits DDR2 SDRAM";
case ARCH_EXID_SAMA5D27C_D1G:
return "SAMA5D27 1G bits DDR2 SDRAM";
case ARCH_EXID_SAMA5D27C_LD1G:
return "SAMA5D27 1G bits LPDDR2 SDRAM";
case ARCH_EXID_SAMA5D27C_LD2G:
return "SAMA5D27 2G bits LPDDR2 SDRAM";
case ARCH_EXID_SAMA5D28C_D1G:
return "SAMA5D28 1G bits DDR2 SDRAM";
case ARCH_EXID_SAMA5D28C_LD1G:
return "SAMA5D28 1G bits LPDDR2 SDRAM";
case ARCH_EXID_SAMA5D28C_LD2G:
return "SAMA5D28 2G bits LPDDR2 SDRAM";
}
}

2
arch/arm/mach-at91/armv7/sama5d4_devices.c
View File

@ -8,7 +8,7 @@
#include <asm/io.h>
#include <asm/arch/at91_common.h>
#include <asm/arch/clk.h>
#include <asm/arch/sama5_sfr.h>
#include <asm/arch/at91_sfr.h>
#include <asm/arch/sama5d4.h>
char *get_cpu_name()

16
arch/arm/mach-at91/atmel_sfr.c
View File

@ -7,8 +7,9 @@
#include <common.h>
#include <asm/hardware.h>
#include <asm/io.h>
#include <asm/arch/sama5_sfr.h>
#include <asm/arch/at91_sfr.h>
#if defined(CONFIG_SAMA5D2) || defined(CONFIG_SAMA5D4)
void redirect_int_from_saic_to_aic(void)
{
struct atmel_sfr *sfr = (struct atmel_sfr *)ATMEL_BASE_SFR;
@ -26,3 +27,16 @@ void configure_2nd_sram_as_l2_cache(void)
writel(1, &sfr->l2cc_hramc);
}
#endif
void configure_ddrcfg_input_buffers(bool open)
{
struct atmel_sfr *sfr = (struct atmel_sfr *)ATMEL_BASE_SFR;
if (open)
writel(ATMEL_SFR_DDRCFG_FDQIEN | ATMEL_SFR_DDRCFG_FDQSIEN,
&sfr->ddrcfg);
else
writel(0, &sfr->ddrcfg);
}

3
arch/arm/mach-at91/include/mach/at91_common.h
View File

@ -35,6 +35,9 @@ void at91_disable_wdt(void);
void matrix_init(void);
void redirect_int_from_saic_to_aic(void);
void configure_2nd_sram_as_l2_cache(void);
#ifdef CONFIG_ATMEL_SFR
void configure_ddrcfg_input_buffers(bool open);
#endif
int at91_set_ethaddr(int offset);
int at91_video_show_board_info(void);

52
arch/arm/mach-at91/include/mach/sama5_sfr.h → arch/arm/mach-at91/include/mach/at91_sfr.h
View File

@ -6,12 +6,15 @@
* Bo Shen <voice.shen@atmel.com>
*/
#ifndef __SAMA5_SFR_H
#define __SAMA5_SFR_H
#ifndef __AT91_SFR_H
#define __AT91_SFR_H
struct atmel_sfr {
u32 reserved1; /* 0x00 */
u32 ddrcfg; /* 0x04: DDR Configuration Register */
union {
u32 ddrcfg; /* 0x04: DDR Configuration Register */
u32 ebicsa; /* 0x04: EBI Chip Select Register */
};
u32 reserved2; /* 0x08 */
u32 reserved3; /* 0x0c */
u32 ohciicr; /* 0x10: OHCI Interrupt Configuration Register */
@ -28,7 +31,16 @@ struct atmel_sfr {
};
/* Register Mapping*/
#define AT91_SFR_DDRCFG 0x04 /* DDR Configuration Register */
#define AT91_SFR_CCFG_EBICSA 0x04 /* EBI Chip Select Register */
/* 0x08 ~ 0x0c: Reserved */
#define AT91_SFR_OHCIICR 0x10 /* OHCI INT Configuration Register */
#define AT91_SFR_OHCIISR 0x14 /* OHCI INT Status Register */
#define AT91_SFR_UTMICKTRIM 0x30 /* UTMI Clock Trimming Register */
#define AT91_SFR_UTMISWAP 0x3c /* UTMI DP/DM Pin Swapping Register */
#define AT91_SFR_LS 0x7c /* Light Sleep Register */
#define AT91_SFR_I2SCLKSEL 0x90 /* I2SC Register */
#define AT91_SFR_WPMR 0xe4 /* Write Protection Mode Register */
/* Bit field in DDRCFG */
#define ATMEL_SFR_DDRCFG_FDQIEN 0x00010000
@ -58,9 +70,39 @@ struct atmel_sfr {
#define AT91_SFR_EBICFG_SCH1_OFF (0x0 << 12)
#define AT91_SFR_EBICFG_SCH1_ON (0x1 << 12)
#define AT91_UTMICKTRIM_FREQ GENMASK(1, 0)
/* Bit field in AICREDIR */
#define ATMEL_SFR_AICREDIR_NSAIC 0x00000001
/* Bit field in DDRCFG */
#define ATMEL_SFR_DDRCFG_FDQIEN 0x00010000
#define ATMEL_SFR_DDRCFG_FDQSIEN 0x00020000
#define AT91_SFR_CCFG_EBI_CSA(cs, val) ((val) << (cs))
#define AT91_SFR_CCFG_EBI_DBPUC BIT(8)
#define AT91_SFR_CCFG_EBI_DBPDC BIT(9)
#define AT91_SFR_CCFG_EBI_DRIVE_SAM9X60 BIT(16)
#define AT91_SFR_CCFG_EBI_DRIVE BIT(17)
#define AT91_SFR_CCFG_DQIEN_F BIT(20)
#define AT91_SFR_CCFG_NFD0_ON_D16 BIT(24)
#define AT91_SFR_CCFG_DDR_MP_EN BIT(25)
#define AT91_SFR_OHCIICR_RES(x) BIT(x)
#define AT91_SFR_OHCIICR_ARIE BIT(4)
#define AT91_SFR_OHCIICR_APPSTART BIT(5)
#define AT91_SFR_OHCIICR_USB_SUSP(x) BIT(8 + (x))
#define AT91_SFR_OHCIICR_UDPPUDIS BIT(23)
#define AT91_OHCIICR_USB_SUSPEND GENMASK(10, 8)
#define AT91_SFR_OHCIISR_RIS(x) BIT(x)
#define AT91_UTMICKTRIM_FREQ GENMASK(1, 0)
#define AT91_SFR_UTMISWAP_PORT(x) BIT(x)
#define AT91_SFR_LS_VALUE(x) BIT(x)
#define AT91_SFR_LS_MEM_POWER_GATING_ULP1_EN BIT(16)
#define AT91_SFR_WPMR_WPEN BIT(0)
#define AT91_SFR_WPMR_WPKEY_MASK GENMASK(31, 8)
#endif

23
arch/arm/mach-at91/include/mach/atmel_mpddrc.h
View File

@ -18,6 +18,9 @@ struct atmel_mpddrc_config {
u32 tpr1;
u32 tpr2;
u32 md;
u32 lpddr23_lpr;
u32 cal_mr4;
u32 tim_cal;
};
/*
@ -61,6 +64,10 @@ int ddr2_init(const unsigned int base,
const unsigned int ram_address,
const struct atmel_mpddrc_config *mpddr_value);
int lpddr2_init(const unsigned int base,
const unsigned int ram_address,
const struct atmel_mpddrc_config *mpddr_value);
int ddr3_init(const unsigned int base,
const unsigned int ram_address,
const struct atmel_mpddrc_config *mpddr_value);
@ -74,6 +81,11 @@ int ddr3_init(const unsigned int base,
#define ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD 0x5
#define ATMEL_MPDDRC_MR_MODE_DEEP_CMD 0x6
#define ATMEL_MPDDRC_MR_MODE_LPDDR2_CMD 0x7
#define ATMEL_MPDDRC_MR_MRS(v) (((v) & 0xFF) << 0x8)
/* Bit field in refresh timer register */
#define ATMEL_MPDDRC_RTR_ADJ_REF (0x1 << 16)
#define ATMEL_MPDDRC_RTR_MR4VALUE(v) (((v) & 0x7) << 20)
/* Bit field in configuration register */
#define ATMEL_MPDDRC_CR_NC_MASK 0x3
@ -157,6 +169,7 @@ int ddr3_init(const unsigned int base,
#define ATMEL_MPDDRC_MD_DDR3_SDRAM 0x4
#define ATMEL_MPDDRC_MD_LPDDR3_SDRAM 0x5
#define ATMEL_MPDDRC_MD_DDR2_SDRAM 0x6
#define ATMEL_MPDDRC_MD_LPDDR2_SDRAM 0x7
#define ATMEL_MPDDRC_MD_DBW_MASK (0x1 << 4)
#define ATMEL_MPDDRC_MD_DBW_32_BITS (0x0 << 4)
#define ATMEL_MPDDRC_MD_DBW_16_BITS (0x1 << 4)
@ -206,4 +219,14 @@ int ddr3_init(const unsigned int base,
#define ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_TWO_CYCLE 0x2
#define ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_THREE_CYCLE 0x3
/* Bit field in LPDDR2 - LPDDR3 Low Power Register */
#define ATMEL_MPDDRC_LPDDR23_LPR_DS(x) (((x) & 0xf) << 24)
/* Bit field in CAL_MR4 Calibration and MR4 Register */
#define ATMEL_MPDDRC_CAL_MR4_COUNT_CAL(x) (((x) & 0xffff) << 0)
#define ATMEL_MPDDRC_CAL_MR4_MR4R(x) (((x) & 0xffff) << 16)
/* Bit field in TIM_CAL Timing Calibration Register */
#define ATMEL_MPDDRC_CALR_ZQCS(x) (((x) & 0xff) << 0)
#endif

2
arch/arm/mach-at91/include/mach/hardware.h
View File

@ -22,6 +22,8 @@
# include <asm/arch/at91sam9g45.h>
#elif defined(CONFIG_AT91SAM9N12) || defined(CONFIG_AT91SAM9X5)
# include <asm/arch/at91sam9x5.h>
#elif defined(CONFIG_SAM9X60)
# include <asm/arch/sam9x60.h>
#elif defined(CONFIG_SAMA5D2)
# include <asm/arch/sama5d2.h>
#elif defined(CONFIG_SAMA5D3)

169
arch/arm/mach-at91/include/mach/sam9x60.h Normal file
View File

@ -0,0 +1,169 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Chip-specific header file for the SAM9X60 SoC.
*
* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries
*/
#ifndef __SAM9X60_H__
#define __SAM9X60_H__
/*
* Peripheral identifiers/interrupts.
*/
#define ATMEL_ID_FIQ 0 /* Advanced Interrupt Controller */
#define ATMEL_ID_SYS 1 /* System Controller Interrupt */
#define ATMEL_ID_PIOA 2 /* Parallel I/O Controller A */
#define ATMEL_ID_PIOB 3 /* Parallel I/O Controller B */
#define ATMEL_ID_PIOC 4 /* Parallel I/O Controller C */
#define ATMEL_ID_FLEXCOM0 5 /* FLEXCOM 0 */
#define ATMEL_ID_FLEXCOM1 6 /* FLEXCOM 1 */
#define ATMEL_ID_FLEXCOM2 7 /* FLEXCOM 2 */
#define ATMEL_ID_FLEXCOM3 8 /* FLEXCOM 3 */
#define ATMEL_ID_FLEXCOM6 9 /* FLEXCOM 6 */
#define ATMEL_ID_FLEXCOM7 10 /* FLEXCOM 7 */
#define ATMEL_ID_FLEXCOM8 11 /* FLEXCOM 8 */
#define ATMEL_ID_SDMMC0 12 /* SDMMC 0 */
#define ATMEL_ID_FLEXCOM4 13 /* FLEXCOM 4 */
#define ATMEL_ID_FLEXCOM5 14 /* FLEXCOM 5 */
#define ATMEL_ID_FLEXCOM9 15 /* FLEXCOM 9 */
#define ATMEL_ID_FLEXCOM10 16 /* FLEXCOM 10 */
#define ATMEL_ID_TC01 17 /* Timer Counter 0, 1, 2, 3, 4 and 5 */
#define ATMEL_ID_PWM 18 /* Pulse Width Modulation Controller */
#define ATMEL_ID_ADC 19 /* ADC Controller */
#define ATMEL_ID_XDMAC0 20 /* XDMA Controller 0 */
#define ATMEL_ID_MATRIX 21 /* BUS Matrix */
#define ATMEL_ID_UHPHS 22 /* USB Host High Speed */
#define ATMEL_ID_UDPHS 23 /* USB Device High Speed */
#define ATMEL_ID_EMAC0 24 /* Ethernet MAC 0 */
#define ATMEL_ID_LCDC 25 /* LCD Controller */
#define ATMEL_ID_SDMMC1 26 /* SDMMC 1 */
#define ATMEL_ID_EMAC1 27 /* Ethernet MAC `1 */
#define ATMEL_ID_SSC 28 /* Synchronous Serial Controller */
#define ATMEL_ID_IRQ 31 /* Advanced Interrupt Controller */
#define ATMEL_ID_TRNG 38 /* True Random Number Generator */
#define ATMEL_ID_PIOD 44 /* Parallel I/O Controller D */
#define ATMEL_ID_DBGU 47 /* Debug unit */
/*
* User Peripheral physical base addresses.
*/
#define ATMEL_BASE_FLEXCOM4 0xf0000000
#define ATMEL_BASE_FLEXCOM5 0xf0004000
#define ATMEL_BASE_XDMA0 0xf0008000
#define ATMEL_BASE_SSC 0xf0010000
#define ATMEL_BASE_QSPI 0xf0014000
#define ATMEL_BASE_CAN0 0xf8000000
#define ATMEL_BASE_CAN1 0xf8004000
#define ATMEL_BASE_TC0 0xf8008000
#define ATMEL_BASE_TC1 0xf8008040
#define ATMEL_BASE_TC2 0xf8008080
#define ATMEL_BASE_TC3 0xf800c000
#define ATMEL_BASE_TC4 0xf800c040
#define ATMEL_BASE_TC5 0xf800c080
#define ATMEL_BASE_FLEXCOM6 0xf8010000
#define ATMEL_BASE_FLEXCOM7 0xf8014000
#define ATMEL_BASE_FLEXCOM8 0xf8018000
#define ATMEL_BASE_FLEXCOM0 0xf801c000
#define ATMEL_BASE_FLEXCOM1 0xf8020000
#define ATMEL_BASE_FLEXCOM2 0xf8024000
#define ATMEL_BASE_FLEXCOM3 0xf8028000
#define ATMEL_BASE_EMAC0 0xf802c000
#define ATMEL_BASE_EMAC1 0xf8030000
#define ATMEL_BASE_PWM 0xf8034000
#define ATMEL_BASE_LCDC 0xf8038000
#define ATMEL_BASE_UDPHS 0xf803c000
#define ATMEL_BASE_FLEXCOM9 0xf8040000
#define ATMEL_BASE_FLEXCOM10 0xf8044000
#define ATMEL_BASE_ISI 0xf8048000
#define ATMEL_BASE_ADC 0xf804c000
#define ATMEL_BASE_SFR 0xf8050000
#define ATMEL_BASE_SYS 0xffffc000
/*
* System Peripherals
*/
#define ATMEL_BASE_MATRIX 0xffffde00
#define ATMEL_BASE_PMECC 0xffffe000
#define ATMEL_BASE_PMERRLOC 0xffffe600
#define ATMEL_BASE_MPDDRC 0xffffe800
#define ATMEL_BASE_SMC 0xffffea00
#define ATMEL_BASE_SDRAMC 0xffffec00
#define ATMEL_BASE_AIC 0xfffff100
#define ATMEL_BASE_DBGU 0xfffff200
#define ATMEL_BASE_PIOA 0xfffff400
#define ATMEL_BASE_PIOB 0xfffff600
#define ATMEL_BASE_PIOC 0xfffff800
#define ATMEL_BASE_PIOD 0xfffffa00
#define ATMEL_BASE_PMC 0xfffffc00
#define ATMEL_BASE_RSTC 0xfffffe00
#define ATMEL_BASE_SHDWC 0xfffffe10
#define ATMEL_BASE_PIT 0xfffffe40
#define ATMEL_BASE_GPBR 0xfffffe60
#define ATMEL_BASE_RTC 0xfffffea8
#define ATMEL_BASE_WDT 0xffffff80
/*
* Internal Memory.
*/
#define ATMEL_BASE_ROM 0x00100000 /* Internal ROM base address */
#define ATMEL_BASE_SRAM 0x00300000 /* Internal SRAM base address */
#define ATMEL_BASE_UDPHS_FIFO 0x00500000 /* USB Device HS controller */
#define ATMEL_BASE_OHCI 0x00600000 /* USB Host controller (OHCI) */
#define ATMEL_BASE_EHCI 0x00700000 /* USB Host controller (EHCI) */
/*
* External memory
*/
#define ATMEL_BASE_CS0 0x10000000
#define ATMEL_BASE_CS1 0x20000000
#define ATMEL_BASE_CS2 0x30000000
#define ATMEL_BASE_CS3 0x40000000
#define ATMEL_BASE_CS4 0x50000000
#define ATMEL_BASE_CS5 0x60000000
#define ATMEL_BASE_SDMMC0 0x80000000
#define ATMEL_BASE_SDMMC1 0x90000000
/* 9x60 series chip id definitions */
#define ARCH_ID_SAM9X60 0x819b35a0
#define ARCH_ID_VERSION_MASK 0x1f
#define ARCH_EXID_SAM9X60 0x00000000
#define cpu_is_sam9x60() (get_chip_id() == ARCH_ID_SAM9X60)
/*
* Cpu Name
*/
#define ATMEL_CPU_NAME get_cpu_name()
/* Timer */
#define CONFIG_SYS_TIMER_COUNTER 0xfffffe4c
/*
* Other misc defines
*/
#define ATMEL_PIO_PORTS 4
#define CPU_HAS_PCR
#define CPU_NO_PLLB
#define PLL_ID_PLLA 0
#define PLL_ID_UPLL 1
/*
* PMECC table in ROM
*/
#define ATMEL_PMECC_INDEX_OFFSET_512 0x8000
#define ATMEL_PMECC_INDEX_OFFSET_1024 0x10000
/*
* SAM9X60 specific prototypes
*/
#ifndef __ASSEMBLY__
unsigned int get_chip_id(void);
unsigned int get_extension_chip_id(void);
unsigned int has_emac1(void);
unsigned int has_emac0(void);
unsigned int has_lcdc(void);
char *get_cpu_name(void);
#endif
#endif

4
arch/arm/mach-at91/include/mach/sama5d2.h
View File

@ -220,7 +220,11 @@
#define ARCH_EXID_SAMA5D225C_D1M 0x00000053
#define ARCH_EXID_SAMA5D27C_D5M 0x00000032
#define ARCH_EXID_SAMA5D27C_D1G 0x00000033
#define ARCH_EXID_SAMA5D27C_LD1G 0x00000061
#define ARCH_EXID_SAMA5D27C_LD2G 0x00000062
#define ARCH_EXID_SAMA5D28C_D1G 0x00000013
#define ARCH_EXID_SAMA5D28C_LD1G 0x00000071
#define ARCH_EXID_SAMA5D28C_LD2G 0x00000072
/* Checked if defined in ethernet driver macb */
#define cpu_is_sama5d2 _cpu_is_sama5d2

162
arch/arm/mach-at91/mpddrc.c
View File

@ -10,6 +10,7 @@
#include <common.h>
#include <asm/io.h>
#include <asm/arch/atmel_mpddrc.h>
#include <asm/arch/at91_common.h>
#define SAMA5D3_MPDDRC_VERSION 0x140
@ -18,6 +19,7 @@ static inline void atmel_mpddr_op(const struct atmel_mpddr *mpddr,
u32 ram_address)
{
writel(mode, &mpddr->mr);
dmb();
writel(0, ram_address);
}
@ -227,3 +229,163 @@ int ddr3_init(const unsigned int base,
return 0;
}
int lpddr2_init(const unsigned int base,
const unsigned int ram_address,
const struct atmel_mpddrc_config *mpddr_value)
{
struct atmel_mpddr *mpddr = (struct atmel_mpddr *)base;
u32 reg;
writel(mpddr_value->lpddr23_lpr, &mpddr->lpddr23_lpr);
writel(mpddr_value->tim_cal, &mpddr->tim_cal);
/* 1. Program the memory device type */
writel(mpddr_value->md, &mpddr->md);
/*
* 2. Program features of the LPDDR2-SDRAM device and timing parameters
*/
writel(mpddr_value->cr, &mpddr->cr);
writel(mpddr_value->tpr0, &mpddr->tpr0);
writel(mpddr_value->tpr1, &mpddr->tpr1);
writel(mpddr_value->tpr2, &mpddr->tpr2);
/* 3. A NOP command is issued to the LPDDR2-SDRAM */
atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_NOP_CMD, ram_address);
/*
* 3bis. Add memory barrier then Perform a write access to
* any low-power DDR2-SDRAM address to acknowledge the command.
*/
dmb();
writel(0, ram_address);
/* 4. A pause of at least 100 ns must be observed before a single toggle */
udelay(1);
/* 5. A NOP command is issued to the LPDDR2-SDRAM */
atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_NOP_CMD, ram_address);
/* 6. A pause of at least 200 us must be observed before a Reset Command */
udelay(200);
/* 7. A Reset command is issued to the low-power DDR2-SDRAM. */
atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_LPDDR2_CMD |
ATMEL_MPDDRC_MR_MRS(63), ram_address);
/*
* 8. A pause of at least tINIT5 must be observed before issuing
* any commands
*/
udelay(1);
/* 9. A Calibration command is issued to the low-power DDR2-SDRAM. */
reg = readl(&mpddr->cr);
reg &= ~ATMEL_MPDDRC_CR_ZQ_RESET;
reg |= ATMEL_MPDDRC_CR_ZQ_RESET;
writel(reg, &mpddr->cr);
atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_LPDDR2_CMD |
ATMEL_MPDDRC_MR_MRS(10), ram_address);
/*
* 9bis: The ZQ Calibration command is now issued.
* Program the type of calibration in the MPDDRC_CR: set the
* ZQ field to the SHORT value.
*/
reg = readl(&mpddr->cr);
reg &= ~ATMEL_MPDDRC_CR_ZQ_RESET;
reg |= ATMEL_MPDDRC_CR_ZQ_SHORT;
writel(reg, &mpddr->cr);
/*
* 10: A Mode Register Write command with 1 to the MRS field
* is issued to the low-power DDR2-SDRAM.
*/
atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_LPDDR2_CMD |
ATMEL_MPDDRC_MR_MRS(1), ram_address);
/*
* 11: A Mode Register Write command with 2 to the MRS field
* is issued to the low-power DDR2-SDRAM.
*/
atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_LPDDR2_CMD |
ATMEL_MPDDRC_MR_MRS(2), ram_address);
/*
* 12: A Mode Register Write command with 3 to the MRS field
* is issued to the low-power DDR2-SDRAM.
*/
atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_LPDDR2_CMD |
ATMEL_MPDDRC_MR_MRS(3), ram_address);
/*
* 13: A Mode Register Write command with 16 to the MRS field
* is issued to the low-power DDR2-SDRAM.
*/
atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_LPDDR2_CMD |
ATMEL_MPDDRC_MR_MRS(16), ram_address);
/*
* 14: In the DDR Configuration Register, open the input buffers.
*/
#ifdef CONFIG_ATMEL_SFR
configure_ddrcfg_input_buffers(true);
#endif
/* 15. A NOP command is issued to the LPDDR2-SDRAM */
atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_NOP_CMD, ram_address);
/*
* 16: A Mode Register Write command with 5 to the MRS field
* is issued to the low-power DDR2-SDRAM.
*/
atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_LPDDR2_CMD |
ATMEL_MPDDRC_MR_MRS(5), ram_address);
/*
* 17: A Mode Register Write command with 6 to the MRS field
* is issued to the low-power DDR2-SDRAM.
*/
atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_LPDDR2_CMD |
ATMEL_MPDDRC_MR_MRS(6), ram_address);
/*
* 18: A Mode Register Write command with 8 to the MRS field
* is issued to the low-power DDR2-SDRAM.
*/
atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_LPDDR2_CMD |
ATMEL_MPDDRC_MR_MRS(8), ram_address);
/*
* 19: A Mode Register Write command with 0 to the MRS field
* is issued to the low-power DDR2-SDRAM.
*/
atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_LPDDR2_CMD |
ATMEL_MPDDRC_MR_MRS(0), ram_address);
/*
* 20: A Normal Mode command is provided.
*/
atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_NORMAL_CMD, ram_address);
/* 21: In the DDR Configuration Register, close the input buffers. */
#ifdef CONFIG_ATMEL_SFR
configure_ddrcfg_input_buffers(false);
#endif
/*
* 22: Write the refresh rate into the COUNT field in the MPDDRC
* Refresh Timer Register.
*/
writel(mpddr_value->rtr, &mpddr->rtr);
/* 23. Configre CAL MR4 register */
writel(mpddr_value->cal_mr4, &mpddr->cal_mr4);
return 0;
}

2
board/atmel/common/video_display.c
View File

@ -23,7 +23,7 @@ int at91_video_show_board_info(void)
int i;
u32 len = 0;
char buf[255];
char *corp = "2017 Microchip Technology Inc.\n";
char *corp = "Microchip Technology Inc.\n";
char temp[32];
struct udevice *dev, *con;
const char *s;

12
board/atmel/sam9x60ek/Kconfig Normal file
View File

@ -0,0 +1,12 @@
if TARGET_SAM9X60EK
config SYS_BOARD
default "sam9x60ek"
config SYS_VENDOR
default "atmel"
config SYS_CONFIG_NAME
default "sam9x60ek"
endif

9
board/atmel/sam9x60ek/MAINTAINERS Normal file
View File

@ -0,0 +1,9 @@
SAM9X60EK BOARD
M: Sandeep Sheriker M <sandeep.sheriker@microchip.com>
M: Eugen Hristev <eugen.hristev@microchip.com>
S: Maintained
F: board/atmel/sam9x60ek/
F: include/configs/sam9x60ek.h
F: configs/sam9x60ek_mmc_defconfig
F: configs/sam9x60ek_nandflash_defconfig
F: configs/sam9x60ek_qspiflash_defconfig

7
board/atmel/sam9x60ek/Makefile Normal file
View File

@ -0,0 +1,7 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries
#
# Author: Sandeep Sheriker M <sandeep.sheriker@microchip.com>
obj-y += sam9x60ek.o

125
board/atmel/sam9x60ek/sam9x60ek.c Normal file
View File

@ -0,0 +1,125 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries
*
* Author: Sandeep Sheriker M <sandeep.sheriker@microchip.com>
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/at91sam9_smc.h>
#include <asm/arch/at91_common.h>
#include <asm/arch/at91_rstc.h>
#include <asm/arch/at91_sfr.h>
#include <asm/arch/clk.h>
#include <asm/arch/gpio.h>
#include <debug_uart.h>
#include <asm/mach-types.h>
extern void at91_pda_detect(void);
DECLARE_GLOBAL_DATA_PTR;
void at91_prepare_cpu_var(void);
#ifdef CONFIG_CMD_NAND
static void sam9x60ek_nand_hw_init(void)
{
struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
struct atmel_sfr *sfr = (struct atmel_sfr *)ATMEL_BASE_SFR;
unsigned int csa;
at91_pio3_set_a_periph(AT91_PIO_PORTD, 0, 1); /* NAND OE */
at91_pio3_set_a_periph(AT91_PIO_PORTD, 1, 1); /* NAND WE */
at91_pio3_set_a_periph(AT91_PIO_PORTD, 2, 0); /* NAND ALE */
at91_pio3_set_a_periph(AT91_PIO_PORTD, 3, 0); /* NAND CLE */
/* Enable NandFlash */
at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
/* Configure RDY/BSY */
at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
at91_pio3_set_a_periph(AT91_PIO_PORTD, 6, 1);
at91_pio3_set_a_periph(AT91_PIO_PORTD, 7, 1);
at91_pio3_set_a_periph(AT91_PIO_PORTD, 8, 1);
at91_pio3_set_a_periph(AT91_PIO_PORTD, 9, 1);
at91_pio3_set_a_periph(AT91_PIO_PORTD, 10, 1);
at91_pio3_set_a_periph(AT91_PIO_PORTD, 11, 1);
at91_pio3_set_a_periph(AT91_PIO_PORTD, 12, 1);
at91_pio3_set_a_periph(AT91_PIO_PORTD, 13, 1);
at91_periph_clk_enable(ATMEL_ID_PIOD);
/* Enable CS3 */
csa = readl(&sfr->ebicsa);
csa |= AT91_SFR_CCFG_EBI_CSA(3, 1) | AT91_SFR_CCFG_NFD0_ON_D16;
/* Configure IO drive */
csa &= ~AT91_SFR_CCFG_EBI_DRIVE_SAM9X60;
writel(csa, &sfr->ebicsa);
/* Configure SMC CS3 for NAND/SmartMedia */
writel(AT91_SMC_SETUP_NWE(4), &smc->cs[3].setup);
writel(AT91_SMC_PULSE_NWE(10) | AT91_SMC_PULSE_NCS_WR(20) |
AT91_SMC_PULSE_NRD(10) | AT91_SMC_PULSE_NCS_RD(20),
&smc->cs[3].pulse);
writel(AT91_SMC_CYCLE_NWE(20) | AT91_SMC_CYCLE_NRD(20),
&smc->cs[3].cycle);
writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
#ifdef CONFIG_SYS_NAND_DBW_16
AT91_SMC_MODE_DBW_16 |
#else /* CONFIG_SYS_NAND_DBW_8 */
AT91_SMC_MODE_DBW_8 |
#endif
AT91_SMC_MODE_TDF | AT91_SMC_MODE_TDF_CYCLE(15),
&smc->cs[3].mode);
}
#endif
#ifdef CONFIG_BOARD_LATE_INIT
int board_late_init(void)
{
at91_prepare_cpu_var();
at91_pda_detect();
return 0;
}
#endif
#ifdef CONFIG_DEBUG_UART_BOARD_INIT
void board_debug_uart_init(void)
{
at91_seriald_hw_init();
}
#endif
#ifdef CONFIG_BOARD_EARLY_INIT_F
int board_early_init_f(void)
{
#ifdef CONFIG_DEBUG_UART
debug_uart_init();
#endif
return 0;
}
#endif
int board_init(void)
{
/* address of boot parameters */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
#ifdef CONFIG_CMD_NAND
sam9x60ek_nand_hw_init();
#endif
return 0;
}
int dram_init(void)
{
gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
CONFIG_SYS_SDRAM_SIZE);
return 0;
}

15
board/atmel/sama5d27_wlsom1_ek/Kconfig Normal file
View File

@ -0,0 +1,15 @@
if TARGET_SAMA5D27_WLSOM1_EK
config SYS_BOARD
default "sama5d27_wlsom1_ek"
config SYS_VENDOR
default "atmel"
config SYS_SOC
default "at91"
config SYS_CONFIG_NAME
default "sama5d27_wlsom1_ek"
endif

8
board/atmel/sama5d27_wlsom1_ek/MAINTAINERS Normal file
View File

@ -0,0 +1,8 @@
SAMA5D27 WLSOM1 EK BOARD
M: Nicolas Ferre <nicolas.ferre@microchip.com>
M: Eugen Hristev <eugen.hristev@microchip.com>
S: Maintained
F: board/atmel/sama5d27_wlsom1_ek/
F: include/configs/sama5d27_wlsom1_ek.h
F: configs/sama5d27_wlsom1_ek_mmc_defconfig
F: configs/sama5d27_wlsom1_ek_qspiflash_defconfig

7
board/atmel/sama5d27_wlsom1_ek/Makefile Normal file
View File

@ -0,0 +1,7 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries
#
# Author: Nicolas Ferre <nicolas.ferre@microcihp.com>
obj-y += sama5d27_wlsom1_ek.o

252
board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c Normal file
View File

@ -0,0 +1,252 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries
*
* Author: Nicolas Ferre <nicolas.ferre@microcihp.com>
*/
#include <common.h>
#include <debug_uart.h>
#include <asm/io.h>
#include <asm/arch/at91_common.h>
#include <asm/arch/atmel_pio4.h>
#include <asm/arch/atmel_mpddrc.h>
#include <asm/arch/atmel_sdhci.h>
#include <asm/arch/clk.h>
#include <asm/arch/gpio.h>
#include <asm/arch/sama5d2.h>
extern void at91_pda_detect(void);
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_BOARD_LATE_INIT
int board_late_init(void)
{
#ifdef CONFIG_DM_VIDEO
at91_video_show_board_info();
#endif
at91_pda_detect();
return 0;
}
#endif
#ifdef CONFIG_DEBUG_UART_BOARD_INIT
static void board_uart0_hw_init(void)
{
atmel_pio4_set_c_periph(AT91_PIO_PORTB, 26, ATMEL_PIO_PUEN_MASK); /* URXD0 */
atmel_pio4_set_c_periph(AT91_PIO_PORTB, 27, 0); /* UTXD0 */
at91_periph_clk_enable(ATMEL_ID_UART0);
}
void board_debug_uart_init(void)
{
board_uart0_hw_init();
}
#endif
#ifdef CONFIG_BOARD_EARLY_INIT_F
int board_early_init_f(void)
{
#ifdef CONFIG_DEBUG_UART
debug_uart_init();
#endif
return 0;
}
#endif
int board_init(void)
{
/* address of boot parameters */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
return 0;
}
#ifdef CONFIG_MISC_INIT_R
int misc_init_r(void)
{
return 0;
}
#endif
int dram_init(void)
{
gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
CONFIG_SYS_SDRAM_SIZE);
return 0;
}
/* SPL */
#ifdef CONFIG_SPL_BUILD
static void board_leds_init(void)
{
atmel_pio4_set_pio_output(AT91_PIO_PORTA, 6, 0); /* RED */
atmel_pio4_set_pio_output(AT91_PIO_PORTA, 7, 1); /* GREEN */
atmel_pio4_set_pio_output(AT91_PIO_PORTA, 8, 0); /* BLUE */
}
#ifdef CONFIG_SD_BOOT
void spl_mmc_init(void)
{
atmel_pio4_set_a_periph(AT91_PIO_PORTA, 1, 0); /* CMD */
atmel_pio4_set_a_periph(AT91_PIO_PORTA, 2, 0); /* DAT0 */
atmel_pio4_set_a_periph(AT91_PIO_PORTA, 3, 0); /* DAT1 */
atmel_pio4_set_a_periph(AT91_PIO_PORTA, 4, 0); /* DAT2 */
atmel_pio4_set_a_periph(AT91_PIO_PORTA, 5, 0); /* DAT3 */
atmel_pio4_set_a_periph(AT91_PIO_PORTA, 0, 0); /* CK */
atmel_pio4_set_a_periph(AT91_PIO_PORTA, 13, 0); /* CD */
at91_periph_clk_enable(ATMEL_ID_SDMMC0);
}
#endif
#ifdef CONFIG_QSPI_BOOT
void spl_qspi_init(void)
{
atmel_pio4_set_d_periph(AT91_PIO_PORTB, 5, 0); /* SCK */
atmel_pio4_set_d_periph(AT91_PIO_PORTB, 6, 0); /* CS */
atmel_pio4_set_d_periph(AT91_PIO_PORTB, 7, 0); /* IO0 */
atmel_pio4_set_d_periph(AT91_PIO_PORTB, 8, 0); /* IO1 */
atmel_pio4_set_d_periph(AT91_PIO_PORTB, 9, 0); /* IO2 */
atmel_pio4_set_d_periph(AT91_PIO_PORTB, 10, 0); /* IO3 */
at91_periph_clk_enable(ATMEL_ID_QSPI1);
}
#endif
void spl_board_init(void)
{
board_leds_init();
#ifdef CONFIG_SD_BOOT
spl_mmc_init();
#endif
#ifdef CONFIG_QSPI_BOOT
spl_qspi_init();
#endif
}
void spl_display_print(void)
{
}
static void ddrc_conf(struct atmel_mpddrc_config *ddrc)
{
ddrc->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_LPDDR2_SDRAM);
ddrc->cr = (ATMEL_MPDDRC_CR_NC_COL_9 |
ATMEL_MPDDRC_CR_NR_ROW_14 |
ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
ATMEL_MPDDRC_CR_ZQ_SHORT |
ATMEL_MPDDRC_CR_NB_8BANKS |
ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
ddrc->lpddr23_lpr = ATMEL_MPDDRC_LPDDR23_LPR_DS(0x3);
/*
* The AD220032D average time between REFRESH commands (Trefi): 3.9us
* 3.9us * 164MHz = 639.6 = 0x27F.
*/
ddrc->rtr = 0x27f;
/* Enable Adjust Refresh Rate */
ddrc->rtr |= ATMEL_MPDDRC_RTR_ADJ_REF;
ddrc->tpr0 = ((7 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET) |
(3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET) |
(4 << ATMEL_MPDDRC_TPR0_TWR_OFFSET) |
(11 << ATMEL_MPDDRC_TPR0_TRC_OFFSET) |
(4 << ATMEL_MPDDRC_TPR0_TRP_OFFSET) |
(2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET) |
(2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET) |
(5 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET));
ddrc->tpr1 = ((21 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET) |
(0 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET) |
(23 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET) |
(2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET));
ddrc->tpr2 = ((0 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET) |
(0 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET) |
(4 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET) |
(2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET) |
(10 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET));
ddrc->tim_cal = ATMEL_MPDDRC_CALR_ZQCS(15);
/*
* According to the sama5d2 datasheet and the following values:
* T Sens = 0.75%/C, V Sens = 0.2%/mV, T driftrate = 1C/sec and V driftrate = 15 mV/s
* Warning: note that the values T driftrate and V driftrate are dependent on
* the application environment.
* ZQCS period is 1.5 / ((0.75 x 1) + (0.2 x 15)) = 0.4s
* If Trefi is 3.9us, we have: 400000 / 3.9 = 102564: we can maximize
* this timer to 0xFFFE.
*/
ddrc->cal_mr4 = ATMEL_MPDDRC_CAL_MR4_COUNT_CAL(0xFFFE);
/*
* MR4 Read interval is dependent on the application environment.
* Here, we want to maximize this value as temperature is supposed
* to vary slowly in the application chosen.
* If Trefi is 3.9us, we have:
* (0xFFFE) 65534 x 3.9 = 0.25s between MR4 reads.
*/
ddrc->cal_mr4 |= ATMEL_MPDDRC_CAL_MR4_MR4R(0xFFFE);
}
void mem_init(void)
{
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
struct atmel_mpddr *mpddrc = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC;
struct atmel_mpddrc_config ddrc_config;
u32 reg;
at91_periph_clk_enable(ATMEL_ID_MPDDRC);
writel(AT91_PMC_DDR, &pmc->scer);
ddrc_conf(&ddrc_config);
reg = readl(&mpddrc->io_calibr);
reg &= ~ATMEL_MPDDRC_IO_CALIBR_RDIV;
reg |= ATMEL_MPDDRC_IO_CALIBR_LPDDR2_RZQ_48;
reg &= ~ATMEL_MPDDRC_IO_CALIBR_TZQIO;
reg |= ATMEL_MPDDRC_IO_CALIBR_TZQIO_(100);
writel(reg, &mpddrc->io_calibr);
writel(ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_ONE_CYCLE,
&mpddrc->rd_data_path);
lpddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddrc_config);
}
void at91_pmc_init(void)
{
u32 tmp;
/*
* while coming from the ROM code, we run on PLLA @ 492 MHz / 164 MHz
* so we need to slow down and configure MCKR accordingly.
* This is why we have a special flavor of the switching function.
*/
tmp = AT91_PMC_MCKR_PLLADIV_2 |
AT91_PMC_MCKR_MDIV_3 |
AT91_PMC_MCKR_CSS_MAIN;
at91_mck_init_down(tmp);
tmp = AT91_PMC_PLLAR_29 |
AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
AT91_PMC_PLLXR_MUL(40) |
AT91_PMC_PLLXR_DIV(1);
at91_plla_init(tmp);
tmp = AT91_PMC_MCKR_H32MXDIV |
AT91_PMC_MCKR_PLLADIV_2 |
AT91_PMC_MCKR_MDIV_3 |
AT91_PMC_MCKR_CSS_PLLA;
at91_mck_init(tmp);
}
#endif

6
board/laird/wb50n/wb50n.c
View File

@ -4,7 +4,7 @@
#include <common.h>
#include <asm/io.h>
#include <asm/arch/sama5_sfr.h>
#include <asm/arch/at91_sfr.h>
#include <asm/arch/sama5d3_smc.h>
#include <asm/arch/at91_common.h>
#include <asm/arch/at91_pmc.h>
@ -173,13 +173,11 @@ static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
void mem_init(void)
{
struct atmel_sfr *sfr = (struct atmel_sfr *)ATMEL_BASE_SFR;
struct atmel_mpddrc_config ddr2;
ddr2_conf(&ddr2);
writel(ATMEL_SFR_DDRCFG_FDQIEN | ATMEL_SFR_DDRCFG_FDQSIEN,
&sfr->ddrcfg);
configure_ddrcfg_input_buffers(true);
/* enable MPDDR clock */
at91_periph_clk_enable(ATMEL_ID_MPDDRC);

56
configs/sam9x60ek_mmc_defconfig Normal file
View File

@ -0,0 +1,56 @@
CONFIG_ARM=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x23f00000
CONFIG_TARGET_SAM9X60EK=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ENV_SIZE=0x4000
CONFIG_NR_DRAM_BANKS=8
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xfffff200
CONFIG_DEBUG_UART_CLOCK=200000000
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="mem=256M console=ttyS0,115200 root=/dev/mmcblk0p2 rw rootfstype=ext4 rootwait"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_MMC=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="sam9x60ek"
CONFIG_ENV_IS_IN_FAT=y
CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
CONFIG_DM=y
CONFIG_CLK=y
CONFIG_CLK_AT91=y
CONFIG_AT91_GENERIC_CLK=y
CONFIG_DM_GPIO=y
CONFIG_AT91_GPIO=y
CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ATMEL=y
CONFIG_PHY_MICREL=y
CONFIG_DM_ETH=y
CONFIG_MACB=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
CONFIG_W1=y
CONFIG_W1_GPIO=y
CONFIG_W1_EEPROM=y
CONFIG_W1_EEPROM_DS24XXX=y
CONFIG_OF_LIBFDT_OVERLAY=y

57
configs/sam9x60ek_nandflash_defconfig Normal file
View File

@ -0,0 +1,57 @@
CONFIG_ARM=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x23f00000
CONFIG_TARGET_SAM9X60EK=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=8
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xfffff200
CONFIG_DEBUG_UART_CLOCK=200000000
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_NAND_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,768k(uboot)ro,256k(env_redundant),256k(env),512k(dtb),6M(kernel)ro,-(rootfs) rootfstype=ubifs ubi.mtd=12 root=ubi0:rootfs rw"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_NAND=y
CONFIG_CMD_NAND_TRIMFFS=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_FAT=y
CONFIG_CMD_UBI=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="sam9x60ek"
CONFIG_ENV_IS_IN_NAND=y
CONFIG_DM=y
CONFIG_CLK=y
CONFIG_CLK_AT91=y
CONFIG_AT91_GENERIC_CLK=y
CONFIG_DM_GPIO=y
CONFIG_AT91_GPIO=y
CONFIG_DM_MMC=y
CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_PHY_MICREL=y
CONFIG_DM_ETH=y
CONFIG_MACB=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
CONFIG_W1=y
CONFIG_W1_GPIO=y
CONFIG_W1_EEPROM=y
CONFIG_W1_EEPROM_DS24XXX=y
CONFIG_OF_LIBFDT_OVERLAY=y

79
configs/sam9x60ek_qspiflash_defconfig Normal file
View File

@ -0,0 +1,79 @@
CONFIG_ARM=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x23f00000
CONFIG_TARGET_SAM9X60EK=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=8
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xfffff200
CONFIG_DEBUG_UART_CLOCK=200000000
CONFIG_ENV_SECT_SIZE=0x1000
CONFIG_DEBUG_UART=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_FIT=y
CONFIG_QSPI_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,768k(uboot)ro,256k(env_redundant),256k(env),512k(dtb),6M(kernel)ro,-(rootfs) rootfstype=ubifs ubi.mtd=12 root=ubi0:rootfs rw"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_NAND=y
CONFIG_CMD_NAND_TRIMFFS=y
CONFIG_CMD_SF=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_FAT=y
CONFIG_CMD_UBI=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="sam9x60ek"
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_USE_ENV_SPI_BUS=y
CONFIG_ENV_SPI_BUS=0
CONFIG_USE_ENV_SPI_CS=y
CONFIG_ENV_SPI_CS=0
CONFIG_USE_ENV_SPI_MAX_HZ=y
CONFIG_ENV_SPI_MAX_HZ=50000000
CONFIG_USE_ENV_SPI_MODE=y
CONFIG_ENV_SPI_MODE=0x0
CONFIG_DM=y
CONFIG_CLK=y
CONFIG_CLK_AT91=y
CONFIG_AT91_GENERIC_CLK=y
CONFIG_DM_GPIO=y
CONFIG_AT91_GPIO=y
CONFIG_DM_MMC=y
CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_SST=y
CONFIG_SPI_FLASH_MTD=y
CONFIG_PHY_MICREL=y
CONFIG_DM_ETH=y
CONFIG_MACB=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_ATMEL_QSPI=y
CONFIG_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
CONFIG_W1=y
CONFIG_W1_GPIO=y
CONFIG_W1_EEPROM=y
CONFIG_W1_EEPROM_DS24XXX=y
CONFIG_OF_LIBFDT_OVERLAY=y

102
configs/sama5d27_wlsom1_ek_mmc_defconfig Normal file
View File

@ -0,0 +1,102 @@
CONFIG_ARM=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x26f00000
CONFIG_TARGET_SAMA5D27_WLSOM1_EK=y
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_ENV_SIZE=0x4000
CONFIG_SPL=y
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xf801c000
CONFIG_DEBUG_UART_CLOCK=82000000
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_DEBUG_UART=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2"
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_MISC_INIT_R=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_TEXT_BASE=0x200000
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SPL_DISPLAY_PRINT=y
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
CONFIG_SPL_AT91_MCK_BYPASS=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_I2C=y
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d27_wlsom1_ek"
CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dmas dma-names"
CONFIG_ENV_IS_IN_FAT=y
CONFIG_DM=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_CLK=y
CONFIG_SPL_CLK=y
CONFIG_CLK_AT91=y
CONFIG_AT91_UTMI=y
CONFIG_AT91_H32MX=y
CONFIG_AT91_GENERIC_CLK=y
CONFIG_DM_GPIO=y
CONFIG_ATMEL_PIO4=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_AT91=y
CONFIG_I2C_EEPROM=y
CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ATMEL=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_SST=y
CONFIG_PHY_MICREL=y
CONFIG_DM_ETH=y
CONFIG_MACB=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_AT91PIO4=y
CONFIG_DM_SERIAL=y
CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_TIMER=y
CONFIG_SPL_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_ATMEL_USBA=y
CONFIG_DM_VIDEO=y
CONFIG_ATMEL_HLCD=y
CONFIG_W1=y
CONFIG_W1_GPIO=y
CONFIG_W1_EEPROM=y
CONFIG_W1_EEPROM_DS24XXX=y
CONFIG_OF_LIBFDT_OVERLAY=y
# CONFIG_EFI_LOADER_HII is not set

117
configs/sama5d27_wlsom1_ek_qspiflash_defconfig Normal file
View File

@ -0,0 +1,117 @@
CONFIG_ARM=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x26f00000
CONFIG_TARGET_SAMA5D27_WLSOM1_EK=y
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL=y
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xf801c000
CONFIG_DEBUG_UART_CLOCK=82000000
CONFIG_ENV_SECT_SIZE=0x1000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_DEBUG_UART=y
CONFIG_SPL_TEXT_BASE=0x200000
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2"
CONFIG_QSPI_BOOT=y
CONFIG_SPI_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_MISC_INIT_R=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SPL_DISPLAY_PRINT=y
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
CONFIG_SPL_SPI_LOAD=y
CONFIG_SPL_AT91_MCK_BYPASS=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_I2C=y
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d27_wlsom1_ek"
CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dmas dma-names"
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_USE_ENV_SPI_BUS=y
CONFIG_ENV_SPI_BUS=2
CONFIG_USE_ENV_SPI_CS=y
CONFIG_ENV_SPI_CS=0
CONFIG_USE_ENV_SPI_MAX_HZ=y
CONFIG_ENV_SPI_MAX_HZ=50000000
CONFIG_USE_ENV_SPI_MODE=y
CONFIG_ENV_SPI_MODE=0x0
CONFIG_DM=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_CLK=y
CONFIG_SPL_CLK=y
CONFIG_CLK_AT91=y
CONFIG_AT91_UTMI=y
CONFIG_AT91_H32MX=y
CONFIG_AT91_GENERIC_CLK=y
CONFIG_DM_GPIO=y
CONFIG_ATMEL_PIO4=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_AT91=y
CONFIG_I2C_EEPROM=y
CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ATMEL=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_BUS=2
CONFIG_SF_DEFAULT_SPEED=50000000
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_SST=y
CONFIG_PHY_MICREL=y
CONFIG_DM_ETH=y
CONFIG_MACB=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_AT91PIO4=y
CONFIG_DM_SERIAL=y
CONFIG_DEBUG_UART_ATMEL=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_ATMEL_QSPI=y
CONFIG_TIMER=y
CONFIG_SPL_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_ATMEL_USBA=y
CONFIG_DM_VIDEO=y
CONFIG_ATMEL_HLCD=y
CONFIG_W1=y
CONFIG_W1_GPIO=y
CONFIG_W1_EEPROM=y
CONFIG_W1_EEPROM_DS24XXX=y
CONFIG_OF_LIBFDT_OVERLAY=y
# CONFIG_EFI_LOADER_HII is not set

2
drivers/clk/at91/clk-utmi.c
View File

@ -10,7 +10,7 @@
#include <syscon.h>
#include <linux/io.h>
#include <mach/at91_pmc.h>
#include <mach/sama5_sfr.h>
#include <mach/at91_sfr.h>
#include "pmc.h"
/*

1
drivers/mmc/atmel_sdhci.c
View File

@ -112,6 +112,7 @@ static int atmel_sdhci_bind(struct udevice *dev)
static const struct udevice_id atmel_sdhci_ids[] = {
{ .compatible = "atmel,sama5d2-sdhci" },
{ .compatible = "microchip,sam9x60-sdhci" },
{ }
};

1
drivers/net/macb.c
View File

@ -1321,6 +1321,7 @@ static const struct macb_config sifive_config = {
static const struct udevice_id macb_eth_ids[] = {
{ .compatible = "cdns,macb" },
{ .compatible = "cdns,at91sam9260-macb" },
{ .compatible = "cdns,sam9x60-macb" },
{ .compatible = "atmel,sama5d2-gem" },
{ .compatible = "atmel,sama5d3-gem" },
{ .compatible = "atmel,sama5d4-gem", .data = (ulong)&sama5d4_config },

95
include/configs/sam9x60ek.h Normal file
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@ -0,0 +1,95 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Configuation settings for the SAM9X60EK board.
*
* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries
*
* Author: Sandeep Sheriker M <sandeep.sheriker@microchip.com>
*/
#ifndef __CONFIG_H__
#define __CONFIG_H__
/* ARM asynchronous clock */
#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
#define CONFIG_SYS_AT91_MAIN_CLOCK 24000000 /* 24 MHz crystal */
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_USART_BASE ATMEL_BASE_DBGU
#define CONFIG_USART_ID 0 /* ignored in arm */
/* general purpose I/O */
#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */
/*
* BOOTP options
*/
#define CONFIG_BOOTP_BOOTFILESIZE
/*
* define CONFIG_USB_EHCI_HCD to enable USB Hi-Speed (aka 2.0)
* NB: in this case, USB 1.1 devices won't be recognized.
*/
/* SDRAM */
#define CONFIG_SYS_SDRAM_BASE 0x20000000
#define CONFIG_SYS_SDRAM_SIZE 0x10000000 /* 256 megs */
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
/* NAND flash */
#ifdef CONFIG_CMD_NAND
#define CONFIG_NAND_ATMEL
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x40000000
#define CONFIG_SYS_NAND_MASK_ALE BIT(21)
#define CONFIG_SYS_NAND_MASK_CLE BIT(22)
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD4
#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD5
#define CONFIG_SYS_NAND_ONFI_DETECTION
#define CONFIG_MTD_DEVICE
#endif
/* PMECC & PMERRLOC */
#define CONFIG_ATMEL_NAND_HWECC
#define CONFIG_ATMEL_NAND_HW_PMECC
#define CONFIG_PMECC_CAP 8
#define CONFIG_PMECC_SECTOR_SIZE 512
#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
#ifdef CONFIG_SD_BOOT
/* bootstrap + u-boot + env + linux in sd card */
#define CONFIG_BOOTCOMMAND \
"fatload mmc 0:1 0x21000000 at91-sam9x60ek.dtb;" \
"fatload mmc 0:1 0x22000000 zImage;" \
"bootz 0x22000000 - 0x21000000"
#elif defined(CONFIG_NAND_BOOT)
/* bootstrap + u-boot + env + linux in nandflash */
#define CONFIG_ENV_OFFSET_REDUND 0x100000
#define CONFIG_BOOTCOMMAND "nand read " \
"0x22000000 0x200000 0x600000; " \
"nand read 0x21000000 0x180000 0x20000; " \
"bootz 0x22000000 - 0x21000000"
#elif defined(CONFIG_QSPI_BOOT)
/* bootstrap + u-boot + env + linux in SPI NOR flash */
#define CONFIG_BOOTCOMMAND "sf probe 0; " \
"sf read 0x21000000 0x180000 0x80000; " \
"sf read 0x22000000 0x200000 0x600000; " \
"bootz 0x22000000 - 0x21000000"
#endif
/*
* Size of malloc() pool
*/
#define CONFIG_SYS_MALLOC_LEN (512 * 1024 + 0x1000)
#endif

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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Configuration file for the SAMA5D27 WLSOM1 EK Board.
*
* Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries
*
* Author: Nicolas Ferre <nicolas.ferre@microcihp.com>
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#include "at91-sama5_common.h"
#undef CONFIG_SYS_AT91_MAIN_CLOCK
#define CONFIG_SYS_AT91_MAIN_CLOCK 24000000 /* from 24 MHz crystal */
/* SDRAM */
#define CONFIG_SYS_SDRAM_BASE 0x20000000
#define CONFIG_SYS_SDRAM_SIZE 0x10000000
#ifdef CONFIG_SPL_BUILD
#define CONFIG_SYS_INIT_SP_ADDR 0x218000
#else
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
#endif
#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
/* SPL */
#define CONFIG_SPL_TEXT_BASE 0x200000
#define CONFIG_SPL_MAX_SIZE 0x10000
#define CONFIG_SPL_BSS_START_ADDR 0x20000000
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
#define CONFIG_SYS_SPL_MALLOC_START 0x20080000
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
#define CONFIG_SYS_MONITOR_LEN (512 << 10)
#ifdef CONFIG_SD_BOOT
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
#endif
#endif