* Update for AT91RM9200DK and CMC_PU2 boards:
- Enable booting directly from flash - fix CMC_PU2 flash driver * Fix mkimage usage message
This commit is contained in:
wdenk
parent
cacfab588a
commit
9d5028c2f7
@ -2,6 +2,12 @@
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Changes since U-Boot 1.1.1:
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======================================================================
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* Update for AT91RM9200DK and CMC_PU2 boards:
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- Enable booting directly from flash
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- fix CMC_PU2 flash driver
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* Fix mkimage usage message
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* Map SRAM on NC650 board
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* Work around for Ethernet problems on Xaeniax board
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@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk
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LIB = lib$(BOARD).a
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OBJS := at91rm9200dk.o at45.o dm9161.o flash.o
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SOBJS :=
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SOBJS := memsetup.o
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$(LIB): $(OBJS) $(SOBJS)
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$(AR) crv $@ $(OBJS) $(SOBJS)
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@ -1 +1 @@
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TEXT_BASE = 0x21f80000
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TEXT_BASE = 0x21f00000
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200
board/at91rm9200dk/memsetup.S
Normal file
200
board/at91rm9200dk/memsetup.S
Normal file
@ -0,0 +1,200 @@
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/*
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* Memory Setup stuff - taken from blob memsetup.S
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*
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* Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
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* Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
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*
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* Modified for the at91rm9200dk board by
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* (C) Copyright 2004
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* Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <version.h>
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#ifdef CONFIG_BOOTBINFUNC
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/*
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* some parameters for the board
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*
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* This is based on rm9200dk.cfg for the BDI2000 from ABATRON which in
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* turn is based on the boot.bin code from ATMEL
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*
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*/
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/* flash */
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#define MC_PUIA 0xFFFFFF10
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#define MC_PUIA_VAL 0x00000000
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#define MC_PUP 0xFFFFFF50
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#define MC_PUP_VAL 0x00000000
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#define MC_PUER 0xFFFFFF54
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#define MC_PUER_VAL 0x00000000
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#define MC_ASR 0xFFFFFF04
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#define MC_ASR_VAL 0x00000000
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#define MC_AASR 0xFFFFFF08
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#define MC_AASR_VAL 0x00000000
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#define EBI_CFGR 0xFFFFFF64
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#define EBI_CFGR_VAL 0x00000000
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#define SMC2_CSR 0xFFFFFF70
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#define SMC2_CSR_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
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/* clocks */
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#define PLLAR 0xFFFFFC28
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#define PLLAR_VAL 0x20263E04 /* 179.712000 MHz for PCK */
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#define PLLBR 0xFFFFFC2C
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#define PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */
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#define MCKR 0xFFFFFC30
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#define MCKR_VAL 0x00000202 /* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */
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/* sdram */
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#define PIOC_ASR 0xFFFFF870
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#define PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
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#define PIOC_BSR 0xFFFFF804
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#define PIOC_BSR_VAL 0x00000000
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#define PIOC_PDR 0xFFFFF804
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#define PIOC_PDR_VAL 0xFFFF0000
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#define EBI_CSA 0xFFFFFF60
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#define EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */
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#define SDRC_CR 0xFFFFFF98
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#define SDRC_CR_VAL 0x2188c155 /* set up the SDRAM */
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#define SDRAM 0x20000000 /* address of the SDRAM */
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#define SDRAM1 0x20000080 /* address of the SDRAM */
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#define SDRAM_VAL 0x00000000 /* value written to SDRAM */
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#define SDRC_MR 0xFFFFFF90
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#define SDRC_MR_VAL 0x00000002 /* Precharge All */
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#define SDRC_MR_VAL1 0x00000004 /* refresh */
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#define SDRC_MR_VAL2 0x00000003 /* Load Mode Register */
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#define SDRC_MR_VAL3 0x00000000 /* Normal Mode */
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#define SDRC_TR 0xFFFFFF94
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#define SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
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_TEXT_BASE:
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.word TEXT_BASE
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.globl lowlevelinit
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lowlevelinit:
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/* memory control configuration */
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/* this isn't very elegant, but what the heck */
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ldr r0, =SMRDATA
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ldr r1, _TEXT_BASE
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sub r0, r0, r1
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add r2, r0, #80
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0:
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/* the address */
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ldr r1, [r0], #4
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/* the value */
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ldr r3, [r0], #4
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str r3, [r1]
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cmp r2, r0
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bne 0b
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/* delay - this is all done by guess */
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ldr r0, =0x00010000
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1:
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subs r0, r0, #1
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bhi 1b
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ldr r0, =SMRDATA1
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ldr r1, _TEXT_BASE
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sub r0, r0, r1
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add r2, r0, #176
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2:
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/* the address */
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ldr r1, [r0], #4
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/* the value */
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ldr r3, [r0], #4
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str r3, [r1]
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cmp r2, r0
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bne 2b
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/* everything is fine now */
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mov pc, lr
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.ltorg
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SMRDATA:
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.word MC_PUIA
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.word MC_PUIA_VAL
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.word MC_PUP
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.word MC_PUP_VAL
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.word MC_PUER
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.word MC_PUER_VAL
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.word MC_ASR
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.word MC_ASR_VAL
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.word MC_AASR
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.word MC_AASR_VAL
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.word EBI_CFGR
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.word EBI_CFGR_VAL
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.word SMC2_CSR
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.word SMC2_CSR_VAL
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.word PLLAR
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.word PLLAR_VAL
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.word PLLBR
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.word PLLBR_VAL
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.word MCKR
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.word MCKR_VAL
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/* SMRDATA is 80 bytes long */
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/* here there's a delay of 100 */
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SMRDATA1:
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.word PIOC_ASR
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.word PIOC_ASR_VAL
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.word PIOC_BSR
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.word PIOC_BSR_VAL
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.word PIOC_PDR
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.word PIOC_PDR_VAL
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.word EBI_CSA
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.word EBI_CSA_VAL
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.word SDRC_CR
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.word SDRC_CR_VAL
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.word SDRC_MR
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.word SDRC_MR_VAL
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.word SDRAM
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.word SDRAM_VAL
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.word SDRC_MR
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.word SDRC_MR_VAL1
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.word SDRAM
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.word SDRAM_VAL
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.word SDRAM
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.word SDRAM_VAL
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.word SDRAM
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.word SDRAM_VAL
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.word SDRAM
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.word SDRAM_VAL
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.word SDRAM
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.word SDRAM_VAL
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.word SDRAM
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.word SDRAM_VAL
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.word SDRAM
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.word SDRAM_VAL
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.word SDRAM
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.word SDRAM_VAL
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.word SDRC_MR
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.word SDRC_MR_VAL2
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.word SDRAM1
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.word SDRAM_VAL
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.word SDRC_TR
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.word SDRC_TR_VAL
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.word SDRAM
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.word SDRAM_VAL
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.word SDRC_MR
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.word SDRC_MR_VAL3
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.word SDRAM
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.word SDRAM_VAL
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/* SMRDATA1 is 176 bytes long */
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#endif /* CONFIG_BOOTBINFUNC */
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@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
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LIB = lib$(BOARD).a
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OBJS := at91rm9200dk.o at45.o dm9161.o flash.o
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OBJS := cmc_pu2.o at45.o dm9161.o flash.o
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SOBJS := memsetup.o
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$(LIB): $(OBJS) $(SOBJS)
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@ -1,118 +0,0 @@
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/*
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* (C) Copyright 2002
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Marius Groeger <mgroeger@sysgo.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/arch/AT91RM9200.h>
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/* ------------------------------------------------------------------------- */
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/*
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* Miscelaneous platform dependent initialisations
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*/
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int board_init (void)
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{
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DECLARE_GLOBAL_DATA_PTR;
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/* Enable Ctrlc */
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console_init_f ();
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/* Correct IRDA resistor problem */
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/* Set PA23_TXD in Output */
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(AT91PS_PIO) AT91C_BASE_PIOA->PIO_OER = AT91C_PA23_TXD2;
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/* memory and cpu-speed are setup before relocation */
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/* so we do _nothing_ here */
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/* arch number of AT91RM9200DK-Board */
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gd->bd->bi_arch_number = 251;
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/* adress of boot parameters */
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gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
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return 0;
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}
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int dram_init (void)
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{
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DECLARE_GLOBAL_DATA_PTR;
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gd->bd->bi_dram[0].start = PHYS_SDRAM;
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gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
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return 0;
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}
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/*
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* Disk On Chip (NAND) Millenium initialization.
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* The NAND lives in the CS2* space
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*/
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#if (CONFIG_COMMANDS & CFG_CMD_NAND)
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extern ulong nand_probe (ulong physadr);
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#define AT91_SMARTMEDIA_BASE 0x40000000 /* physical address to access memory on NCS3 */
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void nand_init (void)
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{
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/* Setup Smart Media, fitst enable the address range of CS3 */
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*AT91C_EBI_CSA |= AT91C_EBI_CS3A_SMC_SmartMedia;
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/* set the bus interface characteristics based on
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tDS Data Set up Time 30 - ns
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tDH Data Hold Time 20 - ns
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tALS ALE Set up Time 20 - ns
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16ns at 60 MHz ~= 3 */
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/*memory mapping structures */
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#define SM_ID_RWH (5 << 28)
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#define SM_RWH (1 << 28)
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#define SM_RWS (0 << 24)
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#define SM_TDF (1 << 8)
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#define SM_NWS (3)
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AT91C_BASE_SMC2->SMC2_CSR[3] = (SM_RWH | SM_RWS |
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AT91C_SMC2_ACSS_STANDARD | AT91C_SMC2_DBW_8 |
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SM_TDF | AT91C_SMC2_WSEN | SM_NWS);
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/* enable the SMOE line PC0=SMCE, A21=CLE, A22=ALE */
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*AT91C_PIOC_ASR = AT91C_PC0_BFCK | AT91C_PC1_BFRDY_SMOE |
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AT91C_PC3_BFBAA_SMWE;
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*AT91C_PIOC_PDR = AT91C_PC0_BFCK | AT91C_PC1_BFRDY_SMOE |
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AT91C_PC3_BFBAA_SMWE;
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/* Configure PC2 as input (signal READY of the SmartMedia) */
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*AT91C_PIOC_PER = AT91C_PC2_BFAVD; /* enable direct output enable */
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*AT91C_PIOC_ODR = AT91C_PC2_BFAVD; /* disable output */
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/* Configure PB1 as input (signal Card Detect of the SmartMedia) */
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*AT91C_PIOB_PER = AT91C_PIO_PB1; /* enable direct output enable */
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*AT91C_PIOB_ODR = AT91C_PIO_PB1; /* disable output */
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/* PIOB and PIOC clock enabling */
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*AT91C_PMC_PCER = 1 << AT91C_ID_PIOB;
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*AT91C_PMC_PCER = 1 << AT91C_ID_PIOC;
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if (*AT91C_PIOB_PDSR & AT91C_PIO_PB1)
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printf (" No SmartMedia card inserted\n");
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#ifdef DEBUG
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printf (" SmartMedia card inserted\n");
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printf ("Probing at 0x%.8x\n", AT91_SMARTMEDIA_BASE);
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#endif
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printf ("%4lu MB\n", nand_probe(AT91_SMARTMEDIA_BASE) >> 20);
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}
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#endif
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67
board/cmc_pu2/cmc_pu2.c
Normal file
67
board/cmc_pu2/cmc_pu2.c
Normal file
@ -0,0 +1,67 @@
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/*
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* (C) Copyright 2002
|
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
|
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* Marius Groeger <mgroeger@sysgo.de>
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*
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* Modified for CMC_PU2 (removed Smart Media support) by Gary Jennejohn
|
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* (2004) garyj@denx.de
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*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
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#include <asm/mach-types.h>
|
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#include <asm/arch/AT91RM9200.h>
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
/*
|
||||
* Miscelaneous platform dependent initialisations
|
||||
*/
|
||||
|
||||
int board_init (void)
|
||||
{
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
/* Enable Ctrlc */
|
||||
console_init_f ();
|
||||
|
||||
/* Correct IRDA resistor problem */
|
||||
/* Set PA23_TXD in Output */
|
||||
(AT91PS_PIO) AT91C_BASE_PIOA->PIO_OER = AT91C_PA23_TXD2;
|
||||
|
||||
/* memory and cpu-speed are setup before relocation */
|
||||
/* so we do _nothing_ here */
|
||||
|
||||
/* arch number of CMC_PU2-Board */
|
||||
/* gd->bd->bi_arch_number = MACH_TYPE_CMC_PU2; */
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gd->bd->bi_arch_number = 251;
|
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/* adress of boot parameters */
|
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gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
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|
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return 0;
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}
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|
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int dram_init (void)
|
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{
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DECLARE_GLOBAL_DATA_PTR;
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|
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gd->bd->bi_dram[0].start = PHYS_SDRAM;
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gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
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return 0;
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}
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||||
@ -1 +1 @@
|
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TEXT_BASE = 0x21f00000
|
||||
TEXT_BASE = 0x20f00000
|
||||
|
||||
@ -1,11 +1,12 @@
|
||||
/*
|
||||
* (C) Copyright 2002
|
||||
* Lineo, Inc. <www.lineo.com>
|
||||
* Bernhard Kuhn <bkuhn@lineo.com>
|
||||
* (C) Copyright 2003-2004
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* (C) Copyright 2002
|
||||
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
|
||||
* Alex Zuepke <azu@sysgo.de>
|
||||
* (C) Copyright 2004
|
||||
* Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
|
||||
*
|
||||
* Modified for the CMC PU2 by (C) Copyright 2004 Gary Jennejohn
|
||||
* garyj@denx.de
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
@ -28,444 +29,339 @@
|
||||
|
||||
#include <common.h>
|
||||
|
||||
ulong myflush(void);
|
||||
flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
|
||||
|
||||
/*
|
||||
* CPU to flash interface is 32-bit, so make declaration accordingly
|
||||
*/
|
||||
typedef unsigned short FLASH_PORT_WIDTH;
|
||||
typedef volatile unsigned short FLASH_PORT_WIDTHV;
|
||||
|
||||
/* Flash Organization Structure */
|
||||
typedef struct OrgDef
|
||||
{
|
||||
unsigned int sector_number;
|
||||
unsigned int sector_size;
|
||||
} OrgDef;
|
||||
#define FPW FLASH_PORT_WIDTH
|
||||
#define FPWV FLASH_PORT_WIDTHV
|
||||
|
||||
|
||||
/* Flash Organizations */
|
||||
OrgDef OrgAT49BV16x4[] =
|
||||
{
|
||||
{ 8, 8*1024 }, /* 8 * 8 kBytes sectors */
|
||||
{ 2, 32*1024 }, /* 2 * 32 kBytes sectors */
|
||||
{ 30, 64*1024 }, /* 30 * 64 kBytes sectors */
|
||||
};
|
||||
|
||||
OrgDef OrgAT49BV16x4A[] =
|
||||
{
|
||||
{ 8, 8*1024 }, /* 8 * 8 kBytes sectors */
|
||||
{ 31, 64*1024 }, /* 31 * 64 kBytes sectors */
|
||||
};
|
||||
|
||||
OrgDef OrgAT49BV6416[] =
|
||||
{
|
||||
{ 8, 8*1024 }, /* 8 * 8 kBytes sectors */
|
||||
{ 127, 64*1024 }, /* 127 * 64 kBytes sectors */
|
||||
};
|
||||
|
||||
flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
|
||||
|
||||
/* AT49BV1614A Codes */
|
||||
#define FLASH_CODE1 0xAA
|
||||
#define FLASH_CODE2 0x55
|
||||
#define ID_IN_CODE 0x90
|
||||
#define ID_OUT_CODE 0xF0
|
||||
|
||||
|
||||
#define CMD_READ_ARRAY 0x00F0
|
||||
#define CMD_UNLOCK1 0x00AA
|
||||
#define CMD_UNLOCK2 0x0055
|
||||
#define CMD_ERASE_SETUP 0x0080
|
||||
#define CMD_ERASE_CONFIRM 0x0030
|
||||
#define CMD_PROGRAM 0x00A0
|
||||
#define CMD_UNLOCK_BYPASS 0x0020
|
||||
#define CMD_SECTOR_UNLOCK 0x0070
|
||||
|
||||
#define MEM_FLASH_ADDR1 (*(volatile u16 *)(CFG_FLASH_BASE + (0x00005555<<1)))
|
||||
#define MEM_FLASH_ADDR2 (*(volatile u16 *)(CFG_FLASH_BASE + (0x00002AAA<<1)))
|
||||
|
||||
#define BIT_ERASE_DONE 0x0080
|
||||
#define BIT_RDY_MASK 0x0080
|
||||
#define BIT_PROGRAM_ERROR 0x0020
|
||||
#define BIT_TIMEOUT 0x80000000 /* our flag */
|
||||
|
||||
#define READY 1
|
||||
#define ERR 2
|
||||
#define TMO 4
|
||||
#define FLASH_CYCLE1 0x0555
|
||||
#define FLASH_CYCLE2 0x02aa
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Functions
|
||||
*/
|
||||
void flash_identification (flash_info_t * info)
|
||||
static ulong flash_get_size(FPWV *addr, flash_info_t *info);
|
||||
static void flash_reset(flash_info_t *info);
|
||||
static int write_word_amd(flash_info_t *info, FPWV *dest, FPW data);
|
||||
static flash_info_t *flash_get_info(ulong base);
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* flash_init()
|
||||
*
|
||||
* sets up flash_info and returns size of FLASH (bytes)
|
||||
*/
|
||||
unsigned long flash_init (void)
|
||||
{
|
||||
volatile u16 manuf_code, device_code, add_device_code;
|
||||
unsigned long size = 0;
|
||||
ulong flashbase = CFG_FLASH_BASE;
|
||||
|
||||
MEM_FLASH_ADDR1 = FLASH_CODE1;
|
||||
MEM_FLASH_ADDR2 = FLASH_CODE2;
|
||||
MEM_FLASH_ADDR1 = ID_IN_CODE;
|
||||
/* Init: no FLASHes known */
|
||||
memset(&flash_info[0], 0, sizeof(flash_info_t));
|
||||
|
||||
manuf_code = *(volatile u16 *) CFG_FLASH_BASE;
|
||||
device_code = *(volatile u16 *) (CFG_FLASH_BASE + 2);
|
||||
add_device_code = *(volatile u16 *) (CFG_FLASH_BASE + (3 << 1));
|
||||
flash_info[0].size =
|
||||
flash_get_size((FPW *)flashbase, &flash_info[0]);
|
||||
|
||||
MEM_FLASH_ADDR1 = FLASH_CODE1;
|
||||
MEM_FLASH_ADDR2 = FLASH_CODE2;
|
||||
MEM_FLASH_ADDR1 = ID_OUT_CODE;
|
||||
size = flash_info[0].size;
|
||||
|
||||
/* Vendor type */
|
||||
info->flash_id = ATM_MANUFACT & FLASH_VENDMASK;
|
||||
printf ("Atmel: ");
|
||||
#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
|
||||
/* monitor protection ON by default */
|
||||
flash_protect(FLAG_PROTECT_SET,
|
||||
CFG_MONITOR_BASE,
|
||||
CFG_MONITOR_BASE+monitor_flash_len-1,
|
||||
flash_get_info(CFG_MONITOR_BASE));
|
||||
#endif
|
||||
|
||||
if ((device_code & FLASH_TYPEMASK) == (ATM_ID_BV1614 & FLASH_TYPEMASK)) {
|
||||
#ifdef CFG_ENV_IS_IN_FLASH
|
||||
/* ENV protection ON by default */
|
||||
flash_protect(FLAG_PROTECT_SET,
|
||||
CFG_ENV_ADDR,
|
||||
CFG_ENV_ADDR+CFG_ENV_SIZE-1,
|
||||
flash_get_info(CFG_ENV_ADDR));
|
||||
#endif
|
||||
|
||||
if ((add_device_code & FLASH_TYPEMASK) ==
|
||||
(ATM_ID_BV1614A & FLASH_TYPEMASK)) {
|
||||
info->flash_id |= ATM_ID_BV1614A & FLASH_TYPEMASK;
|
||||
printf ("AT49BV1614A (16Mbit)\n");
|
||||
} else { /* AT49BV1614 Flash */
|
||||
info->flash_id |= ATM_ID_BV1614 & FLASH_TYPEMASK;
|
||||
printf ("AT49BV1614 (16Mbit)\n");
|
||||
}
|
||||
|
||||
} else if ((device_code & FLASH_TYPEMASK) == (ATM_ID_BV6416 & FLASH_TYPEMASK)) {
|
||||
info->flash_id |= ATM_ID_BV6416 & FLASH_TYPEMASK;
|
||||
printf ("AT49BV6416 (64Mbit)\n");
|
||||
}
|
||||
}
|
||||
|
||||
ushort flash_number_sector(OrgDef *pOrgDef, unsigned int nb_blocks)
|
||||
{
|
||||
int i, nb_sectors = 0;
|
||||
|
||||
for (i=0; i<nb_blocks; i++){
|
||||
nb_sectors += pOrgDef[i].sector_number;
|
||||
}
|
||||
|
||||
return nb_sectors;
|
||||
}
|
||||
|
||||
void flash_unlock_sector(flash_info_t * info, unsigned int sector)
|
||||
{
|
||||
volatile u16 *addr = (volatile u16 *) (info->start[sector]);
|
||||
|
||||
MEM_FLASH_ADDR1 = CMD_UNLOCK1;
|
||||
*addr = CMD_SECTOR_UNLOCK;
|
||||
}
|
||||
|
||||
|
||||
ulong flash_init (void)
|
||||
{
|
||||
int i, j, k;
|
||||
unsigned int flash_nb_blocks, sector;
|
||||
unsigned int start_address;
|
||||
OrgDef *pOrgDef;
|
||||
|
||||
ulong size = 0;
|
||||
|
||||
for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
|
||||
ulong flashbase = 0;
|
||||
|
||||
flash_identification (&flash_info[i]);
|
||||
|
||||
if ((flash_info[i].flash_id & FLASH_TYPEMASK) ==
|
||||
(ATM_ID_BV1614 & FLASH_TYPEMASK)) {
|
||||
|
||||
pOrgDef = OrgAT49BV16x4;
|
||||
flash_nb_blocks = sizeof (OrgAT49BV16x4) / sizeof (OrgDef);
|
||||
} else if ((flash_info[i].flash_id & FLASH_TYPEMASK) ==
|
||||
(ATM_ID_BV1614A & FLASH_TYPEMASK)){ /* AT49BV1614A Flash */
|
||||
|
||||
pOrgDef = OrgAT49BV16x4A;
|
||||
flash_nb_blocks = sizeof (OrgAT49BV16x4A) / sizeof (OrgDef);
|
||||
} else if ((flash_info[i].flash_id & FLASH_TYPEMASK) ==
|
||||
(ATM_ID_BV6416 & FLASH_TYPEMASK)){ /* AT49BV6416 Flash */
|
||||
|
||||
pOrgDef = OrgAT49BV6416;
|
||||
flash_nb_blocks = sizeof (OrgAT49BV6416) / sizeof (OrgDef);
|
||||
} else {
|
||||
flash_nb_blocks = 0;
|
||||
pOrgDef = OrgAT49BV16x4;
|
||||
}
|
||||
|
||||
flash_info[i].sector_count = flash_number_sector(pOrgDef, flash_nb_blocks);
|
||||
memset (flash_info[i].protect, 0, flash_info[i].sector_count);
|
||||
|
||||
if (i == 0)
|
||||
flashbase = PHYS_FLASH_1;
|
||||
else
|
||||
panic ("configured too many flash banks!\n");
|
||||
|
||||
sector = 0;
|
||||
start_address = flashbase;
|
||||
flash_info[i].size = 0;
|
||||
|
||||
for (j = 0; j < flash_nb_blocks; j++) {
|
||||
for (k = 0; k < pOrgDef[j].sector_number; k++) {
|
||||
flash_info[i].start[sector++] = start_address;
|
||||
start_address += pOrgDef[j].sector_size;
|
||||
flash_info[i].size += pOrgDef[j].sector_size;
|
||||
}
|
||||
}
|
||||
|
||||
size += flash_info[i].size;
|
||||
|
||||
if ((flash_info[i].flash_id & FLASH_TYPEMASK) ==
|
||||
(ATM_ID_BV6416 & FLASH_TYPEMASK)){ /* AT49BV6416 Flash */
|
||||
|
||||
/* Unlock all sectors at reset */
|
||||
for (j=0; j<flash_info[i].sector_count; j++){
|
||||
flash_unlock_sector(&flash_info[i], j);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Protect binary boot image */
|
||||
flash_protect (FLAG_PROTECT_SET,
|
||||
CFG_FLASH_BASE,
|
||||
CFG_FLASH_BASE + CFG_BOOT_SIZE - 1, &flash_info[0]);
|
||||
|
||||
/* Protect environment variables */
|
||||
flash_protect (FLAG_PROTECT_SET,
|
||||
CFG_ENV_ADDR,
|
||||
CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]);
|
||||
|
||||
/* Protect U-Boot gzipped image */
|
||||
flash_protect (FLAG_PROTECT_SET,
|
||||
CFG_U_BOOT_BASE,
|
||||
CFG_U_BOOT_BASE + CFG_U_BOOT_SIZE - 1, &flash_info[0]);
|
||||
|
||||
return size;
|
||||
return size ? size : 1;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
void flash_print_info (flash_info_t * info)
|
||||
static void flash_reset(flash_info_t *info)
|
||||
{
|
||||
FPWV *base = (FPWV *)(info->start[0]);
|
||||
|
||||
/* Put FLASH back in read mode */
|
||||
if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL)
|
||||
*base = (FPW)0x00FF00FF; /* Intel Read Mode */
|
||||
else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD)
|
||||
*base = (FPW)0x00F000F0; /* AMD Read Mode */
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
static flash_info_t *flash_get_info(ulong base)
|
||||
{
|
||||
int i;
|
||||
flash_info_t * info;
|
||||
|
||||
info = NULL;
|
||||
for (i = 0; i < CFG_MAX_FLASH_BANKS; i ++) {
|
||||
info = & flash_info[i];
|
||||
if (info->size && info->start[0] <= base &&
|
||||
base <= info->start[0] + info->size - 1)
|
||||
break;
|
||||
}
|
||||
|
||||
return i == CFG_MAX_FLASH_BANKS ? 0 : info;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
void flash_print_info (flash_info_t *info)
|
||||
{
|
||||
int i;
|
||||
|
||||
if (info->flash_id == FLASH_UNKNOWN) {
|
||||
printf ("missing or unknown FLASH type\n");
|
||||
return;
|
||||
}
|
||||
|
||||
switch (info->flash_id & FLASH_VENDMASK) {
|
||||
case (ATM_MANUFACT & FLASH_VENDMASK):
|
||||
printf ("Atmel: ");
|
||||
break;
|
||||
default:
|
||||
printf ("Unknown Vendor ");
|
||||
break;
|
||||
case FLASH_MAN_AMD: printf ("AMD "); break;
|
||||
case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break;
|
||||
case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
|
||||
case FLASH_MAN_SST: printf ("SST "); break;
|
||||
case FLASH_MAN_STM: printf ("STM "); break;
|
||||
case FLASH_MAN_INTEL: printf ("INTEL "); break;
|
||||
default: printf ("Unknown Vendor "); break;
|
||||
}
|
||||
|
||||
switch (info->flash_id & FLASH_TYPEMASK) {
|
||||
case (ATM_ID_BV1614 & FLASH_TYPEMASK):
|
||||
printf ("AT49BV1614 (16Mbit)\n");
|
||||
break;
|
||||
case (ATM_ID_BV1614A & FLASH_TYPEMASK):
|
||||
printf ("AT49BV1614A (16Mbit)\n");
|
||||
break;
|
||||
case (ATM_ID_BV6416 & FLASH_TYPEMASK):
|
||||
printf ("AT49BV6416 (64Mbit)\n");
|
||||
case FLASH_S29GL064M:
|
||||
printf ("S29GL064M-R6 (64Mbit, uniform sector size)\n");
|
||||
break;
|
||||
default:
|
||||
printf ("Unknown Chip Type\n");
|
||||
goto Done;
|
||||
break;
|
||||
}
|
||||
|
||||
printf (" Size: %ld MB in %d Sectors\n",
|
||||
info->size >> 20, info->sector_count);
|
||||
info->size >> 20,
|
||||
info->sector_count);
|
||||
|
||||
printf (" Sector Start Addresses:");
|
||||
for (i = 0; i < info->sector_count; i++) {
|
||||
|
||||
for (i=0; i<info->sector_count; ++i) {
|
||||
if ((i % 5) == 0) {
|
||||
printf ("\n ");
|
||||
}
|
||||
printf (" %08lX%s", info->start[i],
|
||||
printf (" %08lX%s",
|
||||
info->start[i],
|
||||
info->protect[i] ? " (RO)" : " ");
|
||||
}
|
||||
printf ("\n");
|
||||
|
||||
Done: ;
|
||||
return;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
int flash_erase (flash_info_t * info, int s_first, int s_last)
|
||||
/*
|
||||
* The following code cannot be run from FLASH!
|
||||
*/
|
||||
|
||||
ulong flash_get_size (FPWV *addr, flash_info_t *info)
|
||||
{
|
||||
ulong result;
|
||||
int iflag, cflag, prot, sect;
|
||||
int rc = ERR_OK;
|
||||
int chip1;
|
||||
int i;
|
||||
ulong base = (ulong)addr;
|
||||
|
||||
/* first look for protection bits */
|
||||
/* Write auto select command: read Manufacturer ID */
|
||||
/* Write auto select command sequence and test FLASH answer */
|
||||
addr[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* for AMD, Intel ignores this */
|
||||
addr[FLASH_CYCLE2] = (FPW)0x00550055; /* for AMD, Intel ignores this */
|
||||
addr[FLASH_CYCLE1] = (FPW)0x00900090; /* selects Intel or AMD */
|
||||
|
||||
if (info->flash_id == FLASH_UNKNOWN)
|
||||
return ERR_UNKNOWN_FLASH_TYPE;
|
||||
/* The manufacturer codes are only 1 byte, so just use 1 byte.
|
||||
* This works for any bus width and any FLASH device width.
|
||||
*/
|
||||
udelay(100);
|
||||
switch (addr[0] & 0xff) {
|
||||
|
||||
if ((s_first < 0) || (s_first > s_last)) {
|
||||
return ERR_INVAL;
|
||||
case (uchar)AMD_MANUFACT:
|
||||
printf ("Manufacturer: AMD (Spansion)\n");
|
||||
info->flash_id = FLASH_MAN_AMD;
|
||||
break;
|
||||
|
||||
case (uchar)INTEL_MANUFACT:
|
||||
printf ("Manufacturer: Intel (not supported yet)\n");
|
||||
info->flash_id = FLASH_MAN_INTEL;
|
||||
break;
|
||||
|
||||
default:
|
||||
info->flash_id = FLASH_UNKNOWN;
|
||||
info->sector_count = 0;
|
||||
info->size = 0;
|
||||
break;
|
||||
}
|
||||
|
||||
if ((info->flash_id & FLASH_VENDMASK) !=
|
||||
(ATM_MANUFACT & FLASH_VENDMASK)) {
|
||||
return ERR_UNKNOWN_FLASH_VENDOR;
|
||||
/* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */
|
||||
if (info->flash_id != FLASH_UNKNOWN) switch ((FPW)addr[1]) {
|
||||
|
||||
case AMD_ID_MIRROR:
|
||||
printf ("Mirror Bit flash: addr[14] = %08X addr[15] = %08X\n",
|
||||
addr[14], addr[15]);
|
||||
|
||||
switch(addr[14] & 0xffff) {
|
||||
case (AMD_ID_GL064M_2 & 0xffff):
|
||||
if (addr[15] != (AMD_ID_GL064M_3 & 0xffff)) {
|
||||
printf ("Chip: S29GLxxxM -> unknown\n");
|
||||
info->flash_id = FLASH_UNKNOWN;
|
||||
info->sector_count = 0;
|
||||
info->size = 0;
|
||||
} else {
|
||||
printf ("Chip: S29GL064M-R6\n");
|
||||
info->flash_id += FLASH_S29GL064M;
|
||||
info->sector_count = 128;
|
||||
info->size = 0x00800000;
|
||||
for (i = 0; i < info->sector_count; i++) {
|
||||
info->start[i] = base;
|
||||
base += 0x10000;
|
||||
}
|
||||
}
|
||||
break; /* => 16 MB */
|
||||
default:
|
||||
printf ("Chip: *** unknown ***\n");
|
||||
info->flash_id = FLASH_UNKNOWN;
|
||||
info->sector_count = 0;
|
||||
info->size = 0;
|
||||
break;
|
||||
}
|
||||
break;
|
||||
|
||||
default:
|
||||
info->flash_id = FLASH_UNKNOWN;
|
||||
info->sector_count = 0;
|
||||
info->size = 0;
|
||||
}
|
||||
|
||||
/* Put FLASH back in read mode */
|
||||
flash_reset(info);
|
||||
|
||||
return (info->size);
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
int flash_erase (flash_info_t *info, int s_first, int s_last)
|
||||
{
|
||||
FPWV *addr = (FPWV *)(info->start[0]);
|
||||
int flag, prot, sect, l_sect;
|
||||
ulong start, now, last;
|
||||
|
||||
printf ("flash_erase: first: %d last: %d\n", s_first, s_last);
|
||||
|
||||
if ((s_first < 0) || (s_first > s_last)) {
|
||||
if (info->flash_id == FLASH_UNKNOWN) {
|
||||
printf ("- missing\n");
|
||||
} else {
|
||||
printf ("- no sectors to erase\n");
|
||||
}
|
||||
return 1;
|
||||
}
|
||||
|
||||
if ((info->flash_id == FLASH_UNKNOWN) ||
|
||||
(info->flash_id > FLASH_AMD_COMP)) {
|
||||
printf ("Can't erase unknown flash type %08lx - aborted\n",
|
||||
info->flash_id);
|
||||
return 1;
|
||||
}
|
||||
|
||||
prot = 0;
|
||||
for (sect = s_first; sect <= s_last; ++sect) {
|
||||
for (sect=s_first; sect<=s_last; ++sect) {
|
||||
if (info->protect[sect]) {
|
||||
prot++;
|
||||
}
|
||||
}
|
||||
if (prot)
|
||||
return ERR_PROTECTED;
|
||||
|
||||
/*
|
||||
* Disable interrupts which might cause a timeout
|
||||
* here. Remember that our exception vectors are
|
||||
* at address 0 in the flash, and we don't want a
|
||||
* (ticker) exception to happen while the flash
|
||||
* chip is in programming mode.
|
||||
*/
|
||||
cflag = icache_status ();
|
||||
icache_disable ();
|
||||
iflag = disable_interrupts ();
|
||||
if (prot) {
|
||||
printf ("- Warning: %d protected sectors will not be erased!\n",
|
||||
prot);
|
||||
} else {
|
||||
printf ("\n");
|
||||
}
|
||||
|
||||
l_sect = -1;
|
||||
|
||||
/* Disable interrupts which might cause a timeout here */
|
||||
flag = disable_interrupts();
|
||||
|
||||
addr[0x0555] = 0x00AA;
|
||||
addr[0x02AA] = 0x0055;
|
||||
addr[0x0555] = 0x0080;
|
||||
addr[0x0555] = 0x00AA;
|
||||
addr[0x02AA] = 0x0055;
|
||||
|
||||
/* Start erase on unprotected sectors */
|
||||
for (sect = s_first; sect <= s_last && !ctrlc (); sect++) {
|
||||
printf ("Erasing sector %2d ... ", sect);
|
||||
|
||||
/* arm simple, non interrupt dependent timer */
|
||||
reset_timer_masked ();
|
||||
|
||||
for (sect = s_first; sect<=s_last; sect++) {
|
||||
if (info->protect[sect] == 0) { /* not protected */
|
||||
volatile u16 *addr = (volatile u16 *) (info->start[sect]);
|
||||
|
||||
MEM_FLASH_ADDR1 = CMD_UNLOCK1;
|
||||
MEM_FLASH_ADDR2 = CMD_UNLOCK2;
|
||||
MEM_FLASH_ADDR1 = CMD_ERASE_SETUP;
|
||||
|
||||
MEM_FLASH_ADDR1 = CMD_UNLOCK1;
|
||||
MEM_FLASH_ADDR2 = CMD_UNLOCK2;
|
||||
*addr = CMD_ERASE_CONFIRM;
|
||||
|
||||
/* wait until flash is ready */
|
||||
chip1 = 0;
|
||||
|
||||
do {
|
||||
result = *addr;
|
||||
|
||||
/* check timeout */
|
||||
if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) {
|
||||
MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
|
||||
chip1 = TMO;
|
||||
break;
|
||||
}
|
||||
|
||||
if (!chip1 && (result & 0xFFFF) & BIT_ERASE_DONE)
|
||||
chip1 = READY;
|
||||
|
||||
} while (!chip1);
|
||||
|
||||
MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
|
||||
|
||||
if (chip1 == ERR) {
|
||||
rc = ERR_PROG_ERROR;
|
||||
goto outahere;
|
||||
}
|
||||
if (chip1 == TMO) {
|
||||
rc = ERR_TIMOUT;
|
||||
goto outahere;
|
||||
}
|
||||
|
||||
printf ("ok.\n");
|
||||
} else { /* it was protected */
|
||||
printf ("protected!\n");
|
||||
addr = (FPWV *)(info->start[sect]);
|
||||
addr[0] = 0x0030;
|
||||
l_sect = sect;
|
||||
}
|
||||
}
|
||||
|
||||
if (ctrlc ())
|
||||
printf ("User Interrupt!\n");
|
||||
/* re-enable interrupts if necessary */
|
||||
if (flag)
|
||||
enable_interrupts();
|
||||
|
||||
outahere:
|
||||
/* allow flash to settle - wait 10 ms */
|
||||
udelay_masked (10000);
|
||||
|
||||
if (iflag)
|
||||
enable_interrupts ();
|
||||
|
||||
if (cflag)
|
||||
icache_enable ();
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Copy memory to flash
|
||||
*/
|
||||
|
||||
volatile static int write_word (flash_info_t * info, ulong dest,
|
||||
ulong data)
|
||||
{
|
||||
volatile u16 *addr = (volatile u16 *) dest;
|
||||
ulong result;
|
||||
int rc = ERR_OK;
|
||||
int cflag, iflag;
|
||||
int chip1;
|
||||
/* wait at least 80us - let's wait 1 ms */
|
||||
udelay (1000);
|
||||
|
||||
/*
|
||||
* Check if Flash is (sufficiently) erased
|
||||
* We wait for the last triggered sector
|
||||
*/
|
||||
result = *addr;
|
||||
if ((result & data) != data)
|
||||
return ERR_NOT_ERASED;
|
||||
if (l_sect < 0)
|
||||
goto DONE;
|
||||
|
||||
|
||||
/*
|
||||
* Disable interrupts which might cause a timeout
|
||||
* here. Remember that our exception vectors are
|
||||
* at address 0 in the flash, and we don't want a
|
||||
* (ticker) exception to happen while the flash
|
||||
* chip is in programming mode.
|
||||
*/
|
||||
cflag = icache_status ();
|
||||
icache_disable ();
|
||||
iflag = disable_interrupts ();
|
||||
|
||||
MEM_FLASH_ADDR1 = CMD_UNLOCK1;
|
||||
MEM_FLASH_ADDR2 = CMD_UNLOCK2;
|
||||
MEM_FLASH_ADDR1 = CMD_PROGRAM;
|
||||
*addr = data;
|
||||
|
||||
/* arm simple, non interrupt dependent timer */
|
||||
reset_timer_masked ();
|
||||
|
||||
/* wait until flash is ready */
|
||||
chip1 = 0;
|
||||
do {
|
||||
result = *addr;
|
||||
|
||||
/* check timeout */
|
||||
if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) {
|
||||
chip1 = ERR | TMO;
|
||||
break;
|
||||
start = get_timer (0);
|
||||
last = start;
|
||||
addr = (FPWV *)(info->start[l_sect]);
|
||||
while ((addr[0] & 0x00000080) != 0x00000080) {
|
||||
if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
|
||||
printf ("Timeout\n");
|
||||
return 1;
|
||||
}
|
||||
/* show that we're waiting */
|
||||
if ((now - last) > 1000) { /* every second */
|
||||
putc ('.');
|
||||
last = now;
|
||||
}
|
||||
}
|
||||
if (!chip1 && ((result & 0x80) == (data & 0x80)))
|
||||
chip1 = READY;
|
||||
|
||||
} while (!chip1);
|
||||
DONE:
|
||||
/* reset to read mode */
|
||||
addr = (FPWV *)info->start[0];
|
||||
addr[0] = 0x000000F0; /* reset bank */
|
||||
|
||||
*addr = CMD_READ_ARRAY;
|
||||
|
||||
if (chip1 == ERR || *addr != data)
|
||||
rc = ERR_PROG_ERROR;
|
||||
|
||||
if (iflag)
|
||||
enable_interrupts ();
|
||||
|
||||
if (cflag)
|
||||
icache_enable ();
|
||||
|
||||
return rc;
|
||||
printf (" done\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Copy memory to flash.
|
||||
* Copy memory to flash, returns:
|
||||
* 0 - OK
|
||||
* 1 - write timeout
|
||||
* 2 - Flash not erased
|
||||
*/
|
||||
|
||||
int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
|
||||
int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
|
||||
{
|
||||
ulong wp, data;
|
||||
int rc;
|
||||
@ -483,8 +379,8 @@ int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
|
||||
wp = addr;
|
||||
|
||||
while (cnt >= 2) {
|
||||
data = *((volatile u16 *) src);
|
||||
if ((rc = write_word (info, wp, data)) != 0) {
|
||||
data = *((FPWV *)src);
|
||||
if ((rc = write_word_amd(info, (FPW *)wp, data)) != 0) {
|
||||
return (rc);
|
||||
}
|
||||
src += 2;
|
||||
@ -492,16 +388,68 @@ int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
|
||||
cnt -= 2;
|
||||
}
|
||||
|
||||
if (cnt == 0) {
|
||||
return (0);
|
||||
}
|
||||
|
||||
if (cnt == 1) {
|
||||
data = (*((volatile u8 *) src)) | (*((volatile u8 *) (wp + 1)) <<
|
||||
8);
|
||||
if ((rc = write_word (info, wp, data)) != 0) {
|
||||
data = (*((volatile u8 *) src)) | (*((volatile u8 *) (wp + 1))
|
||||
<< 8);
|
||||
if ((rc = write_word_amd(info, (FPW *)wp, data)) != 0) {
|
||||
return (rc);
|
||||
}
|
||||
src += 1;
|
||||
wp += 1;
|
||||
cnt -= 1;
|
||||
};
|
||||
}
|
||||
|
||||
return ERR_OK;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Write a word to Flash for AMD FLASH
|
||||
* A word is 16 or 32 bits, whichever the bus width of the flash bank
|
||||
* (not an individual chip) is.
|
||||
*
|
||||
* returns:
|
||||
* 0 - OK
|
||||
* 1 - write timeout
|
||||
* 2 - Flash not erased
|
||||
*/
|
||||
static int write_word_amd (flash_info_t *info, FPWV *dest, FPW data)
|
||||
{
|
||||
ulong start;
|
||||
int flag;
|
||||
FPWV *base; /* first address in flash bank */
|
||||
|
||||
/* Check if Flash is (sufficiently) erased */
|
||||
if ((*dest & data) != data) {
|
||||
return (2);
|
||||
}
|
||||
|
||||
base = (FPWV *)(info->start[0]);
|
||||
|
||||
/* Disable interrupts which might cause a timeout here */
|
||||
flag = disable_interrupts();
|
||||
|
||||
base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */
|
||||
base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */
|
||||
base[FLASH_CYCLE1] = (FPW)0x00A000A0; /* selects program mode */
|
||||
|
||||
*dest = data; /* start programming the data */
|
||||
|
||||
/* re-enable interrupts if necessary */
|
||||
if (flag)
|
||||
enable_interrupts();
|
||||
|
||||
start = get_timer (0);
|
||||
|
||||
/* data polling for D7 */
|
||||
while ((*dest & (FPW)0x00000080) != (data & (FPW)0x00000080)) {
|
||||
if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
|
||||
*dest = (FPW)0x000000F0; /* reset bank */
|
||||
return (1);
|
||||
}
|
||||
}
|
||||
return (0);
|
||||
}
|
||||
|
||||
@ -6,7 +6,7 @@
|
||||
*
|
||||
* Modified for the at91rm9200dk board by
|
||||
* (C) Copyright 2004
|
||||
* Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
|
||||
* Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
@ -35,7 +35,7 @@
|
||||
* some parameters for the board
|
||||
*
|
||||
* This is based on rm9200dk.cfg for the BDI2000 from ABATRON which in
|
||||
* turn is based on the boot.bin code from ATMMEL
|
||||
* turn is based on the boot.bin code from ATMEL
|
||||
*
|
||||
*/
|
||||
|
||||
@ -53,7 +53,7 @@
|
||||
#define EBI_CFGR 0xFFFFFF64
|
||||
#define EBI_CFGR_VAL 0x00000000
|
||||
#define SMC2_CSR 0xFFFFFF70
|
||||
#define SMC2_CSR_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
|
||||
#define SMC2_CSR_VAL 0x100032ad /* 16bit, 2 TDF, 4 WS */
|
||||
|
||||
/* clocks */
|
||||
#define PLLAR 0xFFFFFC28
|
||||
@ -73,7 +73,7 @@
|
||||
#define EBI_CSA 0xFFFFFF60
|
||||
#define EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */
|
||||
#define SDRC_CR 0xFFFFFF98
|
||||
#define SDRC_CR_VAL 0x2188c155
|
||||
#define SDRC_CR_VAL 0x3399c1d4 /* set up the SDRAM */
|
||||
#define SDRAM 0x20000000 /* address of the SDRAM */
|
||||
#define SDRAM1 0x20000080 /* address of the SDRAM */
|
||||
#define SDRAM_VAL 0x00000000 /* value written to SDRAM */
|
||||
@ -86,15 +86,20 @@
|
||||
#define SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
|
||||
|
||||
|
||||
_TEXT_BASE:
|
||||
_MTEXT_BASE:
|
||||
#undef START_FROM_MEM
|
||||
#ifdef START_FROM_MEM
|
||||
.word TEXT_BASE-PHYS_FLASH_1
|
||||
#else
|
||||
.word TEXT_BASE
|
||||
#endif
|
||||
|
||||
.globl memsetup
|
||||
memsetup:
|
||||
.globl lowlevelinit
|
||||
lowlevelinit:
|
||||
/* memory control configuration */
|
||||
/* this isn't very elegant, but what the heck */
|
||||
ldr r0, =SMRDATA
|
||||
ldr r1, _TEXT_BASE
|
||||
ldr r1, _MTEXT_BASE
|
||||
sub r0, r0, r1
|
||||
add r2, r0, #80
|
||||
0:
|
||||
@ -106,12 +111,12 @@ memsetup:
|
||||
cmp r2, r0
|
||||
bne 0b
|
||||
/* delay - this is all done by guess */
|
||||
ldr r0, =0x00001000
|
||||
ldr r0, =0x00010000
|
||||
1:
|
||||
subs r0, r0, #1
|
||||
bhi 1b
|
||||
ldr r0, =SMRDATA1
|
||||
ldr r1, _TEXT_BASE
|
||||
ldr r1, _MTEXT_BASE
|
||||
sub r0, r0, r1
|
||||
add r2, r0, #176
|
||||
2:
|
||||
|
||||
@ -449,8 +449,8 @@ U_BOOT_CMD(
|
||||
bootm, CFG_MAXARGS, 1, do_bootm,
|
||||
"bootm - boot application image from memory\n",
|
||||
"[addr [arg ...]]\n - boot application image stored in memory\n"
|
||||
" passing arguments 'arg ...'; when booting a Linux kernel,\n"
|
||||
" 'arg' can be the address of an initrd image\n"
|
||||
"\tpassing arguments 'arg ...'; when booting a Linux kernel,\n"
|
||||
"\t'arg' can be the address of an initrd image\n"
|
||||
);
|
||||
|
||||
#ifdef CONFIG_SILENT_CONSOLE
|
||||
@ -574,11 +574,11 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag,
|
||||
kbd->bi_intfreq /= 1000000L;
|
||||
kbd->bi_busfreq /= 1000000L;
|
||||
#if defined(CONFIG_MPC8220)
|
||||
kbd->bi_inpfreq /= 1000000L;
|
||||
kbd->bi_pcifreq /= 1000000L;
|
||||
kbd->bi_pevfreq /= 1000000L;
|
||||
kbd->bi_flbfreq /= 1000000L;
|
||||
kbd->bi_vcofreq /= 1000000L;
|
||||
kbd->bi_inpfreq /= 1000000L;
|
||||
kbd->bi_pcifreq /= 1000000L;
|
||||
kbd->bi_pevfreq /= 1000000L;
|
||||
kbd->bi_flbfreq /= 1000000L;
|
||||
kbd->bi_vcofreq /= 1000000L;
|
||||
#endif
|
||||
#if defined(CONFIG_8260) || defined(CONFIG_MPC8560)
|
||||
kbd->bi_cpmfreq /= 1000000L;
|
||||
|
||||
@ -29,6 +29,10 @@
|
||||
#ifdef CONFIG_MPC8260 /* only valid for MPC8260 */
|
||||
#include <ioports.h>
|
||||
#endif
|
||||
#ifdef CONFIG_AT91RM9200DK /* need this for the at91rm9200dk */
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/hardware.h>
|
||||
#endif
|
||||
#include <i2c.h>
|
||||
|
||||
#if defined(CONFIG_SOFT_I2C)
|
||||
|
||||
@ -169,6 +169,7 @@ int eth_init (bd_t * bd)
|
||||
AT91C_PA10_ETX1 | AT91C_PA9_ETX0 | AT91C_PA8_ETXEN |
|
||||
AT91C_PA7_ETXCK_EREFCK;
|
||||
|
||||
#if defined(CONFIG_AT91C_USE_RMII) && !defined(CONFIG_CMC_PU2)
|
||||
*AT91C_PIOB_PDR = AT91C_PB25_EF100 |
|
||||
AT91C_PB19_ERXCK | AT91C_PB18_ECOL | AT91C_PB17_ERXDV |
|
||||
AT91C_PB16_ERX3 | AT91C_PB15_ERX2 | AT91C_PB14_ETXER |
|
||||
@ -178,6 +179,7 @@ int eth_init (bd_t * bd)
|
||||
*AT91C_PIOB_BSR = AT91C_PB25_EF100 | AT91C_PB19_ERXCK | AT91C_PB18_ECOL |
|
||||
AT91C_PB17_ERXDV | AT91C_PB16_ERX3 | AT91C_PB15_ERX2 |
|
||||
AT91C_PB14_ETXER | AT91C_PB13_ETX3 | AT91C_PB12_ETX2;
|
||||
#endif
|
||||
|
||||
*AT91C_PMC_PCER = 1 << AT91C_ID_EMAC; /* Peripheral Clock Enable Register */
|
||||
|
||||
|
||||
@ -42,7 +42,7 @@ static int debug = 0;
|
||||
static short at91_poll_status(AT91PS_TWI twi, unsigned long bit) {
|
||||
int loop_cntr = 10000;
|
||||
do {
|
||||
udelay(100);
|
||||
udelay(10);
|
||||
} while (!(twi->TWI_SR & bit) && (--loop_cntr > 0));
|
||||
|
||||
return (loop_cntr > 0);
|
||||
|
||||
@ -55,17 +55,11 @@ void serial_setbrg (void)
|
||||
|
||||
if ((baudrate = gd->baudrate) <= 0)
|
||||
baudrate = CONFIG_BAUDRATE;
|
||||
if (baudrate == CONFIG_BAUDRATE) {
|
||||
if (baudrate == 0 || baudrate == CONFIG_BAUDRATE)
|
||||
us->US_BRGR = CFG_AT91C_BRGR_DIVISOR; /* hardcode so no __divsi3 */
|
||||
} else {
|
||||
#if 0
|
||||
/* 33 -> 115200 */
|
||||
us->US_BRGR = 33 * (115200/baudrate);
|
||||
#else
|
||||
else
|
||||
/* MASTER_CLOCK/(16 * baudrate) */
|
||||
us->US_BRGR = (AT91C_MASTER_CLOCK >> 4)/baudrate;
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
int serial_init (void)
|
||||
|
||||
@ -112,9 +112,53 @@ reset:
|
||||
*/
|
||||
mrs r0,cpsr
|
||||
bic r0,r0,#0x1f
|
||||
orr r0,r0,#0x13
|
||||
orr r0,r0,#0xd3 /* was 13 */
|
||||
msr cpsr,r0
|
||||
|
||||
#ifdef CONFIG_BOOTBINFUNC
|
||||
/* code based on entry.S from ATMEL */
|
||||
#define AT91C_BASE_CKGR 0xFFFFFC20
|
||||
#define CKGR_MOR 0
|
||||
/* Get the CKGR Base Address */
|
||||
ldr r1, =AT91C_BASE_CKGR
|
||||
|
||||
/* Main oscillator Enable register APMC_MOR : Enable main oscillator , OSCOUNT = 0xFF */
|
||||
/* ldr r0, = AT91C_CKGR_MOSCEN:OR:AT91C_CKGR_OSCOUNT */
|
||||
ldr r0, =0x0000FF01
|
||||
str r0, [r1, #CKGR_MOR]
|
||||
/* Add loop to compensate Main Oscillator startup time */
|
||||
ldr r0, =0x00000010
|
||||
LoopOsc:
|
||||
subs r0, r0, #1
|
||||
bhi LoopOsc
|
||||
|
||||
/* scratch stack */
|
||||
ldr r1, =0x00204000
|
||||
/* Insure word alignment */
|
||||
bic r1, r1, #3
|
||||
/* Init stack SYS */
|
||||
mov sp, r1
|
||||
/*
|
||||
* This does a lot more than just set up the memory, which
|
||||
* is why it's called lowlevelinit
|
||||
*/
|
||||
bl lowlevelinit /* in memsetup.S */
|
||||
bl icache_enable;
|
||||
/*------------------------------------
|
||||
Read/modify/write CP15 control register
|
||||
-------------------------------------
|
||||
read cp15 control register (cp15 r1) in r0
|
||||
------------------------------------*/
|
||||
mrc p15, 0, r0, c1, c0, 0
|
||||
/* Reset bit :Little Endian end fast bus mode */
|
||||
ldr r3, =0xC0000080
|
||||
/* Set bit :Asynchronous clock mode, Not Fast Bus */
|
||||
ldr r4, =0xC0000000
|
||||
bic r0, r0, r3
|
||||
orr r0, r0, r4
|
||||
/* write r0 in cp15 control register (cp15 r1) */
|
||||
mcr p15, 0, r0, c1, c0, 0
|
||||
#endif /* CONFIG_BOOTBINFUNC */
|
||||
/*
|
||||
* relocate exeception table
|
||||
*/
|
||||
@ -135,6 +179,25 @@ copyex:
|
||||
bl cpu_init_crit
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_BOOTBINFUNC
|
||||
relocate: /* relocate U-Boot to RAM */
|
||||
adr r0, _start /* r0 <- current position of code */
|
||||
ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
|
||||
cmp r0, r1 /* don't reloc during debug */
|
||||
beq stack_setup
|
||||
|
||||
ldr r2, _armboot_start
|
||||
ldr r3, _bss_start
|
||||
sub r2, r3, r2 /* r2 <- size of armboot */
|
||||
add r2, r0, r2 /* r2 <- source end address */
|
||||
|
||||
copy_loop:
|
||||
ldmia r0!, {r3-r10} /* copy from source address [r0] */
|
||||
stmia r1!, {r3-r10} /* copy to target address [r1] */
|
||||
cmp r0, r2 /* until source end addreee [r2] */
|
||||
ble copy_loop
|
||||
#endif /* CONFIG_BOOTBINFUNC */
|
||||
|
||||
/* Set up the stack */
|
||||
stack_setup:
|
||||
ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
|
||||
@ -168,7 +231,7 @@ _start_armboot: .word start_armboot
|
||||
*/
|
||||
|
||||
cpu_init_crit:
|
||||
# actually do nothing for now!
|
||||
/* do nothing for now */
|
||||
mov pc, lr
|
||||
|
||||
|
||||
|
||||
@ -92,9 +92,52 @@ typedef struct _AT91S_USART {
|
||||
AT91_REG US_PTSR; /* PDC Transfer Status Register */
|
||||
} AT91S_USART, *AT91PS_USART;
|
||||
|
||||
/* ***************************************************************************** */
|
||||
/************************************************************************/
|
||||
/* SOFTWARE API DEFINITION FOR Clock Generator Controler */
|
||||
/************************************************************************/
|
||||
typedef struct _AT91S_CKGR {
|
||||
AT91_REG CKGR_MOR; /* Main Oscillator Register */
|
||||
AT91_REG CKGR_MCFR; /* Main Clock Frequency Register */
|
||||
AT91_REG CKGR_PLLAR; /* PLL A Register */
|
||||
AT91_REG CKGR_PLLBR; /* PLL B Register */
|
||||
} AT91S_CKGR, *AT91PS_CKGR;
|
||||
|
||||
/* -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- */
|
||||
#define AT91C_CKGR_MOSCEN ((unsigned int) 0x1 << 0) /* (CKGR) Main Oscillator Enable */
|
||||
#define AT91C_CKGR_OSCTEST ((unsigned int) 0x1 << 1) /* (CKGR) Oscillator Test */
|
||||
#define AT91C_CKGR_OSCOUNT ((unsigned int) 0xFF << 8) /* (CKGR) Main Oscillator Start-up Time */
|
||||
/* -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- */
|
||||
#define AT91C_CKGR_MAINF ((unsigned int) 0xFFFF << 0) /* (CKGR) Main Clock Frequency */
|
||||
#define AT91C_CKGR_MAINRDY ((unsigned int) 0x1 << 16) /* (CKGR) Main Clock Ready */
|
||||
/* -------- CKGR_PLLAR : (CKGR Offset: 0x8) PLL A Register -------- */
|
||||
#define AT91C_CKGR_DIVA ((unsigned int) 0xFF << 0) /* (CKGR) Divider Selected */
|
||||
#define AT91C_CKGR_DIVA_0 ((unsigned int) 0x0) /* (CKGR) Divider output is 0 */
|
||||
#define AT91C_CKGR_DIVA_BYPASS ((unsigned int) 0x1) /* (CKGR) Divider is bypassed */
|
||||
#define AT91C_CKGR_PLLACOUNT ((unsigned int) 0x3F << 8) /* (CKGR) PLL A Counter */
|
||||
#define AT91C_CKGR_OUTA ((unsigned int) 0x3 << 14) /* (CKGR) PLL A Output Frequency Range */
|
||||
#define AT91C_CKGR_OUTA_0 ((unsigned int) 0x0 << 14) /* (CKGR) Please refer to the PLLA datasheet */
|
||||
#define AT91C_CKGR_OUTA_1 ((unsigned int) 0x1 << 14) /* (CKGR) Please refer to the PLLA datasheet */
|
||||
#define AT91C_CKGR_OUTA_2 ((unsigned int) 0x2 << 14) /* (CKGR) Please refer to the PLLA datasheet */
|
||||
#define AT91C_CKGR_OUTA_3 ((unsigned int) 0x3 << 14) /* (CKGR) Please refer to the PLLA datasheet */
|
||||
#define AT91C_CKGR_MULA ((unsigned int) 0x7FF << 16) /* (CKGR) PLL A Multiplier */
|
||||
#define AT91C_CKGR_SRCA ((unsigned int) 0x1 << 29) /* (CKGR) PLL A Source */
|
||||
/* -------- CKGR_PLLBR : (CKGR Offset: 0xc) PLL B Register -------- */
|
||||
#define AT91C_CKGR_DIVB ((unsigned int) 0xFF << 0) /* (CKGR) Divider Selected */
|
||||
#define AT91C_CKGR_DIVB_0 ((unsigned int) 0x0) /* (CKGR) Divider output is 0 */
|
||||
#define AT91C_CKGR_DIVB_BYPASS ((unsigned int) 0x1) /* (CKGR) Divider is bypassed */
|
||||
#define AT91C_CKGR_PLLBCOUNT ((unsigned int) 0x3F << 8) /* (CKGR) PLL B Counter */
|
||||
#define AT91C_CKGR_OUTB ((unsigned int) 0x3 << 14) /* (CKGR) PLL B Output Frequency Range */
|
||||
#define AT91C_CKGR_OUTB_0 ((unsigned int) 0x0 << 14) /* (CKGR) Please refer to the PLLB datasheet */
|
||||
#define AT91C_CKGR_OUTB_1 ((unsigned int) 0x1 << 14) /* (CKGR) Please refer to the PLLB datasheet */
|
||||
#define AT91C_CKGR_OUTB_2 ((unsigned int) 0x2 << 14) /* (CKGR) Please refer to the PLLB datasheet */
|
||||
#define AT91C_CKGR_OUTB_3 ((unsigned int) 0x3 << 14) /* (CKGR) Please refer to the PLLB datasheet */
|
||||
#define AT91C_CKGR_MULB ((unsigned int) 0x7FF << 16) /* (CKGR) PLL B Multiplier */
|
||||
#define AT91C_CKGR_USB_96M ((unsigned int) 0x1 << 28) /* (CKGR) Divider for USB Ports */
|
||||
#define AT91C_CKGR_USB_PLL ((unsigned int) 0x1 << 29) /* (CKGR) PLL Use */
|
||||
|
||||
/* ************************************************************************* */
|
||||
/* SOFTWARE API DEFINITION FOR Parallel Input Output Controler */
|
||||
/* ***************************************************************************** */
|
||||
/* ************************************************************************* */
|
||||
typedef struct _AT91S_PIO {
|
||||
AT91_REG PIO_PER; /* PIO Enable Register */
|
||||
AT91_REG PIO_PDR; /* PIO Disable Register */
|
||||
@ -198,6 +241,23 @@ typedef struct _AT91S_SMC2 {
|
||||
AT91_REG SMC2_CSR[8]; /* SMC2 Chip Select Register */
|
||||
} AT91S_SMC2, *AT91PS_SMC2;
|
||||
|
||||
/* -------- SMC2_CSR : (SMC2 Offset: 0x0) SMC2 Chip Select Register -------- */
|
||||
#define AT91C_SMC2_NWS ((unsigned int) 0x7F << 0) /* (SMC2) Number of Wait States */
|
||||
#define AT91C_SMC2_WSEN ((unsigned int) 0x1 << 7) /* (SMC2) Wait State Enable */
|
||||
#define AT91C_SMC2_TDF ((unsigned int) 0xF << 8) /* (SMC2) Data Float Time */
|
||||
#define AT91C_SMC2_BAT ((unsigned int) 0x1 << 12) /* (SMC2) Byte Access Type */
|
||||
#define AT91C_SMC2_DBW ((unsigned int) 0x1 << 13) /* (SMC2) Data Bus Width */
|
||||
#define AT91C_SMC2_DBW_16 ((unsigned int) 0x1 << 13) /* (SMC2) 16-bit. */
|
||||
#define AT91C_SMC2_DBW_8 ((unsigned int) 0x2 << 13) /* (SMC2) 8-bit. */
|
||||
#define AT91C_SMC2_DRP ((unsigned int) 0x1 << 15) /* (SMC2) Data Read Protocol */
|
||||
#define AT91C_SMC2_ACSS ((unsigned int) 0x3 << 16) /* (SMC2) Address to Chip Select Setup */
|
||||
#define AT91C_SMC2_ACSS_STANDARD ((unsigned int) 0x0 << 16) /* (SMC2) Standard, asserted at the beginning of the access and deasserted at the end. */
|
||||
#define AT91C_SMC2_ACSS_1_CYCLE ((unsigned int) 0x1 << 16) /* (SMC2) One cycle less at the beginning and the end of the access. */
|
||||
#define AT91C_SMC2_ACSS_2_CYCLES ((unsigned int) 0x2 << 16) /* (SMC2) Two cycles less at the beginning and the end of the access. */
|
||||
#define AT91C_SMC2_ACSS_3_CYCLES ((unsigned int) 0x3 << 16) /* (SMC2) Three cycles less at the beginning and the end of the access. */
|
||||
#define AT91C_SMC2_RWSETUP ((unsigned int) 0x7 << 24) /* (SMC2) Read and Write Signal Setup Time */
|
||||
#define AT91C_SMC2_RWHOLD ((unsigned int) 0x7 << 29) /* (SMC2) Read and Write Signal Hold Time */
|
||||
|
||||
/* ***************************************************************************** */
|
||||
/* SOFTWARE API DEFINITION FOR Power Management Controler */
|
||||
/* ******************************************************************************/
|
||||
@ -220,6 +280,58 @@ typedef struct _AT91S_PMC {
|
||||
} AT91S_PMC, *AT91PS_PMC;
|
||||
|
||||
|
||||
/*------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register --------*/
|
||||
#define AT91C_PMC_PCK ((unsigned int) 0x1 << 0) /* (PMC) Processor Clock */
|
||||
#define AT91C_PMC_UDP ((unsigned int) 0x1 << 1) /* (PMC) USB Device Port Clock */
|
||||
#define AT91C_PMC_MCKUDP ((unsigned int) 0x1 << 2) /* (PMC) USB Device Port Master Clock Automatic Disable on Suspend */
|
||||
#define AT91C_PMC_UHP ((unsigned int) 0x1 << 4) /* (PMC) USB Host Port Clock */
|
||||
#define AT91C_PMC_PCK0 ((unsigned int) 0x1 << 8) /* (PMC) Programmable Clock Output */
|
||||
#define AT91C_PMC_PCK1 ((unsigned int) 0x1 << 9) /* (PMC) Programmable Clock Output */
|
||||
#define AT91C_PMC_PCK2 ((unsigned int) 0x1 << 10) /* (PMC) Programmable Clock Output */
|
||||
#define AT91C_PMC_PCK3 ((unsigned int) 0x1 << 11) /* (PMC) Programmable Clock Output */
|
||||
#define AT91C_PMC_PCK4 ((unsigned int) 0x1 << 12) /* (PMC) Programmable Clock Output */
|
||||
#define AT91C_PMC_PCK5 ((unsigned int) 0x1 << 13) /* (PMC) Programmable Clock Output */
|
||||
#define AT91C_PMC_PCK6 ((unsigned int) 0x1 << 14) /* (PMC) Programmable Clock Output */
|
||||
#define AT91C_PMC_PCK7 ((unsigned int) 0x1 << 15) /* (PMC) Programmable Clock Output */
|
||||
/*-------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register ------*/
|
||||
/*-------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------*/
|
||||
/*-------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register --------*/
|
||||
#define AT91C_PMC_CSS ((unsigned int) 0x3 << 0) /* (PMC) Programmable Clock Selection */
|
||||
#define AT91C_PMC_CSS_SLOW_CLK ((unsigned int) 0x0) /* (PMC) Slow Clock is selected */
|
||||
#define AT91C_PMC_CSS_MAIN_CLK ((unsigned int) 0x1) /* (PMC) Main Clock is selected */
|
||||
#define AT91C_PMC_CSS_PLLA_CLK ((unsigned int) 0x2) /* (PMC) Clock from PLL A is selected */
|
||||
#define AT91C_PMC_CSS_PLLB_CLK ((unsigned int) 0x3) /* (PMC) Clock from PLL B is selected */
|
||||
#define AT91C_PMC_PRES ((unsigned int) 0x7 << 2) /* (PMC) Programmable Clock Prescaler */
|
||||
#define AT91C_PMC_PRES_CLK ((unsigned int) 0x0 << 2) /* (PMC) Selected clock */
|
||||
#define AT91C_PMC_PRES_CLK_2 ((unsigned int) 0x1 << 2) /* (PMC) Selected clock divided by 2 */
|
||||
#define AT91C_PMC_PRES_CLK_4 ((unsigned int) 0x2 << 2) /* (PMC) Selected clock divided by 4 */
|
||||
#define AT91C_PMC_PRES_CLK_8 ((unsigned int) 0x3 << 2) /* (PMC) Selected clock divided by 8 */
|
||||
#define AT91C_PMC_PRES_CLK_16 ((unsigned int) 0x4 << 2) /* (PMC) Selected clock divided by 16 */
|
||||
#define AT91C_PMC_PRES_CLK_32 ((unsigned int) 0x5 << 2) /* (PMC) Selected clock divided by 32 */
|
||||
#define AT91C_PMC_PRES_CLK_64 ((unsigned int) 0x6 << 2) /* (PMC) Selected clock divided by 64 */
|
||||
#define AT91C_PMC_MDIV ((unsigned int) 0x3 << 8) /* (PMC) Master Clock Division */
|
||||
#define AT91C_PMC_MDIV_1 ((unsigned int) 0x0 << 8) /* (PMC) The master clock and the processor clock are the same */
|
||||
#define AT91C_PMC_MDIV_2 ((unsigned int) 0x1 << 8) /* (PMC) The processor clock is twice as fast as the master clock */
|
||||
#define AT91C_PMC_MDIV_3 ((unsigned int) 0x2 << 8) /* (PMC) The processor clock is three times faster than the master clock */
|
||||
#define AT91C_PMC_MDIV_4 ((unsigned int) 0x3 << 8) /* (PMC) The processor clock is four times faster than the master clock */
|
||||
/*------ PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register --------*/
|
||||
/*------ PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------*/
|
||||
#define AT91C_PMC_MOSCS ((unsigned int) 0x1 << 0) /* (PMC) MOSC Status/Enable/Disable/Mask */
|
||||
#define AT91C_PMC_LOCKA ((unsigned int) 0x1 << 1) /* (PMC) PLL A Status/Enable/Disable/Mask */
|
||||
#define AT91C_PMC_LOCKB ((unsigned int) 0x1 << 2) /* (PMC) PLL B Status/Enable/Disable/Mask */
|
||||
#define AT91C_PMC_MCKRDY ((unsigned int) 0x1 << 3) /* (PMC) MCK_RDY Status/Enable/Disable/Mask */
|
||||
#define AT91C_PMC_PCK0RDY ((unsigned int) 0x1 << 8) /* (PMC) PCK0_RDY Status/Enable/Disable/Mask */
|
||||
#define AT91C_PMC_PCK1RDY ((unsigned int) 0x1 << 9) /* (PMC) PCK1_RDY Status/Enable/Disable/Mask */
|
||||
#define AT91C_PMC_PCK2RDY ((unsigned int) 0x1 << 10) /* (PMC) PCK2_RDY Status/Enable/Disable/Mask */
|
||||
#define AT91C_PMC_PCK3RDY ((unsigned int) 0x1 << 11) /* (PMC) PCK3_RDY Status/Enable/Disable/Mask */
|
||||
#define AT91C_PMC_PCK4RDY ((unsigned int) 0x1 << 12) /* (PMC) PCK4_RDY Status/Enable/Disable/Mask */
|
||||
#define AT91C_PMC_PCK5RDY ((unsigned int) 0x1 << 13) /* (PMC) PCK5_RDY Status/Enable/Disable/Mask */
|
||||
#define AT91C_PMC_PCK6RDY ((unsigned int) 0x1 << 14) /* (PMC) PCK6_RDY Status/Enable/Disable/Mask */
|
||||
#define AT91C_PMC_PCK7RDY ((unsigned int) 0x1 << 15) /* (PMC) PCK7_RDY Status/Enable/Disable/Mask */
|
||||
/*---- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register --------*/
|
||||
/*-------- PMC_SR : (PMC Offset: 0x68) PMC Status Register --------*/
|
||||
/*-------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register --------*/
|
||||
|
||||
/* ***************************************************************************** */
|
||||
/* SOFTWARE API DEFINITION FOR Ethernet MAC */
|
||||
/* ***************************************************************************** */
|
||||
|
||||
@ -347,8 +347,6 @@
|
||||
#define CFG_OR5_PRELIM (((-CFG_SRAM_SIZE) & OR_AM_MSK) | CFG_OR_TIMING_SRAM)
|
||||
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* 4096 Rows from SDRAM example configuration
|
||||
* 1000 factor s -> ms
|
||||
|
||||
@ -44,6 +44,9 @@
|
||||
#define CONFIG_SETUP_MEMORY_TAGS 1
|
||||
#define CONFIG_INITRD_TAG 1
|
||||
|
||||
/* define this to include the functionality of boot.bin in u-boot */
|
||||
#undef CONFIG_BOOTBINFUNC
|
||||
|
||||
/*
|
||||
* Size of malloc() pool
|
||||
*/
|
||||
@ -58,8 +61,9 @@
|
||||
* Hardware drivers
|
||||
*/
|
||||
|
||||
/* define one of these to choose the DBGU or USART1 as console */
|
||||
/* define one of these to choose the DBGU, USART0 or USART1 as console */
|
||||
#define CONFIG_DBGU
|
||||
#undef CONFIG_USART0
|
||||
#undef CONFIG_USART1
|
||||
|
||||
#undef CONFIG_HWFLOW /* don't include RTS/CTS flow control support */
|
||||
@ -145,16 +149,27 @@
|
||||
#define CFG_ENV_SIZE 0x2000 /* 0x8000 */
|
||||
#else
|
||||
#define CFG_ENV_IS_IN_FLASH 1
|
||||
#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0xe000) /* 0x10000 */
|
||||
#ifdef CONFIG_BOOTBINFUNC
|
||||
#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x60000) /* after u-boot.bin */
|
||||
#define CFG_ENV_SIZE 0x10000 /* sectors are 64K here */
|
||||
#else
|
||||
#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0xe000) /* between boot.bin and u-boot.bin.gz */
|
||||
#define CFG_ENV_SIZE 0x2000 /* 0x8000 */
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
||||
#define CFG_LOAD_ADDR 0x21000000 /* default load address */
|
||||
|
||||
#ifdef CONFIG_BOOTBINFUNC
|
||||
#define CFG_BOOT_SIZE 0x00 /* 0 KBytes */
|
||||
#define CFG_U_BOOT_BASE PHYS_FLASH_1
|
||||
#define CFG_U_BOOT_SIZE 0x60000 /* 384 KBytes */
|
||||
#else
|
||||
#define CFG_BOOT_SIZE 0x6000 /* 24 KBytes */
|
||||
#define CFG_U_BOOT_BASE (PHYS_FLASH_1 + 0x10000)
|
||||
#define CFG_U_BOOT_SIZE 0x10000 /* 64 KBytes */
|
||||
#endif
|
||||
|
||||
#define CFG_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 }
|
||||
|
||||
|
||||
@ -1,7 +1,7 @@
|
||||
/*
|
||||
* Rick Bronson <rick@efn.org>
|
||||
* Gary Jennejohn <garyj@denx.de>
|
||||
*
|
||||
* Configuation settings for the AT91RM9200DK board.
|
||||
* Configuration settings for the CMC PU2 board.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
@ -34,7 +34,6 @@
|
||||
/* ARM asynchronous clock */
|
||||
#define AT91C_MAIN_CLOCK 179712000 /* from 18.432 MHz crystal (18432000 / 4 * 39) */
|
||||
#define AT91C_MASTER_CLOCK 59904000 /* peripheral clock (AT91C_MASTER_CLOCK / 3) */
|
||||
/* #define AT91C_MASTER_CLOCK 44928000 */ /* peripheral clock (AT91C_MASTER_CLOCK / 4) */
|
||||
|
||||
#define AT91_SLOW_CLOCK 32768 /* slow clock */
|
||||
|
||||
@ -46,7 +45,12 @@
|
||||
#define CONFIG_INITRD_TAG 1
|
||||
|
||||
/* define this to include the functionality of boot.bin in u-boot */
|
||||
#undef CONFIG_BOOTBINFUNC
|
||||
#define CONFIG_BOOTBINFUNC
|
||||
|
||||
/* just to make sure */
|
||||
#ifndef CONFIG_BOOTBINFUNC
|
||||
#define CONFIG_BOOTBINFUNC
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Size of malloc() pool
|
||||
@ -64,14 +68,14 @@
|
||||
|
||||
/* define one of these to choose the DBGU, USART0 or USART1 as console */
|
||||
#undef CONFIG_DBGU
|
||||
#undef CONFIG_USART0
|
||||
#define CONFIG_USART1
|
||||
#define CONFIG_USART0
|
||||
#undef CONFIG_USART1
|
||||
|
||||
#undef CONFIG_HWFLOW /* don't include RTS/CTS flow control support */
|
||||
|
||||
#undef CONFIG_MODEM_SUPPORT /* disable modem initialization stuff */
|
||||
|
||||
#undef CONFIG_HARD_I2C
|
||||
#define CONFIG_HARD_I2C
|
||||
|
||||
#ifdef CONFIG_HARD_I2C
|
||||
#define CFG_I2C_SPEED 0 /* not used */
|
||||
@ -114,38 +118,12 @@
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
|
||||
#include <cmd_confdefs.h>
|
||||
|
||||
#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
|
||||
#define SECTORSIZE 512
|
||||
|
||||
#define ADDR_COLUMN 1
|
||||
#define ADDR_PAGE 2
|
||||
#define ADDR_COLUMN_PAGE 3
|
||||
|
||||
#define NAND_ChipID_UNKNOWN 0x00
|
||||
#define NAND_MAX_FLOORS 1
|
||||
#define NAND_MAX_CHIPS 1
|
||||
|
||||
#define AT91_SMART_MEDIA_ALE (1 << 22) /* our ALE is AD22 */
|
||||
#define AT91_SMART_MEDIA_CLE (1 << 21) /* our CLE is AD21 */
|
||||
|
||||
#define NAND_DISABLE_CE(nand) do { *AT91C_PIOC_SODR = AT91C_PIO_PC0;} while(0)
|
||||
#define NAND_ENABLE_CE(nand) do { *AT91C_PIOC_CODR = AT91C_PIO_PC0;} while(0)
|
||||
|
||||
#define NAND_WAIT_READY(nand) while (!(*AT91C_PIOC_PDSR & AT91C_PIO_PC2))
|
||||
|
||||
#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | AT91_SMART_MEDIA_CLE) = (__u8)(d); } while(0)
|
||||
#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | AT91_SMART_MEDIA_ALE) = (__u8)(d); } while(0)
|
||||
#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
|
||||
#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
|
||||
/* the following are NOP's in our implementation */
|
||||
#define NAND_CTL_CLRALE(nandptr)
|
||||
#define NAND_CTL_SETALE(nandptr)
|
||||
#define NAND_CTL_CLRCLE(nandptr)
|
||||
#define NAND_CTL_SETCLE(nandptr)
|
||||
|
||||
#define CONFIG_NR_DRAM_BANKS 1
|
||||
#define PHYS_SDRAM 0x20000000
|
||||
#define PHYS_SDRAM_SIZE 0x2000000 /* 32 megs */
|
||||
#define PHYS_SDRAM_SIZE 0x1000000 /* 16 megs */
|
||||
|
||||
#define CFG_MEMTEST_START PHYS_SDRAM
|
||||
#define CFG_MEMTEST_END CFG_MEMTEST_START + PHYS_SDRAM_SIZE - 262144
|
||||
@ -162,35 +140,26 @@
|
||||
#define CFG_DATAFLASH_LOGIC_ADDR_CS3 0xD0000000 /* Logical adress for CS3 */
|
||||
|
||||
#define PHYS_FLASH_1 0x10000000
|
||||
#define PHYS_FLASH_SIZE 0x200000 /* 2 megs main flash */
|
||||
#define PHYS_FLASH_SIZE 0x800000 /* 8 megs main flash */
|
||||
#define CFG_FLASH_BASE PHYS_FLASH_1
|
||||
#define CFG_MAX_FLASH_BANKS 1
|
||||
#define CFG_MAX_FLASH_SECT 256
|
||||
#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */
|
||||
#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */
|
||||
|
||||
#undef CFG_ENV_IS_IN_DATAFLASH
|
||||
|
||||
#ifdef CFG_ENV_IS_IN_DATAFLASH
|
||||
#define CFG_ENV_OFFSET 0x20000
|
||||
#define CFG_ENV_ADDR (CFG_DATAFLASH_LOGIC_ADDR_CS0 + CFG_ENV_OFFSET)
|
||||
#define CFG_ENV_SIZE 0x2000 /* 0x8000 */
|
||||
#else
|
||||
#define CFG_ENV_IS_IN_FLASH 1
|
||||
#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0xe000) /* 0x10000 */
|
||||
#define CFG_ENV_SIZE 0x2000 /* 0x8000 */
|
||||
#endif
|
||||
|
||||
#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x20000) /* after u-boot.bin */
|
||||
#define CFG_ENV_SIZE 0x10000 /* sectors are 64K here */
|
||||
|
||||
#define CFG_LOAD_ADDR 0x21000000 /* default load address */
|
||||
|
||||
#define CFG_BOOT_SIZE 0x6000 /* 24 KBytes */
|
||||
#define CFG_U_BOOT_BASE (PHYS_FLASH_1 + 0x10000)
|
||||
#define CFG_U_BOOT_SIZE 0x10000 /* 64 KBytes */
|
||||
#define CFG_BOOT_SIZE 0x00 /* 0 KBytes */
|
||||
#define CFG_U_BOOT_BASE PHYS_FLASH_1
|
||||
#define CFG_U_BOOT_SIZE 0x20000 /* 128 KBytes */
|
||||
|
||||
#define CFG_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 }
|
||||
|
||||
#define CFG_PROMPT "U-Boot> " /* Monitor Command Prompt */
|
||||
#define CFG_PROMPT "cmc> " /* Monitor Command Prompt */
|
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#define CFG_MAXARGS 16 /* max number of command args */
|
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
|
||||
|
||||
@ -194,6 +194,8 @@ extern void flash_read_factory_serial(flash_info_t * info, void * buffer, int of
|
||||
#define AMD_ID_LV128U_3 0x22002200 /* 3rd ID word for AM29LV128M at 0x3c */
|
||||
#define AMD_ID_LV256U_2 0x22122212 /* 2nd ID word for AM29LV256M at 0x38 */
|
||||
#define AMD_ID_LV256U_3 0x22012201 /* 3rd ID word for AM29LV256M at 0x3c */
|
||||
#define AMD_ID_GL064M_2 0x22132213 /* 2nd ID word for S29GL064M-R6 */
|
||||
#define AMD_ID_GL064M_3 0x22012201 /* 3rd ID word for S29GL064M-R6 */
|
||||
|
||||
#define AMD_ID_LV320B_2 0x221A221A /* 2d ID word for AM29LV320MB at 0x38 */
|
||||
#define AMD_ID_LV320B_3 0x22002200 /* 3d ID word for AM29LV320MB at 0x3c */
|
||||
@ -374,6 +376,7 @@ extern void flash_read_factory_serial(flash_info_t * info, void * buffer, int of
|
||||
|
||||
#define FLASH_FUJLV650 0x00D0 /* Fujitsu MBM 29LV650UE/651UE */
|
||||
#define FLASH_MT28S4M16LC 0x00E1 /* Micron MT28S4M16LC */
|
||||
#define FLASH_S29GL064M 0x00F0 /* Spansion S29GL064M-R6 */
|
||||
|
||||
#define FLASH_UNKNOWN 0xFFFF /* unknown flash type */
|
||||
|
||||
|
||||
@ -505,14 +505,14 @@ void board_init_f (ulong bootflag)
|
||||
|
||||
/* store bootparam to sram (backward compatible), here? */
|
||||
{
|
||||
u32 *sram = (u32 *)CFG_SRAM_BASE;
|
||||
*sram++ = gd->ram_size;
|
||||
*sram++ = gd->bus_clk;
|
||||
*sram++ = gd->inp_clk;
|
||||
*sram++ = gd->cpu_clk;
|
||||
*sram++ = gd->vco_clk;
|
||||
*sram++ = gd->flb_clk;
|
||||
*sram++ = 0xb8c3ba11; /* boot signature */
|
||||
u32 *sram = (u32 *)CFG_SRAM_BASE;
|
||||
*sram++ = gd->ram_size;
|
||||
*sram++ = gd->bus_clk;
|
||||
*sram++ = gd->inp_clk;
|
||||
*sram++ = gd->cpu_clk;
|
||||
*sram++ = gd->vco_clk;
|
||||
*sram++ = gd->flb_clk;
|
||||
*sram++ = 0xb8c3ba11; /* boot signature */
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
@ -590,7 +590,7 @@ usage ()
|
||||
{
|
||||
fprintf (stderr, "Usage: %s -l image\n"
|
||||
" -l ==> list image header information\n"
|
||||
" %s -A arch -O os -T type -C comp "
|
||||
" %s [-x] -A arch -O os -T type -C comp "
|
||||
"-a addr -e ep -n name -d data_file[:data_file...] image\n",
|
||||
cmdname, cmdname);
|
||||
fprintf (stderr, " -A ==> set architecture to 'arch'\n"
|
||||
|
||||
Loading…
Reference in New Issue
Block a user