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Merge git://git.denx.de/u-boot-fsl-qoriq

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This commit is contained in:
Tom Rini 2016-07-26 17:34:28 -04:00
commit 9c7a0a600b
38 changed files with 889 additions and 106 deletions
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138
arch/arm/cpu/armv7/ls102xa/psci.S
View File

@ -12,19 +12,102 @@
#include <asm/arch-armv7/generictimer.h>
#include <asm/psci.h>
#define RCPM_TWAITSR 0x04C
#define SCFG_CORE0_SFT_RST 0x130
#define SCFG_CORESRENCR 0x204
#define DCFG_CCSR_BRR 0x0E4
#define DCFG_CCSR_SCRATCHRW1 0x200
#define DCFG_CCSR_RSTCR 0x0B0
#define DCFG_CCSR_RSTCR_RESET_REQ 0x2
#define DCFG_CCSR_BRR 0x0E4
#define DCFG_CCSR_SCRATCHRW1 0x200
#define PSCI_FN_PSCI_VERSION_FEATURE_MASK 0x0
#define PSCI_FN_CPU_SUSPEND_FEATURE_MASK 0x0
#define PSCI_FN_CPU_OFF_FEATURE_MASK 0x0
#define PSCI_FN_CPU_ON_FEATURE_MASK 0x0
#define PSCI_FN_AFFINITY_INFO_FEATURE_MASK 0x0
#define PSCI_FN_SYSTEM_OFF_FEATURE_MASK 0x0
#define PSCI_FN_SYSTEM_RESET_FEATURE_MASK 0x0
.pushsection ._secure.text, "ax"
.arch_extension sec
.align 5
#define ONE_MS (GENERIC_TIMER_CLK / 1000)
#define RESET_WAIT (30 * ONE_MS)
.globl psci_version
psci_version:
movw r0, #0
movt r0, #1
bx lr
_ls102x_psci_supported_table:
.word ARM_PSCI_0_2_FN_PSCI_VERSION
.word PSCI_FN_PSCI_VERSION_FEATURE_MASK
.word ARM_PSCI_0_2_FN_CPU_SUSPEND
.word PSCI_FN_CPU_SUSPEND_FEATURE_MASK
.word ARM_PSCI_0_2_FN_CPU_OFF
.word PSCI_FN_CPU_OFF_FEATURE_MASK
.word ARM_PSCI_0_2_FN_CPU_ON
.word PSCI_FN_CPU_ON_FEATURE_MASK
.word ARM_PSCI_0_2_FN_AFFINITY_INFO
.word PSCI_FN_AFFINITY_INFO_FEATURE_MASK
.word ARM_PSCI_0_2_FN_SYSTEM_OFF
.word PSCI_FN_SYSTEM_OFF_FEATURE_MASK
.word ARM_PSCI_0_2_FN_SYSTEM_RESET
.word PSCI_FN_SYSTEM_RESET_FEATURE_MASK
.word 0
.word ARM_PSCI_RET_NI
.globl psci_features
psci_features:
adr r2, _ls102x_psci_supported_table
1: ldr r3, [r2]
cmp r3, #0
beq out_psci_features
cmp r1, r3
addne r2, r2, #8
bne 1b
out_psci_features:
ldr r0, [r2, #4]
bx lr
@ r0: return value ARM_PSCI_RET_SUCCESS or ARM_PSCI_RET_INVAL
@ r1: input target CPU ID in MPIDR format, original value in r1 may be dropped
@ r4: output validated CPU ID if ARM_PSCI_RET_SUCCESS returns, meaningless for
@ ARM_PSCI_RET_INVAL,suppose caller saves r4 before calling
LENTRY(psci_check_target_cpu_id)
@ Get the real CPU number
and r4, r1, #0xff
mov r0, #ARM_PSCI_RET_INVAL
@ Bit[31:24], bits must be zero.
tst r1, #0xff000000
bxne lr
@ Affinity level 2 - Cluster: only one cluster in LS1021xa.
tst r1, #0xff0000
bxne lr
@ Affinity level 1 - Processors: should be in 0xf00 format.
lsr r1, r1, #8
teq r1, #0xf
bxne lr
@ Affinity level 0 - CPU: only 0, 1 are valid in LS1021xa.
cmp r4, #2
bxge lr
mov r0, #ARM_PSCI_RET_SUCCESS
bx lr
ENDPROC(psci_check_target_cpu_id)
@ r1 = target CPU
@ r2 = target PC
.globl psci_cpu_on
@ -33,7 +116,9 @@ psci_cpu_on:
@ Clear and Get the correct CPU number
@ r1 = 0xf01
and r4, r1, #0xff
bl psci_check_target_cpu_id
cmp r0, #ARM_PSCI_RET_INVAL
beq out_psci_cpu_on
mov r0, r4
mov r1, r2
@ -101,6 +186,7 @@ holdoff_release:
@ Return
mov r0, #ARM_PSCI_RET_SUCCESS
out_psci_cpu_on:
pop {r4, r5, r6, lr}
bx lr
@ -108,6 +194,52 @@ holdoff_release:
psci_cpu_off:
bl psci_cpu_off_common
1: wfi
b 1b
.globl psci_affinity_info
psci_affinity_info:
push {lr}
mov r0, #ARM_PSCI_RET_INVAL
@ Verify Affinity level
cmp r2, #0
bne out_affinity_info
bl psci_check_target_cpu_id
cmp r0, #ARM_PSCI_RET_INVAL
beq out_affinity_info
mov r1, r4
@ Get RCPM base address
movw r4, #(CONFIG_SYS_FSL_RCPM_ADDR & 0xffff)
movt r4, #(CONFIG_SYS_FSL_RCPM_ADDR >> 16)
mov r0, #PSCI_AFFINITY_LEVEL_ON
@ Detect target CPU state
ldr r2, [r4, #RCPM_TWAITSR]
rev r2, r2
lsr r2, r2, r1
ands r2, r2, #1
beq out_affinity_info
mov r0, #PSCI_AFFINITY_LEVEL_OFF
out_affinity_info:
pop {pc}
.globl psci_system_reset
psci_system_reset:
@ Get DCFG base address
movw r1, #(CONFIG_SYS_FSL_GUTS_ADDR & 0xffff)
movt r1, #(CONFIG_SYS_FSL_GUTS_ADDR >> 16)
mov r2, #DCFG_CCSR_RSTCR_RESET_REQ
rev r2, r2
str r2, [r1, #DCFG_CCSR_RSTCR]
1: wfi
b 1b

78
arch/arm/cpu/armv7/psci.S
View File

@ -46,20 +46,62 @@ ENTRY(default_psci_vector)
ENDPROC(default_psci_vector)
.weak default_psci_vector
ENTRY(psci_version)
ENTRY(psci_cpu_suspend)
ENTRY(psci_cpu_off)
ENTRY(psci_cpu_on)
ENTRY(psci_affinity_info)
ENTRY(psci_migrate)
ENTRY(psci_migrate_info_type)
ENTRY(psci_migrate_info_up_cpu)
ENTRY(psci_system_off)
ENTRY(psci_system_reset)
ENTRY(psci_features)
ENTRY(psci_cpu_freeze)
ENTRY(psci_cpu_default_suspend)
ENTRY(psci_node_hw_state)
ENTRY(psci_system_suspend)
ENTRY(psci_set_suspend_mode)
ENTRY(psi_stat_residency)
ENTRY(psci_stat_count)
mov r0, #ARM_PSCI_RET_NI @ Return -1 (Not Implemented)
mov pc, lr
ENDPROC(psci_stat_count)
ENDPROC(psi_stat_residency)
ENDPROC(psci_set_suspend_mode)
ENDPROC(psci_system_suspend)
ENDPROC(psci_node_hw_state)
ENDPROC(psci_cpu_default_suspend)
ENDPROC(psci_cpu_freeze)
ENDPROC(psci_features)
ENDPROC(psci_system_reset)
ENDPROC(psci_system_off)
ENDPROC(psci_migrate_info_up_cpu)
ENDPROC(psci_migrate_info_type)
ENDPROC(psci_migrate)
ENDPROC(psci_affinity_info)
ENDPROC(psci_cpu_on)
ENDPROC(psci_cpu_off)
ENDPROC(psci_cpu_suspend)
ENDPROC(psci_version)
.weak psci_version
.weak psci_cpu_suspend
.weak psci_cpu_off
.weak psci_cpu_on
.weak psci_affinity_info
.weak psci_migrate
.weak psci_migrate_info_type
.weak psci_migrate_info_up_cpu
.weak psci_system_off
.weak psci_system_reset
.weak psci_features
.weak psci_cpu_freeze
.weak psci_cpu_default_suspend
.weak psci_node_hw_state
.weak psci_system_suspend
.weak psci_set_suspend_mode
.weak psi_stat_residency
.weak psci_stat_count
_psci_table:
.word ARM_PSCI_FN_CPU_SUSPEND
@ -70,6 +112,42 @@ _psci_table:
.word psci_cpu_on
.word ARM_PSCI_FN_MIGRATE
.word psci_migrate
.word ARM_PSCI_0_2_FN_PSCI_VERSION
.word psci_version
.word ARM_PSCI_0_2_FN_CPU_SUSPEND
.word psci_cpu_suspend
.word ARM_PSCI_0_2_FN_CPU_OFF
.word psci_cpu_off
.word ARM_PSCI_0_2_FN_CPU_ON
.word psci_cpu_on
.word ARM_PSCI_0_2_FN_AFFINITY_INFO
.word psci_affinity_info
.word ARM_PSCI_0_2_FN_MIGRATE
.word psci_migrate
.word ARM_PSCI_0_2_FN_MIGRATE_INFO_TYPE
.word psci_migrate_info_type
.word ARM_PSCI_0_2_FN_MIGRATE_INFO_UP_CPU
.word psci_migrate_info_up_cpu
.word ARM_PSCI_0_2_FN_SYSTEM_OFF
.word psci_system_off
.word ARM_PSCI_0_2_FN_SYSTEM_RESET
.word psci_system_reset
.word ARM_PSCI_1_0_FN_PSCI_FEATURES
.word psci_features
.word ARM_PSCI_1_0_FN_CPU_FREEZE
.word psci_cpu_freeze
.word ARM_PSCI_1_0_FN_CPU_DEFAULT_SUSPEND
.word psci_cpu_default_suspend
.word ARM_PSCI_1_0_FN_NODE_HW_STATE
.word psci_node_hw_state
.word ARM_PSCI_1_0_FN_SYSTEM_SUSPEND
.word psci_system_suspend
.word ARM_PSCI_1_0_FN_SET_SUSPEND_MODE
.word psci_set_suspend_mode
.word ARM_PSCI_1_0_FN_STAT_RESIDENCY
.word psi_stat_residency
.word ARM_PSCI_1_0_FN_STAT_COUNT
.word psci_stat_count
.word 0
.word 0

4
arch/arm/cpu/armv8/fsl-layerscape/Makefile
View File

@ -33,3 +33,7 @@ endif
ifneq ($(CONFIG_LS1012A),)
obj-$(CONFIG_SYS_HAS_SERDES) += ls1012a_serdes.o
endif
ifneq ($(CONFIG_LS1046A),)
obj-$(CONFIG_SYS_HAS_SERDES) += ls1046a_serdes.o
endif

8
arch/arm/cpu/armv8/fsl-layerscape/cpu.c
View File

@ -145,11 +145,14 @@ static inline void final_mmu_setup(void)
set_ttbr_tcr_mair(el, gd->arch.tlb_addr, get_tcr(el, NULL, NULL),
MEMORY_ATTRIBUTES);
/*
* MMU is already enabled, just need to invalidate TLB to load the
* EL3 MMU is already enabled, just need to invalidate TLB to load the
* new table. The new table is compatible with the current table, if
* MMU somehow walks through the new table before invalidation TLB,
* it still works. So we don't need to turn off MMU here.
* When EL2 MMU table is created by calling this function, MMU needs
* to be enabled.
*/
set_sctlr(get_sctlr() | CR_M);
}
u64 get_page_table_size(void)
@ -309,7 +312,8 @@ int print_cpuinfo(void)
printf("CPU%d(%s):%-4s MHz ", core,
type == TY_ITYP_VER_A7 ? "A7 " :
(type == TY_ITYP_VER_A53 ? "A53" :
(type == TY_ITYP_VER_A57 ? "A57" : " ")),
(type == TY_ITYP_VER_A57 ? "A57" :
(type == TY_ITYP_VER_A72 ? "A72" : " "))),
strmhz(buf, sysinfo.freq_processor[core]));
}
printf("\n Bus: %-4s MHz ",

42
arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc
View File

@ -3,6 +3,7 @@ SoC overview
1. LS1043A
2. LS2080A
3. LS1012A
4. LS1046A
LS1043A
---------
@ -127,3 +128,44 @@ The LS1012A SoC includes the following function and features:
- Two WatchDog timers
- ARM generic timer
- QorIQ platform's trust architecture 2.1
LS1046A
--------
The LS1046A integrated multicore processor combines four ARM Cortex-A72
processor cores with datapath acceleration optimized for L2/3 packet
processing, single pass security offload and robust traffic management
and quality of service.
The LS1046A SoC includes the following function and features:
- Four 64-bit ARM Cortex-A72 CPUs
- 2 MB unified L2 Cache
- One 64-bit DDR4 SDRAM memory controllers with ECC and interleaving
support
- Data Path Acceleration Architecture (DPAA) incorporating acceleration the
the following functions:
- Packet parsing, classification, and distribution (FMan)
- Queue management for scheduling, packet sequencing, and congestion
management (QMan)
- Hardware buffer management for buffer allocation and de-allocation (BMan)
- Cryptography acceleration (SEC)
- Two Configurable x4 SerDes
- Two PLLs per four-lane SerDes
- Support for 10G operation
- Ethernet interfaces by FMan
- Up to 2 x XFI supporting 10G interface (MAC 9, 10)
- Up to 1 x QSGMII (MAC 5, 6, 10, 1)
- Up to 4 x SGMII supporting 1000Mbps (MAC 5, 6, 9, 10)
- Up to 3 x SGMII supporting 2500Mbps (MAC 5, 9, 10)
- Up to 2 x RGMII supporting 1000Mbps (MAC 3, 4)
- High-speed peripheral interfaces
- Three PCIe 3.0 controllers, one supporting x4 operation
- One serial ATA (SATA 3.0) controllers
- Additional peripheral interfaces
- Three high-speed USB 3.0 controllers with integrated PHY
- Enhanced secure digital host controller (eSDXC/eMMC)
- Quad Serial Peripheral Interface (QSPI) Controller
- Serial peripheral interface (SPI) controller
- Four I2C controllers
- Two DUARTs
- Integrated flash controller (IFC) supporting NAND and NOR flash
- QorIQ platform's trust architecture 2.1

19
arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c
View File

@ -13,6 +13,9 @@
#ifdef CONFIG_SYS_FSL_SRDS_1
static u8 serdes1_prtcl_map[SERDES_PRCTL_COUNT];
#endif
#ifdef CONFIG_SYS_FSL_SRDS_2
static u8 serdes2_prtcl_map[SERDES_PRCTL_COUNT];
#endif
int is_serdes_configured(enum srds_prtcl device)
{
@ -21,6 +24,9 @@ int is_serdes_configured(enum srds_prtcl device)
#ifdef CONFIG_SYS_FSL_SRDS_1
ret |= serdes1_prtcl_map[device];
#endif
#ifdef CONFIG_SYS_FSL_SRDS_2
ret |= serdes2_prtcl_map[device];
#endif
return !!ret;
}
@ -37,6 +43,12 @@ int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
cfg &= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
cfg >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
break;
#endif
#ifdef CONFIG_SYS_FSL_SRDS_2
case FSL_SRDS_2:
cfg &= FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK;
cfg >>= FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_SHIFT;
break;
#endif
default:
printf("invalid SerDes%d\n", sd);
@ -114,4 +126,11 @@ void fsl_serdes_init(void)
FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT,
serdes1_prtcl_map);
#endif
#ifdef CONFIG_SYS_FSL_SRDS_2
serdes_init(FSL_SRDS_2,
CONFIG_SYS_FSL_SERDES_ADDR,
FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK,
FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_SHIFT,
serdes2_prtcl_map);
#endif
}

25
arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
View File

@ -107,6 +107,12 @@ void get_sys_info(struct sys_info *sys_info)
case 3:
sys_info->freq_fman[0] = freq_c_pll[0] / 3;
break;
case 4:
sys_info->freq_fman[0] = freq_c_pll[0] / 4;
break;
case 5:
sys_info->freq_fman[0] = sys_info->freq_systembus;
break;
case 6:
sys_info->freq_fman[0] = freq_c_pll[1] / 2;
break;
@ -124,8 +130,23 @@ void get_sys_info(struct sys_info *sys_info)
#ifdef CONFIG_FSL_ESDHC
#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
rcw_tmp = in_be32(&gur->rcwsr[15]);
rcw_tmp = (rcw_tmp & HWA_CGA_M2_CLK_SEL) >> HWA_CGA_M2_CLK_SHIFT;
sys_info->freq_sdhc = freq_c_pll[1] / rcw_tmp;
switch ((rcw_tmp & HWA_CGA_M2_CLK_SEL) >> HWA_CGA_M2_CLK_SHIFT) {
case 1:
sys_info->freq_sdhc = freq_c_pll[1];
break;
case 2:
sys_info->freq_sdhc = freq_c_pll[1] / 2;
break;
case 3:
sys_info->freq_sdhc = freq_c_pll[1] / 3;
break;
case 6:
sys_info->freq_sdhc = freq_c_pll[0] / 2;
break;
default:
printf("Error: Unknown ESDHC clock select!\n");
break;
}
#else
sys_info->freq_sdhc = sys_info->freq_systembus;
#endif

99
arch/arm/cpu/armv8/fsl-layerscape/ls1046a_serdes.c Normal file
View File

@ -0,0 +1,99 @@
/*
* Copyright 2016 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/arch/fsl_serdes.h>
#include <asm/arch/immap_lsch2.h>
struct serdes_config {
u32 protocol;
u8 lanes[SRDS_MAX_LANES];
};
static struct serdes_config serdes1_cfg_tbl[] = {
/* SerDes 1 */
{0x3333, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC5,
SGMII_FM1_DTSEC6} },
{0x1133, {XFI_FM1_MAC9, XFI_FM1_MAC10, SGMII_FM1_DTSEC5,
SGMII_FM1_DTSEC6} },
{0x1333, {XFI_FM1_MAC9, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC5,
SGMII_FM1_DTSEC6} },
{0x2333, {SGMII_2500_FM1_DTSEC9, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC5,
SGMII_FM1_DTSEC6} },
{0x2233, {SGMII_2500_FM1_DTSEC9, SGMII_2500_FM1_DTSEC10,
SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
{0x1040, {XFI_FM1_MAC9, NONE, QSGMII_FM1_A, NONE} },
{0x2040, {SGMII_2500_FM1_DTSEC9, NONE, QSGMII_FM1_A, NONE} },
{0x1163, {XFI_FM1_MAC9, XFI_FM1_MAC10, PCIE1, SGMII_FM1_DTSEC6} },
{0x2263, {SGMII_2500_FM1_DTSEC9, SGMII_2500_FM1_DTSEC10, PCIE1,
SGMII_FM1_DTSEC6} },
{0x3363, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, PCIE1,
SGMII_FM1_DTSEC6} },
{0x2223, {SGMII_2500_FM1_DTSEC9, SGMII_2500_FM1_DTSEC10,
SGMII_2500_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
{}
};
static struct serdes_config serdes2_cfg_tbl[] = {
/* SerDes 2 */
{0x8888, {PCIE1, PCIE1, PCIE1, PCIE1} },
{0x5559, {PCIE1, PCIE2, PCIE3, SATA1} },
{0x5577, {PCIE1, PCIE2, PCIE3, PCIE3} },
{0x5506, {PCIE1, PCIE2, NONE, PCIE3} },
{0x0506, {NONE, PCIE2, NONE, PCIE3} },
{0x0559, {NONE, PCIE2, PCIE3, SATA1} },
{0x5A59, {PCIE1, SGMII_FM1_DTSEC2, PCIE3, SATA1} },
{0x5A06, {PCIE1, SGMII_FM1_DTSEC2, NONE, PCIE3} },
{}
};
static struct serdes_config *serdes_cfg_tbl[] = {
serdes1_cfg_tbl,
serdes2_cfg_tbl,
};
enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
{
struct serdes_config *ptr;
if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
return 0;
ptr = serdes_cfg_tbl[serdes];
while (ptr->protocol) {
if (ptr->protocol == cfg)
return ptr->lanes[lane];
ptr++;
}
return 0;
}
int is_serdes_prtcl_valid(int serdes, u32 prtcl)
{
int i;
struct serdes_config *ptr;
if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
return 0;
ptr = serdes_cfg_tbl[serdes];
while (ptr->protocol) {
if (ptr->protocol == prtcl)
break;
ptr++;
}
if (!ptr->protocol)
return 0;
for (i = 0; i < SRDS_MAX_LANES; i++) {
if (ptr->lanes[i] != NONE)
return 1;
}
return 0;
}

86
arch/arm/include/asm/arch-fsl-layerscape/config.h
View File

@ -149,43 +149,43 @@
#define CONFIG_ARM_ERRATA_833471
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
#elif defined(CONFIG_LS1043A)
#define CONFIG_MAX_CPUS 4
#elif defined(CONFIG_FSL_LSCH2)
#define CONFIG_SYS_CACHELINE_SIZE 64
#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_SYS_FSL_SEC_COMPAT 5
#define CONFIG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */
#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00200000 /* 2M */
#define CONFIG_SYS_CCSRBAR_DEFAULT 0x01000000
#define CONFIG_SYS_FSL_CCSR_SCFG_BE
#define CONFIG_SYS_FSL_ESDHC_BE
#define CONFIG_SYS_FSL_WDOG_BE
#define CONFIG_SYS_FSL_DSPI_BE
#define CONFIG_SYS_FSL_QSPI_BE
#define CONFIG_SYS_FSL_CCSR_GUR_BE
#define CONFIG_SYS_FSL_PEX_LUT_BE
#define CONFIG_SYS_FSL_SEC_BE
#define CONFIG_SYS_FSL_SRDS_1
/* SoC related */
#ifdef CONFIG_LS1043A
#define CONFIG_MAX_CPUS 4
#define CONFIG_SYS_FMAN_V3
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_NUM_FM1_DTSEC 7
#define CONFIG_SYS_NUM_FM1_10GEC 1
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_SYS_CCSRBAR_DEFAULT 0x01000000
#define CONFIG_SYS_FSL_SEC_COMPAT 5
#define CONFIG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */
#define CONFIG_SYS_FSL_OCRAM_SIZE 0x200000 /* 2 MiB */
#define CONFIG_SYS_FSL_DDR_BE
#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
#define CONFIG_SYS_FSL_CCSR_GUR_BE
#define CONFIG_SYS_FSL_CCSR_SCFG_BE
#define CONFIG_SYS_FSL_IFC_BE
#define CONFIG_SYS_FSL_ESDHC_BE
#define CONFIG_SYS_FSL_WDOG_BE
#define CONFIG_SYS_FSL_DSPI_BE
#define CONFIG_SYS_FSL_QSPI_BE
#define CONFIG_SYS_FSL_PEX_LUT_BE
#define QE_MURAM_SIZE 0x6000UL
#define MAX_QE_RISC 1
#define QE_NUM_OF_SNUM 28
#define SRDS_MAX_LANES 4
#define CONFIG_SYS_FSL_SRDS_1
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
#define CONFIG_SYS_FSL_IFC_BE
#define CONFIG_SYS_FSL_SFP_VER_3_2
#define CONFIG_SYS_FSL_SEC_MON_BE
#define CONFIG_SYS_FSL_SEC_BE
#define CONFIG_SYS_FSL_SFP_BE
#define CONFIG_SYS_FSL_SRK_LE
#define CONFIG_KEY_REVOCATION
@ -205,32 +205,40 @@
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
#elif defined(CONFIG_LS1012A)
#define CONFIG_MAX_CPUS 1
#define CONFIG_SYS_CACHELINE_SIZE 64
#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_SYS_CCSRBAR_DEFAULT 0x01000000
#define CONFIG_SYS_FSL_SEC_COMPAT 5
#undef CONFIG_SYS_FSL_DDRC_ARM_GEN3
#define CONFIG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */
#define CONFIG_SYS_FSL_OCRAM_SIZE 0x200000 /* 2 MiB */
#define GICD_BASE 0x01401000
#define GICC_BASE 0x01402000
#elif defined(CONFIG_LS1046A)
#define CONFIG_MAX_CPUS 4
#define CONFIG_SYS_FMAN_V3
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_NUM_FM1_DTSEC 8
#define CONFIG_SYS_NUM_FM1_10GEC 2
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
#define CONFIG_SYS_FSL_DDR_BE
#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
#define CONFIG_SYS_FSL_CCSR_GUR_BE
#define CONFIG_SYS_FSL_CCSR_SCFG_BE
#define CONFIG_SYS_FSL_ESDHC_BE
#define CONFIG_SYS_FSL_WDOG_BE
#define CONFIG_SYS_FSL_DSPI_BE
#define CONFIG_SYS_FSL_QSPI_BE
#define CONFIG_SYS_FSL_PEX_LUT_BE
#define CONFIG_SYS_FSL_SRDS_2
#define CONFIG_SYS_FSL_IFC_BE
#define CONFIG_SYS_FSL_SFP_VER_3_2
#define CONFIG_SYS_FSL_SNVS_LE
#define CONFIG_SYS_FSL_SFP_BE
#define CONFIG_SYS_FSL_SRK_LE
#define CONFIG_KEY_REVOCATION
#define SRDS_MAX_LANES 4
#define CONFIG_SYS_FSL_SRDS_1
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
#define CONFIG_SYS_FSL_SEC_BE
/* SMMU Defintions */
#define SMMU_BASE 0x09000000
/* Generic Interrupt Controller Definitions */
#define GICD_BASE 0x01410000
#define GICC_BASE 0x01420000
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
#else
#error SoC not defined
#endif
#endif
#endif /* _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_ */

2
arch/arm/include/asm/arch-fsl-layerscape/cpu.h
View File

@ -13,6 +13,8 @@ static struct cpu_type cpu_type_list[] = {
CPU_TYPE_ENTRY(LS2045A, LS2045A, 4),
CPU_TYPE_ENTRY(LS1043A, LS1043A, 4),
CPU_TYPE_ENTRY(LS1023A, LS1023A, 2),
CPU_TYPE_ENTRY(LS1046A, LS1046A, 4),
CPU_TYPE_ENTRY(LS1026A, LS1026A, 2),
CPU_TYPE_ENTRY(LS2040A, LS2040A, 4),
CPU_TYPE_ENTRY(LS1012A, LS1012A, 1),
};

3
arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
View File

@ -140,6 +140,7 @@ enum srds_prtcl {
enum srds {
FSL_SRDS_1 = 0,
FSL_SRDS_2 = 1,
};
#endif
@ -150,7 +151,7 @@ int serdes_get_first_lane(u32 sd, enum srds_prtcl device);
enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane);
int is_serdes_prtcl_valid(int serdes, u32 prtcl);
#ifdef CONFIG_LS1043A
#ifdef CONFIG_FSL_LSCH2
const char *serdes_clock_to_string(u32 clock);
int get_serdes_protocol(void);
#endif

9
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
View File

@ -31,9 +31,9 @@
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011c0600)
#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_IMMR + 0x011d0500)
#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_IMMR + 0x011d0600)
#define CONFIG_SYS_LS1043A_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x01f00000)
#define CONFIG_SYS_LS1043A_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02000000)
#define CONFIG_SYS_LS1043A_XHCI_USB3_ADDR (CONFIG_SYS_IMMR + 0x02100000)
#define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x01f00000)
#define CONFIG_SYS_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02000000)
#define CONFIG_SYS_XHCI_USB3_ADDR (CONFIG_SYS_IMMR + 0x02100000)
#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000)
#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000)
#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x2600000)
@ -94,6 +94,7 @@
#define TY_ITYP_VER_A7 0x1
#define TY_ITYP_VER_A53 0x2
#define TY_ITYP_VER_A57 0x3
#define TY_ITYP_VER_A72 0x4
#define TP_CLUSTER_EOC 0xc0000000 /* end of clusters */
#define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */
@ -227,6 +228,8 @@ struct ccsr_gur {
#define FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK 0x3f
#define FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK 0xffff0000
#define FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT 16
#define FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK 0x0000ffff
#define FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_SHIFT 0
#define RCW_SB_EN_REG_INDEX 7
#define RCW_SB_EN_MASK 0x00200000

5
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
View File

@ -52,8 +52,8 @@
#define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x01020000)
#define I2C4_BASE_ADDR (CONFIG_SYS_IMMR + 0x01030000)
#define CONFIG_SYS_LS2080A_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000)
#define CONFIG_SYS_LS2080A_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02110000)
#define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000)
#define CONFIG_SYS_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02110000)
/* TZ Address Space Controller Definitions */
#define TZASC1_BASE 0x01100000 /* as per CCSR map. */
@ -156,6 +156,7 @@
#define TY_ITYP_VER_A7 0x1
#define TY_ITYP_VER_A53 0x2
#define TY_ITYP_VER_A57 0x3
#define TY_ITYP_VER_A72 0x4
#define TP_CLUSTER_EOC 0x80000000 /* end of clusters */
#define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */

2
arch/arm/include/asm/arch-fsl-layerscape/soc.h
View File

@ -44,6 +44,8 @@ struct cpu_type {
#define SVR_LS1012A 0x870400
#define SVR_LS1043A 0x879200
#define SVR_LS1023A 0x879208
#define SVR_LS1046A 0x870700
#define SVR_LS1026A 0x870708
#define SVR_LS2045A 0x870120
#define SVR_LS2080A 0x870110
#define SVR_LS2085A 0x870100

9
arch/arm/include/asm/arch-ls102xa/config.h
View File

@ -10,7 +10,7 @@
#define CONFIG_SYS_CACHELINE_SIZE 64
#define OCRAM_BASE_ADDR 0x10000000
#define OCRAM_SIZE 0x00020000
#define OCRAM_SIZE 0x00010000
#define OCRAM_BASE_S_ADDR 0x10010000
#define OCRAM_S_SIZE 0x00010000
@ -32,16 +32,15 @@
#define CONFIG_SYS_FSL_SERDES_ADDR (CONFIG_SYS_IMMR + 0x00ea0000)
#define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00ee0000)
#define CONFIG_SYS_FSL_LS1_CLK_ADDR (CONFIG_SYS_IMMR + 0x00ee1000)
#define CONFIG_SYS_FSL_RCPM_ADDR (CONFIG_SYS_IMMR + 0x00ee2000)
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011c0500)
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011d0500)
#define CONFIG_SYS_DCU_ADDR (CONFIG_SYS_IMMR + 0x01ce0000)
#define CONFIG_SYS_LS102XA_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000)
#define CONFIG_SYS_LS102XA_USB1_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_LS102XA_USB1_OFFSET)
#define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000)
#define CONFIG_SYS_EHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x07600000)
#define CONFIG_SYS_FSL_SEC_OFFSET 0x00700000
#define CONFIG_SYS_FSL_JR0_OFFSET 0x00710000
#define CONFIG_SYS_LS102XA_USB1_OFFSET 0x07600000
#define CONFIG_SYS_TSEC1_OFFSET 0x01d10000
#define CONFIG_SYS_TSEC2_OFFSET 0x01d50000
#define CONFIG_SYS_TSEC3_OFFSET 0x01d90000

68
arch/arm/include/asm/fsl_secure_boot.h
View File

@ -17,8 +17,6 @@
#ifdef CONFIG_CHAIN_OF_TRUST
#define CONFIG_CMD_ESBC_VALIDATE
#define CONFIG_CMD_BLOB
#define CONFIG_CMD_HASH
#define CONFIG_FSL_SEC_MON
#define CONFIG_SHA_HW_ACCEL
#define CONFIG_SHA_PROG_HW_ACCEL
@ -28,6 +26,28 @@
#define CONFIG_FSL_CAAM
#endif
#ifdef CONFIG_SPL_BUILD
#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SPL_DM 1
#define CONFIG_SPL_CRYPTO_SUPPORT
#define CONFIG_SPL_HASH_SUPPORT
#define CONFIG_SPL_RSA
#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
/*
* Define the key hash for U-Boot here if public/private key pair used to
* sign U-boot are different from the SRK hash put in the fuse
* Example of defining KEY_HASH is
* #define CONFIG_SPL_UBOOT_KEY_HASH \
* "41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b"
* else leave it defined as NULL
*/
#define CONFIG_SPL_UBOOT_KEY_HASH NULL
#endif /* ifdef CONFIG_SPL_BUILD */
#ifndef CONFIG_SPL_BUILD
#define CONFIG_CMD_BLOB
#define CONFIG_CMD_HASH
#define CONFIG_KEY_REVOCATION
#ifndef CONFIG_SYS_RAMBOOT
/* The key used for verification of next level images
@ -58,39 +78,55 @@
"setenv hwconfig \'fsl_ddr:ctlr_intlv=null,bank_intlv=null\';"
#else
#define CONFIG_EXTRA_ENV \
"setenv fdt_high 0xcfffffff;" \
"setenv initrd_high 0xcfffffff;" \
"setenv fdt_high 0xffffffff;" \
"setenv initrd_high 0xffffffff;" \
"setenv hwconfig \'fsl_ddr:ctlr_intlv=null,bank_intlv=null\';"
#endif
/* Copying Bootscript and Header to DDR from NOR for LS2 and for rest, from
* Non-XIP Memory (Nand/SD)*/
#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_LS2080A)
#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_LS2080A) || \
defined(CONFIG_SD_BOOT)
#define CONFIG_BOOTSCRIPT_COPY_RAM
#endif
/* The address needs to be modified according to NOR and DDR memory map */
/* The address needs to be modified according to NOR, NAND, SD and
* DDR memory map
*/
#ifdef CONFIG_LS2080A
#define CONFIG_BS_HDR_ADDR_FLASH 0x583920000
#define CONFIG_BS_ADDR_FLASH 0x583900000
#define CONFIG_BS_HDR_ADDR_DEVICE 0x583920000
#define CONFIG_BS_ADDR_DEVICE 0x583900000
#define CONFIG_BS_HDR_ADDR_RAM 0xa3920000
#define CONFIG_BS_ADDR_RAM 0xa3900000
#define CONFIG_BS_HDR_SIZE 0x00002000
#define CONFIG_BS_SIZE 0x00001000
#else
#define CONFIG_BS_HDR_ADDR_FLASH 0x600a0000
#define CONFIG_BS_ADDR_FLASH 0x60060000
#define CONFIG_BS_HDR_ADDR_RAM 0xa0060000
#define CONFIG_BS_ADDR_RAM 0xa0060000
#ifdef CONFIG_SD_BOOT
/* For SD boot address and size are assigned in terms of sector
* offset and no. of sectors respectively.
*/
#define CONFIG_BS_HDR_ADDR_DEVICE 0x00000800
#define CONFIG_BS_ADDR_DEVICE 0x00000840
#define CONFIG_BS_HDR_SIZE 0x00000010
#define CONFIG_BS_SIZE 0x00000008
#else
#define CONFIG_BS_HDR_ADDR_DEVICE 0x600a0000
#define CONFIG_BS_ADDR_DEVICE 0x60060000
#define CONFIG_BS_HDR_SIZE 0x00002000
#define CONFIG_BS_SIZE 0x00001000
#endif /* #ifdef CONFIG_SD_BOOT */
#define CONFIG_BS_HDR_ADDR_RAM 0x81000000
#define CONFIG_BS_ADDR_RAM 0x81020000
#endif
#ifdef CONFIG_BOOTSCRIPT_COPY_RAM
#define CONFIG_BOOTSCRIPT_HDR_ADDR CONFIG_BS_HDR_ADDR_RAM
#define CONFIG_BS_HDR_SIZE 0x00002000
#define CONFIG_BOOTSCRIPT_ADDR CONFIG_BS_ADDR_RAM
#define CONFIG_BS_SIZE 0x00001000
#else
#define CONFIG_BOOTSCRIPT_HDR_ADDR CONFIG_BS_HDR_ADDR_FLASH
/* BS_HDR_SIZE, BOOTSCRIPT_ADDR and BS_SIZE are not required */
#define CONFIG_BOOTSCRIPT_HDR_ADDR CONFIG_BS_HDR_ADDR_DEVICE
/* BOOTSCRIPT_ADDR is not required */
#endif
#include <config_fsl_chain_trust.h>
#endif /* #ifndef CONFIG_SPL_BUILD */
#endif /* #ifdef CONFIG_CHAIN_OF_TRUST */
#endif

21
arch/arm/include/asm/psci.h
View File

@ -31,6 +31,12 @@
#define ARM_PSCI_RET_NI (-1)
#define ARM_PSCI_RET_INVAL (-2)
#define ARM_PSCI_RET_DENIED (-3)
#define ARM_PSCI_RET_ALREADY_ON (-4)
#define ARM_PSCI_RET_ON_PENDING (-5)
#define ARM_PSCI_RET_INTERNAL_FAILURE (-6)
#define ARM_PSCI_RET_NOT_PRESENT (-7)
#define ARM_PSCI_RET_DISABLED (-8)
#define ARM_PSCI_RET_INVALID_ADDRESS (-9)
/* PSCI 0.2 interface */
#define ARM_PSCI_0_2_FN_BASE 0x84000000
@ -47,10 +53,25 @@
#define ARM_PSCI_0_2_FN_SYSTEM_OFF ARM_PSCI_0_2_FN(8)
#define ARM_PSCI_0_2_FN_SYSTEM_RESET ARM_PSCI_0_2_FN(9)
/* PSCI 1.0 interface */
#define ARM_PSCI_1_0_FN_PSCI_FEATURES ARM_PSCI_0_2_FN(10)
#define ARM_PSCI_1_0_FN_CPU_FREEZE ARM_PSCI_0_2_FN(11)
#define ARM_PSCI_1_0_FN_CPU_DEFAULT_SUSPEND ARM_PSCI_0_2_FN(12)
#define ARM_PSCI_1_0_FN_NODE_HW_STATE ARM_PSCI_0_2_FN(13)
#define ARM_PSCI_1_0_FN_SYSTEM_SUSPEND ARM_PSCI_0_2_FN(14)
#define ARM_PSCI_1_0_FN_SET_SUSPEND_MODE ARM_PSCI_0_2_FN(15)
#define ARM_PSCI_1_0_FN_STAT_RESIDENCY ARM_PSCI_0_2_FN(16)
#define ARM_PSCI_1_0_FN_STAT_COUNT ARM_PSCI_0_2_FN(17)
/* 1KB stack per core */
#define ARM_PSCI_STACK_SHIFT 10
#define ARM_PSCI_STACK_SIZE (1 << ARM_PSCI_STACK_SHIFT)
/* PSCI affinity level state returned by AFFINITY_INFO */
#define PSCI_AFFINITY_LEVEL_ON 0
#define PSCI_AFFINITY_LEVEL_OFF 1
#define PSCI_AFFINITY_LEVEL_ON_PENDING 2
#ifndef __ASSEMBLY__
#include <asm/types.h>

4
arch/powerpc/include/asm/fsl_secure_boot.h
View File

@ -128,10 +128,10 @@
/* If Boot Script is not on NOR and is required to be copied on RAM */
#ifdef CONFIG_BOOTSCRIPT_COPY_RAM
#define CONFIG_BS_HDR_ADDR_RAM 0x00010000
#define CONFIG_BS_HDR_ADDR_FLASH 0x00800000
#define CONFIG_BS_HDR_ADDR_DEVICE 0x00800000
#define CONFIG_BS_HDR_SIZE 0x00002000
#define CONFIG_BS_ADDR_RAM 0x00012000
#define CONFIG_BS_ADDR_FLASH 0x00802000
#define CONFIG_BS_ADDR_DEVICE 0x00802000
#define CONFIG_BS_SIZE 0x00001000
#define CONFIG_BOOTSCRIPT_HDR_ADDR CONFIG_BS_HDR_ADDR_RAM

34
board/freescale/common/fsl_chain_of_trust.c
View File

@ -10,6 +10,10 @@
#include <fsl_sfp.h>
#include <dm/root.h>
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_FRAMEWORK)
#include <spl.h>
#endif
#ifdef CONFIG_ADDR_MAP
#include <asm/mmu.h>
#endif
@ -115,7 +119,7 @@ void spl_validate_uboot(uint32_t hdr_addr, uintptr_t img_addr)
* do not use common SPL framework, so need to call this function here.
*/
#if defined(CONFIG_SPL_DM) && (!defined(CONFIG_SPL_FRAMEWORK))
dm_init_and_scan(false);
dm_init_and_scan(true);
#endif
res = fsl_secboot_validate(hdr_addr, CONFIG_SPL_UBOOT_KEY_HASH,
&img_addr);
@ -123,4 +127,32 @@ void spl_validate_uboot(uint32_t hdr_addr, uintptr_t img_addr)
if (res == 0)
printf("SPL: Validation of U-boot successful\n");
}
#ifdef CONFIG_SPL_FRAMEWORK
/* Override weak funtion defined in SPL framework to enable validation
* of main u-boot image before jumping to u-boot image.
*/
void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
{
typedef void __noreturn (*image_entry_noargs_t)(void);
uint32_t hdr_addr;
image_entry_noargs_t image_entry =
(image_entry_noargs_t)(unsigned long)spl_image->entry_point;
hdr_addr = (spl_image->entry_point + spl_image->size -
CONFIG_U_BOOT_HDR_SIZE);
spl_validate_uboot(hdr_addr, (uintptr_t)spl_image->entry_point);
/*
* In case of failure in validation, spl_validate_uboot would
* not return back in case of Production environment with ITS=1.
* Thus U-Boot will not start.
* In Development environment (ITS=0 and SB_EN=1), the function
* may return back in case of non-fatal failures.
*/
debug("image entry point: 0x%X\n", spl_image->entry_point);
image_entry();
}
#endif /* ifdef CONFIG_SPL_FRAMEWORK */
#endif /* ifdef CONFIG_SPL_BUILD */

1
board/freescale/ls1021aqds/Makefile
View File

@ -8,3 +8,4 @@ obj-y += ls1021aqds.o
obj-y += ddr.o
obj-y += eth.o
obj-$(CONFIG_FSL_DCU_FB) += dcu.o
obj-$(CONFIG_ARMV7_PSCI) += psci.o

33
board/freescale/ls1021aqds/psci.S Normal file
View File

@ -0,0 +1,33 @@
/*
* Copyright 2016 NXP Semiconductor.
* Author: Wang Dongsheng <dongsheng.wang@freescale.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <config.h>
#include <linux/linkage.h>
#include <asm/armv7.h>
#include <asm/psci.h>
.pushsection ._secure.text, "ax"
.arch_extension sec
.align 5
.globl psci_system_off
psci_system_off:
@ Get QIXIS base address
movw r1, #(QIXIS_BASE & 0xffff)
movt r1, #(QIXIS_BASE >> 16)
ldrb r2, [r1, #QIXIS_PWR_CTL]
orr r2, r2, #QIXIS_PWR_CTL_POWEROFF
strb r2, [r1, #QIXIS_PWR_CTL]
1: wfi
b 1b
.popsection

1
board/freescale/ls1021atwr/Makefile
View File

@ -6,3 +6,4 @@
obj-y += ls1021atwr.o
obj-$(CONFIG_FSL_DCU_FB) += dcu.o
obj-$(CONFIG_ARMV7_PSCI) += psci.o

7
board/freescale/ls1021atwr/ls1021atwr.c
View File

@ -503,6 +503,13 @@ int board_init(void)
return 0;
}
#if defined(CONFIG_SPL_BUILD)
void spl_board_init(void)
{
ls102xa_smmu_stream_id_init();
}
#endif
#ifdef CONFIG_BOARD_LATE_INIT
int board_late_init(void)
{

25
board/freescale/ls1021atwr/psci.S Normal file
View File

@ -0,0 +1,25 @@
/*
* Copyright 2016 NXP Semiconductor.
* Author: Wang Dongsheng <dongsheng.wang@freescale.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <config.h>
#include <linux/linkage.h>
#include <asm/armv7.h>
#include <asm/psci.h>
.pushsection ._secure.text, "ax"
.arch_extension sec
.align 5
.globl psci_system_off
psci_system_off:
1: wfi
b 1b
.popsection

1
board/freescale/ls1043aqds/MAINTAINERS
View File

@ -9,3 +9,4 @@ F: configs/ls1043aqds_nand_defconfig
F: configs/ls1043aqds_sdcard_ifc_defconfig
F: configs/ls1043aqds_sdcard_qspi_defconfig
F: configs/ls1043aqds_qspi_defconfig
F: configs/ls1043aqds_lpuart_defconfig

10
board/freescale/ls1043aqds/ls1043aqds.c
View File

@ -327,6 +327,7 @@ int ft_board_setup(void *blob, bd_t *bd)
{
u64 base[CONFIG_NR_DRAM_BANKS];
u64 size[CONFIG_NR_DRAM_BANKS];
u8 reg;
/* fixup DT for the two DDR banks */
base[0] = gd->bd->bi_dram[0].start;
@ -341,6 +342,15 @@ int ft_board_setup(void *blob, bd_t *bd)
fdt_fixup_fman_ethernet(blob);
fdt_fixup_board_enet(blob);
#endif
reg = QIXIS_READ(brdcfg[0]);
reg = (reg & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
/* Disable IFC if QSPI is enabled */
if (reg == 0xF)
do_fixup_by_compat(blob, "fsl,ifc",
"status", "disabled", 8 + 1, 1);
return 0;
}
#endif

1
board/freescale/ls2080aqds/MAINTAINERS
View File

@ -6,6 +6,7 @@ F: board/freescale/ls2080a/ls2080aqds.c
F: include/configs/ls2080aqds.h
F: configs/ls2080aqds_defconfig
F: configs/ls2080aqds_nand_defconfig
F: configs/ls2080aqds_qspi_defconfig
LS2080A_SECURE_BOOT BOARD
M: Saksham Jain <saksham.jain@nxp.freescale.com>

31
configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig Normal file
View File

@ -0,0 +1,31 @@
CONFIG_ARM=y
CONFIG_TARGET_LS1021ATWR=y
CONFIG_SPL=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SECURE_BOOT"
CONFIG_BOOTDELAY=0
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MMC=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_OF_LIBFDT=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_RSA=y
CONFIG_DM=y

1
drivers/crypto/fsl/fsl_rsa.c
View File

@ -53,6 +53,7 @@ U_BOOT_DRIVER(fsl_rsa_mod_exp) = {
.name = "fsl_rsa_mod_exp",
.id = UCLASS_MOD_EXP,
.ops = &fsl_mod_exp_ops,
.flags = DM_FLAG_PRE_RELOC,
};
U_BOOT_DEVICE(fsl_rsa) = {

9
drivers/i2c/fsl_i2c.c
View File

@ -583,12 +583,11 @@ static int fsl_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
static int fsl_i2c_ofdata_to_platdata(struct udevice *bus)
{
struct fsl_i2c_dev *dev = dev_get_priv(bus);
u64 reg;
u32 addr, size;
fdt_addr_t addr;
fdt_size_t size;
reg = fdtdec_get_addr(gd->fdt_blob, bus->of_offset, "reg");
addr = reg >> 32;
size = reg & 0xFFFFFFFF;
addr = fdtdec_get_addr_size_auto_noparent(gd->fdt_blob, bus->of_offset,
"reg", 0, &size);
dev->base = map_sysmem(CONFIG_SYS_IMMR + addr, size);

1
drivers/net/fm/Makefile
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@ -39,3 +39,4 @@ obj-$(CONFIG_PPC_T4080) += t4240.o
obj-$(CONFIG_PPC_B4420) += b4860.o
obj-$(CONFIG_PPC_B4860) += b4860.o
obj-$(CONFIG_LS1043A) += ls1043.o
obj-$(CONFIG_LS1046A) += ls1046.o

123
drivers/net/fm/ls1046.c Normal file
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@ -0,0 +1,123 @@
/*
* Copyright 2016 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <phy.h>
#include <fm_eth.h>
#include <asm/io.h>
#include <asm/arch/fsl_serdes.h>
#define FSL_CHASSIS2_RCWSR13_EC1 0xe0000000 /* bits 416..418 */
#define FSL_CHASSIS2_RCWSR13_EC1_DTSEC3_RGMII 0x00000000
#define FSL_CHASSIS2_RCWSR13_EC1_GPIO 0x20000000
#define FSL_CHASSIS2_RCWSR13_EC1_FTM 0xa0000000
#define FSL_CHASSIS2_RCWSR13_EC2 0x1c000000 /* bits 419..421 */
#define FSL_CHASSIS2_RCWSR13_EC2_DTSEC4_RGMII 0x00000000
#define FSL_CHASSIS2_RCWSR13_EC2_GPIO 0x04000000
#define FSL_CHASSIS2_RCWSR13_EC2_1588 0x08000000
#define FSL_CHASSIS2_RCWSR13_EC2_FTM 0x14000000
u32 port_to_devdisr[] = {
[FM1_DTSEC1] = FSL_CHASSIS2_DEVDISR2_DTSEC1_1,
[FM1_DTSEC2] = FSL_CHASSIS2_DEVDISR2_DTSEC1_2,
[FM1_DTSEC3] = FSL_CHASSIS2_DEVDISR2_DTSEC1_3,
[FM1_DTSEC4] = FSL_CHASSIS2_DEVDISR2_DTSEC1_4,
[FM1_DTSEC5] = FSL_CHASSIS2_DEVDISR2_DTSEC1_5,
[FM1_DTSEC6] = FSL_CHASSIS2_DEVDISR2_DTSEC1_6,
[FM1_DTSEC9] = FSL_CHASSIS2_DEVDISR2_DTSEC1_9,
[FM1_DTSEC10] = FSL_CHASSIS2_DEVDISR2_DTSEC1_10,
[FM1_10GEC1] = FSL_CHASSIS2_DEVDISR2_10GEC1_1,
[FM1_10GEC2] = FSL_CHASSIS2_DEVDISR2_10GEC1_2,
[FM1_10GEC3] = FSL_CHASSIS2_DEVDISR2_10GEC1_3,
[FM1_10GEC4] = FSL_CHASSIS2_DEVDISR2_10GEC1_4,
};
static int is_device_disabled(enum fm_port port)
{
struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
u32 devdisr2 = in_be32(&gur->devdisr2);
return port_to_devdisr[port] & devdisr2;
}
void fman_disable_port(enum fm_port port)
{
struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
setbits_be32(&gur->devdisr2, port_to_devdisr[port]);
}
phy_interface_t fman_port_enet_if(enum fm_port port)
{
struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
if (is_device_disabled(port))
return PHY_INTERFACE_MODE_NONE;
if ((port == FM1_10GEC1) && (is_serdes_configured(XFI_FM1_MAC9)))
return PHY_INTERFACE_MODE_XGMII;
if ((port == FM1_DTSEC9) && (is_serdes_configured(XFI_FM1_MAC9)))
return PHY_INTERFACE_MODE_NONE;
if ((port == FM1_10GEC2) && (is_serdes_configured(XFI_FM1_MAC10)))
return PHY_INTERFACE_MODE_XGMII;
if ((port == FM1_DTSEC10) && (is_serdes_configured(XFI_FM1_MAC10)))
return PHY_INTERFACE_MODE_NONE;
if (port == FM1_DTSEC3)
if ((rcwsr13 & FSL_CHASSIS2_RCWSR13_EC1) ==
FSL_CHASSIS2_RCWSR13_EC1_DTSEC3_RGMII)
return PHY_INTERFACE_MODE_RGMII;
if (port == FM1_DTSEC4)
if ((rcwsr13 & FSL_CHASSIS2_RCWSR13_EC2) ==
FSL_CHASSIS2_RCWSR13_EC2_DTSEC4_RGMII)
return PHY_INTERFACE_MODE_RGMII;
/* handle SGMII, only MAC 2/5/6/9/10 available */
switch (port) {
case FM1_DTSEC2:
case FM1_DTSEC5:
case FM1_DTSEC6:
case FM1_DTSEC9:
case FM1_DTSEC10:
if (is_serdes_configured(SGMII_FM1_DTSEC2 + port - FM1_DTSEC2))
return PHY_INTERFACE_MODE_SGMII;
break;
default:
break;
}
/* handle 2.5G SGMII, only MAC 5/9/10 available */
switch (port) {
case FM1_DTSEC5:
case FM1_DTSEC9:
case FM1_DTSEC10:
if (is_serdes_configured(SGMII_2500_FM1_DTSEC5 +
port - FM1_DTSEC5))
return PHY_INTERFACE_MODE_SGMII_2500;
break;
default:
break;
}
/* handle QSGMII, only MAC 1/5/6/10 available */
switch (port) {
case FM1_DTSEC1:
case FM1_DTSEC5:
case FM1_DTSEC6:
case FM1_DTSEC10:
if (is_serdes_configured(QSGMII_FM1_A))
return PHY_INTERFACE_MODE_QSGMII;
break;
default:
break;
}
return PHY_INTERFACE_MODE_NONE;
}

18
include/config_fsl_chain_trust.h
View File

@ -74,23 +74,27 @@
#ifdef CONFIG_BOOTSCRIPT_COPY_RAM
#define CONFIG_BS_COPY_ENV \
"setenv bs_hdr_ram " __stringify(CONFIG_BS_HDR_ADDR_RAM)";" \
"setenv bs_hdr_flash " __stringify(CONFIG_BS_HDR_ADDR_FLASH)";" \
"setenv bs_hdr_device " __stringify(CONFIG_BS_HDR_ADDR_DEVICE)";" \
"setenv bs_hdr_size " __stringify(CONFIG_BS_HDR_SIZE)";" \
"setenv bs_ram " __stringify(CONFIG_BS_ADDR_RAM)";" \
"setenv bs_flash " __stringify(CONFIG_BS_ADDR_FLASH)";" \
"setenv bs_device " __stringify(CONFIG_BS_ADDR_DEVICE)";" \
"setenv bs_size " __stringify(CONFIG_BS_SIZE)";"
/* For secure boot flow, default environment used will be used */
#if defined(CONFIG_SYS_RAMBOOT)
#if defined(CONFIG_RAMBOOT_NAND)
#define CONFIG_BS_COPY_CMD \
"nand read $bs_hdr_ram $bs_hdr_flash $bs_hdr_size ;" \
"nand read $bs_ram $bs_flash $bs_size ;"
"nand read $bs_hdr_ram $bs_hdr_device $bs_hdr_size ;" \
"nand read $bs_ram $bs_device $bs_size ;"
#endif /* CONFIG_RAMBOOT_NAND */
#else
#elif defined(CONFIG_SD_BOOT)
#define CONFIG_BS_COPY_CMD \
"cp.b $bs_hdr_flash $bs_hdr_ram $bs_hdr_size ;" \
"cp.b $bs_flash $bs_ram $bs_size ;"
"mmc read $bs_hdr_ram $bs_hdr_device $bs_hdr_size ;" \
"mmc read $bs_ram $bs_device $bs_size ;"
#else /* CONFIG_SD_BOOT */
#define CONFIG_BS_COPY_CMD \
"cp.b $bs_hdr_device $bs_hdr_ram $bs_hdr_size ;" \
"cp.b $bs_device $bs_ram $bs_size ;"
#endif
#endif /* CONFIG_BOOTSCRIPT_COPY_RAM */

5
include/configs/ls1021aqds.h
View File

@ -10,8 +10,11 @@
#define CONFIG_LS102XA
#define CONFIG_ARMV7_PSCI
#define CONFIG_ARMV7_PSCI_1_0
#define CONFIG_ARMV7_PSCI_NR_CPUS CONFIG_MAX_CPUS
#define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR
#define CONFIG_SYS_FSL_CLK
#define CONFIG_DISPLAY_CPUINFO
@ -280,6 +283,8 @@ unsigned long get_board_ddr_clk(void);
#define QIXIS_LBMAP_SHIFT 0
#define QIXIS_LBMAP_DFLTBANK 0x00
#define QIXIS_LBMAP_ALTBANK 0x04
#define QIXIS_PWR_CTL 0x21
#define QIXIS_PWR_CTL_POWEROFF 0x80
#define QIXIS_RST_CTL_RESET 0x44
#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
#define QIXIS_RCFG_CTL_RECONFIG_START 0x21

25
include/configs/ls1021atwr.h
View File

@ -10,8 +10,11 @@
#define CONFIG_LS102XA
#define CONFIG_ARMV7_PSCI
#define CONFIG_ARMV7_PSCI_1_0
#define CONFIG_ARMV7_PSCI_NR_CPUS CONFIG_MAX_CPUS
#define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR
#define CONFIG_SYS_FSL_CLK
#define CONFIG_DISPLAY_CPUINFO
@ -124,7 +127,18 @@
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_MMC_SUPPORT
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8
#ifdef CONFIG_SECURE_BOOT
#define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
/*
* HDR would be appended at end of image and copied to DDR along
* with U-Boot image.
*/
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS (0x400 + \
(CONFIG_U_BOOT_HDR_SIZE / 512)
#else
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400
#endif /* ifdef CONFIG_SECURE_BOOT */
#define CONFIG_SPL_TEXT_BASE 0x10000000
#define CONFIG_SPL_MAX_SIZE 0x1a000
@ -137,7 +151,18 @@
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
#define CONFIG_SPL_BSS_START_ADDR 0x80100000
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
#ifdef CONFIG_U_BOOT_HDR_SIZE
/*
* HDR would be appended at end of image and copied to DDR along
* with U-Boot image. Here u-boot max. size is 512K. So if binary
* size increases then increase this size in case of secure boot as
* it uses raw u-boot image instead of fit image.
*/
#define CONFIG_SYS_MONITOR_LEN (0x80000 + CONFIG_U_BOOT_HDR_SIZE)
#else
#define CONFIG_SYS_MONITOR_LEN 0x80000
#endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */
#endif
#ifdef CONFIG_QSPI_BOOT

25
include/configs/ls1043a_common.h
View File

@ -241,22 +241,37 @@
#define CONFIG_HWCONFIG
#define HWCONFIG_BUFFER_SIZE 128
#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
#define MTDPARTS_DEFAULT "mtdparts=spi0.0:1m(uboot)," \
"5m(kernel),1m(dtb),9m(file_system)"
#else
#define MTDPARTS_DEFAULT "mtdparts=60000000.nor:1m(nor_bank0_rcw)," \
"1m(nor_bank0_uboot),1m(nor_bank0_uboot_env)," \
"1m(nor_bank0_fman_uconde),40m(nor_bank0_fit)," \
"1m(nor_bank4_rcw),1m(nor_bank4_uboot)," \
"1m(nor_bank4_uboot_env),1m(nor_bank4_fman_ucode)," \
"40m(nor_bank4_fit);7e800000.flash:" \
"1m(nand_uboot),1m(nand_uboot_env)," \
"20m(nand_fit);spi0.0:1m(uboot)," \
"5m(kernel),1m(dtb),9m(file_system)"
#endif
/* Initial environment variables */
#define CONFIG_EXTRA_ENV_SETTINGS \
"hwconfig=fsl_ddr:bank_intlv=auto\0" \
"loadaddr=0x80100000\0" \
"kernel_addr=0x100000\0" \
"ramdisk_addr=0x800000\0" \
"ramdisk_size=0x2000000\0" \
"fdt_high=0xffffffffffffffff\0" \
"initrd_high=0xffffffffffffffff\0" \
"kernel_start=0x61100000\0" \
"kernel_load=0xa0000000\0" \
"kernel_size=0x2800000\0" \
"console=ttyAMA0,38400n8\0"
"console=ttyS0,115200\0" \
"mtdparts=" MTDPARTS_DEFAULT "\0"
#define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \
"earlycon=uart8250,mmio,0x21c0500"
"earlycon=uart8250,mmio,0x21c0500 " \
MTDPARTS_DEFAULT
#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
#define CONFIG_BOOTCOMMAND "sf probe && sf read $kernel_load " \
"e0000 f00000 && bootm $kernel_load"

20
include/linux/usb/xhci-fsl.h
View File

@ -51,22 +51,18 @@ struct fsl_xhci {
struct dwc3 *dwc3_reg;
};
#if defined(CONFIG_LS102XA)
#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS102XA_XHCI_USB1_ADDR
#if defined(CONFIG_LS102XA) || defined(CONFIG_LS1012A)
#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_XHCI_USB1_ADDR
#define CONFIG_SYS_FSL_XHCI_USB2_ADDR 0
#define CONFIG_SYS_FSL_XHCI_USB3_ADDR 0
#elif defined(CONFIG_LS2080A)
#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS2080A_XHCI_USB1_ADDR
#define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_LS2080A_XHCI_USB2_ADDR
#define CONFIG_SYS_FSL_XHCI_USB3_ADDR 0
#elif defined(CONFIG_LS1043A) || defined(CONFIG_LS1012A)
#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS1043A_XHCI_USB1_ADDR
#define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_LS1043A_XHCI_USB2_ADDR
#define CONFIG_SYS_FSL_XHCI_USB3_ADDR CONFIG_SYS_LS1043A_XHCI_USB3_ADDR
#elif defined(CONFIG_LS1012A)
#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS1043A_XHCI_USB1_ADDR
#define CONFIG_SYS_FSL_XHCI_USB2_ADDR 0
#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_XHCI_USB1_ADDR
#define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_XHCI_USB2_ADDR
#define CONFIG_SYS_FSL_XHCI_USB3_ADDR 0
#elif defined(CONFIG_LS1043A)
#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_XHCI_USB1_ADDR
#define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_XHCI_USB2_ADDR
#define CONFIG_SYS_FSL_XHCI_USB3_ADDR CONFIG_SYS_XHCI_USB3_ADDR
#endif
#define FSL_USB_XHCI_ADDR {CONFIG_SYS_FSL_XHCI_USB1_ADDR, \

2
include/usb/ehci-ci.h
View File

@ -160,7 +160,7 @@
#define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_MPC512x_USB1_ADDR
#define CONFIG_SYS_FSL_USB2_ADDR 0
#elif defined(CONFIG_LS102XA)
#define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_LS102XA_USB1_ADDR
#define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_EHCI_USB1_ADDR
#define CONFIG_SYS_FSL_USB2_ADDR 0
#endif