ram: rk3399: Order tsel variables
Order tsel* variable declarations and assignment in proper and meaningful way. No functionality change. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
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@ -159,41 +159,48 @@ static void set_ds_odt(const struct chan_info *chan,
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u32 *denali_phy = chan->publ->denali_phy;
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u32 tsel_idle_en, tsel_wr_en, tsel_rd_en;
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u32 tsel_idle_select_p, tsel_wr_select_dq_p, tsel_rd_select_p;
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u32 tsel_wr_select_ca_p, tsel_wr_select_ca_n;
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u32 tsel_idle_select_n, tsel_wr_select_dq_n, tsel_rd_select_n;
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u32 tsel_idle_select_p, tsel_rd_select_p;
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u32 tsel_idle_select_n, tsel_rd_select_n;
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u32 tsel_wr_select_dq_p, tsel_wr_select_ca_p;
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u32 tsel_wr_select_dq_n, tsel_wr_select_ca_n;
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u32 reg_value;
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if (params->base.dramtype == LPDDR4) {
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tsel_rd_select_p = PHY_DRV_ODT_HI_Z;
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tsel_wr_select_dq_p = PHY_DRV_ODT_40;
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tsel_wr_select_ca_p = PHY_DRV_ODT_40;
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tsel_idle_select_p = PHY_DRV_ODT_HI_Z;
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tsel_rd_select_n = PHY_DRV_ODT_240;
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tsel_wr_select_dq_n = PHY_DRV_ODT_40;
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tsel_wr_select_ca_n = PHY_DRV_ODT_40;
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tsel_idle_select_p = PHY_DRV_ODT_HI_Z;
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tsel_idle_select_n = PHY_DRV_ODT_240;
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tsel_wr_select_dq_p = PHY_DRV_ODT_40;
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tsel_wr_select_dq_n = PHY_DRV_ODT_40;
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tsel_wr_select_ca_p = PHY_DRV_ODT_40;
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tsel_wr_select_ca_n = PHY_DRV_ODT_40;
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} else if (params->base.dramtype == LPDDR3) {
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tsel_rd_select_p = PHY_DRV_ODT_240;
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tsel_wr_select_dq_p = PHY_DRV_ODT_34_3;
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tsel_wr_select_ca_p = PHY_DRV_ODT_48;
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tsel_idle_select_p = PHY_DRV_ODT_240;
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tsel_rd_select_n = PHY_DRV_ODT_HI_Z;
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tsel_wr_select_dq_n = PHY_DRV_ODT_34_3;
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tsel_wr_select_ca_n = PHY_DRV_ODT_48;
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tsel_idle_select_p = PHY_DRV_ODT_240;
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tsel_idle_select_n = PHY_DRV_ODT_HI_Z;
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tsel_wr_select_dq_p = PHY_DRV_ODT_34_3;
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tsel_wr_select_dq_n = PHY_DRV_ODT_34_3;
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tsel_wr_select_ca_p = PHY_DRV_ODT_48;
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tsel_wr_select_ca_n = PHY_DRV_ODT_48;
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} else {
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tsel_rd_select_p = PHY_DRV_ODT_240;
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tsel_wr_select_dq_p = PHY_DRV_ODT_34_3;
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tsel_wr_select_ca_p = PHY_DRV_ODT_34_3;
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tsel_idle_select_p = PHY_DRV_ODT_240;
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tsel_rd_select_n = PHY_DRV_ODT_240;
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tsel_wr_select_dq_n = PHY_DRV_ODT_34_3;
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tsel_wr_select_ca_n = PHY_DRV_ODT_34_3;
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tsel_idle_select_p = PHY_DRV_ODT_240;
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tsel_idle_select_n = PHY_DRV_ODT_240;
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tsel_wr_select_dq_p = PHY_DRV_ODT_34_3;
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tsel_wr_select_dq_n = PHY_DRV_ODT_34_3;
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tsel_wr_select_ca_p = PHY_DRV_ODT_34_3;
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tsel_wr_select_ca_n = PHY_DRV_ODT_34_3;
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}
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if (params->base.odt == 1)
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