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arm64: Disable TTBR1 maps in EL1

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When running in EL1, AArch64 knows two page table maps. One with addresses
that start with all zeros (TTBR0) and one with addresses that start with all
ones (TTBR1).

In U-Boot we don't care about the high up maps, so just disable them to ensure
we don't walk an invalid page table by accident.

Reported-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
This commit is contained in:
Alexander Graf 2016-03-04 01:09:46 +01:00 committed by Tom Rini
parent 0691484ac1
commit 9bb367a590
2 changed files with 2 additions and 1 deletions
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2
arch/arm/cpu/armv8/cache_v8.c
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@ -71,7 +71,7 @@ static u64 get_tcr(int el, u64 *pips, u64 *pva_bits)
}
if (el == 1) {
tcr = TCR_EL1_RSVD | (ips << 32);
tcr = TCR_EL1_RSVD | (ips << 32) | TCR_EPD1_DISABLE;
} else if (el == 2) {
tcr = TCR_EL2_RSVD | (ips << 16);
} else {

1
arch/arm/include/asm/armv8/mmu.h
View File

@ -154,6 +154,7 @@
#define TCR_TG0_4K (0 << 14)
#define TCR_TG0_64K (1 << 14)
#define TCR_TG0_16K (2 << 14)
#define TCR_EPD1_DISABLE (1 << 23)
#ifndef CONFIG_SYS_FULL_VA
#define TCR_EL1_IPS_BITS (UL(3) << 32) /* 42 bits physical address */