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arm: am33xx: Avoid writing into reserved DPLL divider

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DPLL DRR doesn't have an M4 divider. But the clock driver is trying
to configure M4 divider as 4(writing into a reserved register).
Fixing it by making M4 divider as -1.

Reported-by: Steve Kipisz <s-kipisz2@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
This commit is contained in:
Lokesh Vutla 2017-12-28 20:40:01 +05:30 committed by Tom Rini
parent 3a0e70f181
commit 9b88a4bda2
1 changed files with 6 additions and 6 deletions
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12
arch/arm/mach-omap2/am33xx/clock_am33xx.c
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@ -116,22 +116,22 @@ const struct dpll_params dpll_per_192MHz[NUM_CRYSTAL_FREQ] = {
const struct dpll_params dpll_ddr3_303MHz[NUM_CRYSTAL_FREQ] = {
{505, 15, 2, -1, -1, -1, -1}, /*19.2*/
{101, 3, 2, -1, -1, -1, -1}, /* 24 MHz */
{303, 24, 1, -1, 4, -1, -1}, /* 25 MHz */
{303, 12, 2, -1, 4, -1, -1} /* 26 MHz */
{303, 24, 1, -1, -1, -1, -1}, /* 25 MHz */
{303, 12, 2, -1, -1, -1, -1} /* 26 MHz */
};
const struct dpll_params dpll_ddr3_400MHz[NUM_CRYSTAL_FREQ] = {
{125, 5, 1, -1, -1, -1, -1}, /*19.2*/
{50, 2, 1, -1, -1, -1, -1}, /* 24 MHz */
{16, 0, 1, -1, 4, -1, -1}, /* 25 MHz */
{200, 12, 1, -1, 4, -1, -1} /* 26 MHz */
{16, 0, 1, -1, -1, -1, -1}, /* 25 MHz */
{200, 12, 1, -1, -1, -1, -1} /* 26 MHz */
};
const struct dpll_params dpll_ddr2_266MHz[NUM_CRYSTAL_FREQ] = {
{665, 47, 1, -1, -1, -1, -1}, /*19.2*/
{133, 11, 1, -1, -1, -1, -1}, /* 24 MHz */
{266, 24, 1, -1, 4, -1, -1}, /* 25 MHz */
{133, 12, 1, -1, 4, -1, -1} /* 26 MHz */
{266, 24, 1, -1, -1, -1, -1}, /* 25 MHz */
{133, 12, 1, -1, -1, -1, -1} /* 26 MHz */
};
__weak const struct dpll_params *get_dpll_mpu_params(void)