AT91 rework: fix TOP9000 files to build again
Fix EMK TOP9000 board to build again: - changes required due to ATMEL rework Signed-off-by: Reinhard Meyer <u-boot@emk-elektronik.de>
This commit is contained in:
Reinhard Meyer
Albert ARIBAUD
parent
8c6407fce3
commit
9b372b2c8e
@ -31,7 +31,8 @@
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#include <mmc.h>
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#include <i2c.h>
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#include <spi.h>
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#include <asm/arch/at91sam9260.h>
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#include <asm/io.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/at91sam9260_matrix.h>
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#include <asm/arch/at91sam9_smc.h>
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#include <asm/arch/at91_common.h>
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@ -39,35 +40,35 @@
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#include <asm/arch/at91_rstc.h>
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#include <asm/arch/at91_shdwn.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/io.h>
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#include <asm/arch/hardware.h>
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DECLARE_GLOBAL_DATA_PTR;
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#ifdef CONFIG_CMD_NAND
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static void nand_hw_init(void)
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{
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struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
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struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
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unsigned long csa;
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/* Enable CS3 */
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csa = at91_sys_read(AT91_MATRIX_EBICSA);
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at91_sys_write(AT91_MATRIX_EBICSA,
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csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
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/* Assign CS3 to NAND/SmartMedia Interface */
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csa = readl(&matrix->ebicsa);
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csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
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writel(csa, &matrix->ebicsa);
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/* Configure SMC CS3 for NAND/SmartMedia */
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at91_sys_write(AT91_SMC_SETUP(3),
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AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
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AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
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at91_sys_write(AT91_SMC_PULSE(3),
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AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
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AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
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at91_sys_write(AT91_SMC_CYCLE(3),
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AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
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at91_sys_write(AT91_SMC_MODE(3),
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AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
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AT91_SMC_EXNWMODE_DISABLE |
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AT91_SMC_DBW_8 |
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AT91_SMC_TDF_(2));
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writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
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AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
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&smc->cs[3].setup);
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writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
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AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
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&smc->cs[3].pulse);
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writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
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&smc->cs[3].cycle);
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writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
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AT91_SMC_MODE_EXNW_DISABLE |
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AT91_SMC_MODE_DBW_8 |
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AT91_SMC_MODE_TDF_CYCLE(2),
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&smc->cs[3].mode);
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/* Configure RDY/BSY */
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at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
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@ -80,8 +81,10 @@ static void nand_hw_init(void)
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#ifdef CONFIG_MACB
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static void macb_hw_init(void)
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{
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struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
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/* Enable EMAC clock */
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at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_EMAC);
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writel(1 << ATMEL_ID_EMAC0, &pmc->pcer);
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/* Initialize EMAC=MACB hardware */
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at91_macb_hw_init();
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@ -92,14 +95,16 @@ static void macb_hw_init(void)
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/* this is a weak define that we are overriding */
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int board_mmc_init(bd_t *bd)
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{
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struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
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/* Enable MCI clock */
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at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_MCI);
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writel(1 << ATMEL_ID_MCI, &pmc->pcer);
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/* Initialize MCI hardware */
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at91_mci_hw_init();
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/* This calls the atmel_mmc_init in gen_atmel_mci.c */
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return atmel_mci_init((void *)AT91_BASE_MCI);
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return atmel_mci_init((void *)ATMEL_BASE_MCI);
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}
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/* this is a weak define that we are overriding */
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@ -120,7 +125,8 @@ int board_mmc_getcd(u8 *cd, struct mmc *mmc)
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int board_early_init_f(void)
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{
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struct at91_shdwn *shdwn = (struct at91_shdwn *)AT91_SHDWN_BASE;
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struct at91_shdwn *shdwn = (struct at91_shdwn *)ATMEL_BASE_SHDWN;
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struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
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/*
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* make sure the board can be powered on by
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@ -130,9 +136,9 @@ int board_early_init_f(void)
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&shdwn->mr);
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/* Enable clocks for all PIOs */
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at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOA);
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at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOB);
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at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOC);
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writel((1 << ATMEL_ID_PIOA) | (1 << ATMEL_ID_PIOB) |
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(1 << ATMEL_ID_PIOC),
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&pmc->pcer);
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/* set SCL0 and SDA0 to open drain */
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at91_set_pio_output(I2C0_PORT, SCL0_PIN, 1);
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@ -159,7 +165,7 @@ int board_init(void)
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/* adress of boot parameters */
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gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
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at91_serial_hw_init();
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at91_seriald_hw_init();
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#ifdef CONFIG_CMD_NAND
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nand_hw_init();
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#endif
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@ -211,7 +217,7 @@ int board_eth_init(bd_t *bis)
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int num = 0;
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#ifdef CONFIG_MACB
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rc = macb_eth_initialize(0,
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(void *)AT91_EMAC_BASE,
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(void *)ATMEL_BASE_EMAC0,
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CONFIG_SYS_PHY_ID);
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if (!rc)
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num++;
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@ -38,6 +38,10 @@
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/* SoC must be defined first, before hardware.h is included */
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#define CONFIG_AT91SAM9XE
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#include <asm/hardware.h>
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/*
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* Warning: changing CONFIG_SYS_TEXT_BASE requires
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* adapting the initial boot program.
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@ -61,17 +65,11 @@
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#define CONFIG_CMD_CACHE
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/* ARM asynchronous clock */
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#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432 MHz xtal */
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#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
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#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* main clock xtal */
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#define CONFIG_SYS_HZ 1000
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/* SoC */
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#define CONFIG_ARM926EJS /* ARM926EJS Core */
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#define CONFIG_AT91FAMILY /* it's a member of AT91 */
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#define CONFIG_AT91SAM9260 /* Atmel AT91SAM9260 based SoC */
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#define CONFIG_AT91SAM9XE
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/* Misc CPU related */
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#define CONFIG_AT91_LEGACY
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#define CONFIG_ARCH_CPU_INIT
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#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
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#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
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@ -83,12 +81,14 @@
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#define CONFIG_AT91RESET_EXTRST /* assert external reset */
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/* general purpose I/O */
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#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */
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#define CONFIG_AT91_GPIO
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#define CONFIG_AT91_GPIO_PULLUP 1 /* keep pullups on peripheral pins */
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/* serial console */
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#define CONFIG_ATMEL_USART
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#define CONFIG_USART3 /* USART 3 is DBGU !!! */
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#define CONFIG_USART_BASE ATMEL_BASE_DBGU
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#define CONFIG_USART_ID ATMEL_ID_SYS
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 }
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@ -123,7 +123,7 @@
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* with u-boot commands
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*/
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# define CONFIG_AT91_EFLASH
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# define CONFIG_SYS_FLASH_BASE 0x200000
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# define CONFIG_SYS_FLASH_BASE ATMEL_BASE_FLASH
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# define CONFIG_SYS_MAX_FLASH_SECT 32
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# define CONFIG_SYS_MAX_FLASH_BANKS 1
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# define CONFIG_SYS_FLASH_PROTECTION
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@ -159,10 +159,10 @@
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* Initialized before u-boot gets started.
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*/
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#define CONFIG_NR_DRAM_BANKS 1
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#define CONFIG_SYS_SDRAM_BASE 0x20000000
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#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1
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#define CONFIG_SYS_SDRAM_SIZE 0x08000000
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#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
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#define CONFIG_SYS_MEMTEST_END 0x21e00000
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#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x01e00000)
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#define CONFIG_SYS_LOAD_ADDR \
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(CONFIG_SYS_SDRAM_BASE + 0x01000000)
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/*
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@ -171,7 +171,7 @@
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* that address while providing maximum stack area below.
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*/
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#define CONFIG_SYS_INIT_SP_ADDR \
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(0x00300000 + 0x4000 - GENERATED_GBL_DATA_SIZE)
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(ATMEL_BASE_SRAM + 0x4000 - GENERATED_GBL_DATA_SIZE)
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/*
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* NAND flash: 256 MB (optional)
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@ -184,7 +184,7 @@
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*/
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#define CONFIG_NAND_ATMEL
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_SYS_NAND_BASE 0x40000000
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#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
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#define CONFIG_SYS_NAND_DBW_8
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#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
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#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
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@ -197,7 +197,7 @@
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#define CONFIG_USB_OHCI_NEW
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#define CONFIG_DOS_PARTITION
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#define CONFIG_SYS_USB_OHCI_CPU_INIT
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#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000
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#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_UHP_BASE
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#define CONFIG_SYS_USB_OHCI_SLOT_NAME "top9000"
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#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
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#define CONFIG_USB_STORAGE
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