Patches Part 1 by Jon Loeliger, 11 May 2004:
Dynamically handle REV1 and REV2 MPC85xx parts. (Jon Loeliger, 10-May-2004). New consistent memory map and Local Access Window across MPC85xx line. New CCSRBAR at 0xE000_0000 now. Add RAPID I/O memory map. New memory map in README.MPC85xxads (Kumar Gala, 10-May-2004) Better board and CPU identification on MPC85xx boards at boot. (Jon Loeliger, 10-May-2004) SDRAM clock control fixes on MPC8540ADS & MPC8560 boards. Some configuration options for MPC8540ADS & MPC8560ADS cleaned up. (Jim Robertson, 10-May-2004) Rewrite of the MPC85xx Three Speed Ethernet Controller (TSEC) driver. Supports multiple PHYs. (Andy Fleming, 10-May-2004) Some README.MPC85xxads updates. (Kumar Gala, 10-May-2004) Copyright updates for "Freescale" (Andy Fleming, 10-May-2004)
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21
CHANGELOG
21
CHANGELOG
@ -2,6 +2,27 @@
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Changes since U-Boot 1.1.1:
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======================================================================
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* Patches Part 1 by Jon Loeliger, 11 May 2004:
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Dynamically handle REV1 and REV2 MPC85xx parts.
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(Jon Loeliger, 10-May-2004).
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New consistent memory map and Local Access Window across MPC85xx line.
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New CCSRBAR at 0xE000_0000 now.
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Add RAPID I/O memory map.
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New memory map in README.MPC85xxads
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(Kumar Gala, 10-May-2004)
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Better board and CPU identification on MPC85xx boards at boot.
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(Jon Loeliger, 10-May-2004)
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SDRAM clock control fixes on MPC8540ADS & MPC8560 boards.
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Some configuration options for MPC8540ADS & MPC8560ADS cleaned up.
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(Jim Robertson, 10-May-2004)
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Rewrite of the MPC85xx Three Speed Ethernet Controller (TSEC) driver.
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Supports multiple PHYs.
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(Andy Fleming, 10-May-2004)
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Some README.MPC85xxads updates.
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(Kumar Gala, 10-May-2004)
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Copyright updates for "Freescale"
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(Andy Fleming, 10-May-2004)
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* Patch by Stephen Williams, 11 May 2004:
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Add flash support for ST M29W040B
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Reduce JSE specific flash.c to remove dead code.
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@ -1,3 +1,4 @@
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# Copyright 2004 Freescale Semiconductor.
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# Modified by Xianghua Xiao, X.Xiao@motorola.com
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# (C) Copyright 2002,Motorola Inc.
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#
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@ -1,4 +1,5 @@
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/*
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* Copyright 2004 Freescale Semiconductor.
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* Copyright (C) 2002,2003, Motorola Inc.
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* Xianghua Xiao <X.Xiao@motorola.com>
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*
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@ -136,43 +137,58 @@ tlb1_entry:
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#endif
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entry_end
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/* LAW(Local Access Window) configuration:
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* 0000_0000-0800_0000: DDR(128M) -or- larger
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* f000_0000-f3ff_ffff: PCI(256M)
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* f400_0000-f7ff_ffff: RapidIO(128M)
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* f800_0000-ffff_ffff: localbus(128M)
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* f800_0000-fbff_ffff: LBC SDRAM(64M)
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* fc00_0000-fdef_ffff: LBC BCSR,RTC,etc(31M)
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* fdf0_0000-fdff_ffff: CCSRBAR(1M)
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* fe00_0000-ffff_ffff: Flash(32M)
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* Note: CCSRBAR and L2-as-SRAM don't need configure Local Access
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* Window.
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/*
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* LAW(Local Access Window) configuration:
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*
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* 0x0000_0000 0x7fff_ffff DDR 2G
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* 0x8000_0000 0x9fff_ffff PCI MEM 512M
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* 0xe000_0000 0xe000_ffff CCSR 1M
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* 0xe200_0000 0xe2ff_ffff PCI IO 16M
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* 0xf000_0000 0xf7ff_ffff SDRAM 128M
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* 0xf800_0000 0xf80f_ffff BCSR 1M
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* 0xff00_0000 0xffff_ffff FLASH (boot bank) 16M
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*
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* Note: CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
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* Note: If flash is 8M at default position(last 8M),no LAW needed.
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*/
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#if !defined(CONFIG_SPD_EEPROM)
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#define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff)
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#define LAWAR0 (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M))
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#define LAWAR0 (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M))
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#else
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#define LAWBAR0 0
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#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
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#endif
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#define LAWBAR1 ((CFG_PCI_MEM_BASE>>12) & 0xfffff)
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#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_256M))
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#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_512M))
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/*
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* This is not so much the SDRAM map as it is the whole localbus map.
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*/
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#if !defined(CONFIG_RAM_AS_FLASH)
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#define LAWBAR2 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
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#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_128M))
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#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M))
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#else
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#define LAWBAR2 0
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#define LAWAR2 ((LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
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#endif
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#define LAWBAR3 ((CFG_PCI_IO_BASE>>12) & 0xfffff)
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#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_16M))
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/*
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* Rapid IO at 0xc000_0000 for 512 M
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*/
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#define LAWBAR4 ((CFG_RAPID_IO_BASE>>12) & 0xfffff)
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#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_512M))
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.section .bootpg, "ax"
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.globl law_entry
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law_entry:
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entry_start
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.long 0x03
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.long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2
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.long 0x05
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.long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3
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.long LAWBAR4,LAWAR4
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entry_end
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@ -1,4 +1,4 @@
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/*
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/*
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* (C) Copyright 2002,2003, Motorola Inc.
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* Xianghua Xiao, (X.Xiao@motorola.com)
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*
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@ -33,6 +33,13 @@ extern long int spd_sdram (void);
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long int fixed_sdram (void);
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#if defined(CONFIG_DDR_ECC)
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void dma_init(void);
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uint dma_check(void);
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int dma_xfer(void *dest, uint count, void *src);
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#endif
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/* MPC8540ADS Board Status & Control Registers */
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#if 0
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typedef struct bscr_ {
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@ -60,24 +67,11 @@ int board_early_init_f (void)
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int checkboard (void)
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{
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sys_info_t sysinfo;
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get_sys_info (&sysinfo);
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printf ("Board: Motorola MPC8540ADS Board\n");
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printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
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printf ("\tCCB: %lu MHz\n", sysinfo.freqSystemBus / 1000000);
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printf ("\tDDR: %lu MHz\n", sysinfo.freqSystemBus / 2000000);
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if((CFG_LBC_LCRR & 0x0f) == 2 || (CFG_LBC_LCRR & 0x0f) == 4 \
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|| (CFG_LBC_LCRR & 0x0f) == 8) {
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printf ("\tLBC: %lu MHz\n", sysinfo.freqSystemBus / 1000000 /(CFG_LBC_LCRR & 0x0f));
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} else {
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printf("\tLBC: unknown\n");
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}
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printf("L1 D-cache 32KB, L1 I-cache 32KB enabled.\n");
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return (0);
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puts("Board: ADS\n");
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return 0;
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}
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long int initdram (int board_type)
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{
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long dram_size = 0;
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@ -91,8 +85,9 @@ long int initdram (int board_type)
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#if !defined(CONFIG_RAM_AS_FLASH) || defined(CONFIG_DDR_DLL)
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volatile ccsr_gur_t *gur= &immap->im_gur;
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#endif
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#if defined(CONFIG_DDR_DLL)
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uint temp_ddrdll = 0;
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uint temp_ddrdll = 0;
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/* Work around to stabilize DDR DLL */
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temp_ddrdll = gur->ddrdllcr;
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@ -112,9 +107,16 @@ long int initdram (int board_type)
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if(sysinfo.freqSystemBus/(CFG_LBC_LCRR & 0x0f) < 66000000) {
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lbc->lcrr = (CFG_LBC_LCRR & 0x0fffffff)| 0x80000000;
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} else {
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#if defined(CONFIG_MPC85xx_REV1) /* need change CLKDIV before enable DLL */
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lbc->lcrr = 0x10000004; /* default CLKDIV is 8, change it to 4 temporarily */
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#endif
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uint pvr = get_pvr();
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if (pvr == PVR_85xx_REV1) {
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/*
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* Need change CLKDIV before enable DLL.
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* Default CLKDIV is 8, change it to 4
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* temporarily.
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*/
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lbc->lcrr = 0x10000004;
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}
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lbc->lcrr = CFG_LBC_LCRR & 0x7fffffff;
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udelay(200);
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temp_lbcdll = gur->lbcdllcr;
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@ -1,3 +1,4 @@
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# Copyright 2004 Freescale Semiconductor.
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# Modified by Xianghua Xiao, X.Xiao@motorola.com
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# (C) Copyright 2002,2003 Motorola Inc.
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#
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@ -1,4 +1,5 @@
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/*
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* Copyright 2004 Freescale Semiconductor.
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* Copyright (C) 2002,2003, Motorola Inc.
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* Xianghua Xiao <X.Xiao@motorola.com>
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*
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@ -136,43 +137,58 @@ tlb1_entry:
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#endif
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entry_end
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/* LAW(Local Access Window) configuration:
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* 0000_0000-0800_0000: DDR(128M) -or- larger
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* f000_0000-f3ff_ffff: PCI(256M)
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* f400_0000-f7ff_ffff: RapidIO(128M)
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* f800_0000-ffff_ffff: localbus(128M)
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* f800_0000-fbff_ffff: LBC SDRAM(64M)
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* fc00_0000-fdef_ffff: LBC BCSR,RTC,etc(31M)
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* fdf0_0000-fdff_ffff: CCSRBAR(1M)
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* fe00_0000-ffff_ffff: Flash(32M)
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* Note: CCSRBAR and L2-as-SRAM don't need configure Local Access
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* Window.
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/*
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* LAW(Local Access Window) configuration:
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*
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* 0x0000_0000 0x7fff_ffff DDR 2G
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* 0x8000_0000 0x9fff_ffff PCI MEM 512M
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* 0xe000_0000 0xe000_ffff CCSR 1M
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* 0xe200_0000 0xe2ff_ffff PCI IO 16M
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* 0xf000_0000 0xf7ff_ffff SDRAM 128M
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* 0xf800_0000 0xf80f_ffff BCSR 1M
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* 0xff00_0000 0xffff_ffff FLASH (boot bank) 16M
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*
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* Note: CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
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* Note: If flash is 8M at default position(last 8M),no LAW needed.
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*/
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#if !defined(CONFIG_SPD_EEPROM)
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#define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff)
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#define LAWAR0 (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M))
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#define LAWAR0 (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M))
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#else
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#define LAWBAR0 0
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#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
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#endif
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#define LAWBAR1 ((CFG_PCI_MEM_BASE>>12) & 0xfffff)
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#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_256M))
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#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_512M))
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/*
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* This is not so much the SDRAM map as it is the whole localbus map.
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*/
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#if !defined(CONFIG_RAM_AS_FLASH)
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#define LAWBAR2 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
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#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_128M))
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#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M))
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#else
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#define LAWBAR2 0
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#define LAWAR2 ((LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
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#endif
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#define LAWBAR3 ((CFG_PCI_IO_BASE>>12) & 0xfffff)
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#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_16M))
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/*
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* Rapid IO at 0xc000_0000 for 512 M
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*/
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#define LAWBAR4 ((CFG_RAPID_IO_BASE>>12) & 0xfffff)
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#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_512M))
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.section .bootpg, "ax"
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.globl law_entry
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.globl law_entry
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law_entry:
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entry_start
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.long 0x03
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.long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2
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.long 0x05
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.long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3
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.long LAWBAR4,LAWAR4
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entry_end
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@ -1,4 +1,5 @@
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/*
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* Copyright 2004 Freescale Semiconductor.
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* (C) Copyright 2003,Motorola Inc.
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* Xianghua Xiao, (X.Xiao@motorola.com)
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*
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@ -236,26 +237,11 @@ void reset_phy (void)
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#endif /* CONFIG_MII */
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}
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int checkboard (void)
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{
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sys_info_t sysinfo;
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get_sys_info (&sysinfo);
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printf ("Board: Motorola MPC8560ADS Board\n");
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printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
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printf ("\tCCB: %lu MHz\n", sysinfo.freqSystemBus / 1000000);
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printf ("\tDDR: %lu MHz\n", sysinfo.freqSystemBus / 2000000);
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if((CFG_LBC_LCRR & 0x0f) == 2 || (CFG_LBC_LCRR & 0x0f) == 4 \
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|| (CFG_LBC_LCRR & 0x0f) == 8) {
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printf ("\tLBC: %lu MHz\n", sysinfo.freqSystemBus / 1000000 /(CFG_LBC_LCRR & 0x0f));
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} else {
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printf("\tLBC: unknown\n");
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}
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printf("\tCPM: %lu Mhz\n", sysinfo.freqSystemBus / 1000000);
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printf("L1 D-cache 32KB, L1 I-cache 32KB enabled.\n");
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return (0);
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puts("Board: ADS\n");
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return 0;
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}
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@ -272,6 +258,7 @@ long int initdram (int board_type)
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#if !defined(CONFIG_RAM_AS_FLASH) || defined(CONFIG_DDR_DLL)
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volatile ccsr_gur_t *gur= &immap->im_gur;
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#endif
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#if defined(CONFIG_DDR_DLL)
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uint temp_ddrdll = 0;
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@ -293,9 +280,16 @@ long int initdram (int board_type)
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if(sysinfo.freqSystemBus/(CFG_LBC_LCRR & 0x0f) < 66000000) {
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lbc->lcrr = (CFG_LBC_LCRR & 0x0fffffff)| 0x80000000;
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} else {
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#if defined(CONFIG_MPC85xx_REV1) /* need change CLKDIV before enable DLL */
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lbc->lcrr = 0x10000004; /* default CLKDIV is 8, change it to 4 temporarily */
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#endif
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uint pvr = get_pvr();
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if (pvr == PVR_85xx_REV1) {
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/*
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* Need change CLKDIV before enable DLL.
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* Default CLKDIV is 8, change it to 4
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* temporarily.
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*/
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lbc->lcrr = 0x10000004;
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}
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lbc->lcrr = CFG_LBC_LCRR & 0x7fffffff;
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udelay(200);
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temp_lbcdll = gur->lbcdllcr;
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@ -55,11 +55,13 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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print_num ("flashoffset", bd->bi_flashoffset );
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print_num ("sramstart", bd->bi_sramstart );
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print_num ("sramsize", bd->bi_sramsize );
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#if defined(CONFIG_5xx) || defined(CONFIG_8xx) || defined(CONFIG_8260) || defined(CONFIG_E500)
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#if defined(CONFIG_5xx) || defined(CONFIG_8xx) || \
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defined(CONFIG_8260) || defined(CONFIG_E500)
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print_num ("immr_base", bd->bi_immr_base );
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#endif
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print_num ("bootflags", bd->bi_bootflags );
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#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_405EP) || defined(CONFIG_XILINX_ML300)
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#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
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defined(CONFIG_405EP) || defined(CONFIG_XILINX_ML300)
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print_str ("procfreq", strmhz(buf, bd->bi_procfreq));
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print_str ("plb_busfreq", strmhz(buf, bd->bi_plb_busfreq));
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#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || defined(CONFIG_XILINX_ML300)
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@ -81,14 +83,15 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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for (i=0; i<6; ++i) {
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printf ("%c%02X", i ? ':' : ' ', bd->bi_enetaddr[i]);
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}
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#if (defined CONFIG_PN62) || (defined CONFIG_PPCHAMELEONEVB) \
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|| (defined CONFIG_MPC8540ADS) || (defined CONFIG_MPC8560ADS)
|
||||
#if (defined CONFIG_PN62) || (defined CONFIG_PPCHAMELEONEVB) || \
|
||||
(defined CONFIG_MPC8540ADS) || (defined CONFIG_MPC8560ADS) || \
|
||||
(defined CONFIG_MPC8555CDS)
|
||||
puts ("\neth1addr =");
|
||||
for (i=0; i<6; ++i) {
|
||||
printf ("%c%02X", i ? ':' : ' ', bd->bi_enet1addr[i]);
|
||||
}
|
||||
#endif /* CONFIG_PN62 */
|
||||
#if defined(CONFIG_MPC8540ADS) || defined(CONFIG_MPC8560ADS)
|
||||
#if defined(CONFIG_MPC8540ADS) || defined(CONFIG_MPC8560ADS) || defined(CONFIG_MPC8555CDS)
|
||||
puts ("\neth2addr =");
|
||||
for (i=0; i<6; ++i) {
|
||||
printf ("%c%02X", i ? ':' : ' ', bd->bi_enet2addr[i]);
|
||||
|
||||
@ -1,4 +1,5 @@
|
||||
/*
|
||||
* Copyright 2004 Freescale Semiconductor.
|
||||
* (C) Copyright 2002, 2003 Motorola Inc.
|
||||
* Xianghua Xiao (X.Xiao@motorola.com)
|
||||
*
|
||||
@ -33,17 +34,87 @@
|
||||
|
||||
int checkcpu (void)
|
||||
{
|
||||
uint pir = get_pir();
|
||||
uint pvr = get_pvr();
|
||||
sys_info_t sysinfo;
|
||||
uint lcrr; /* local bus clock ratio register */
|
||||
uint clkdiv; /* clock divider portion of lcrr */
|
||||
uint pvr, svr;
|
||||
uint ver;
|
||||
uint major, minor;
|
||||
|
||||
printf("Motorola PowerPC ProcessorID=%08x Rev. ",pir);
|
||||
switch(pvr) {
|
||||
puts("Freescale PowerPC\n");
|
||||
|
||||
pvr = get_pvr();
|
||||
ver = PVR_VER(pvr);
|
||||
major = PVR_MAJ(pvr);
|
||||
minor = PVR_MIN(pvr);
|
||||
|
||||
printf(" Core: ");
|
||||
switch (ver) {
|
||||
case PVR_VER(PVR_85xx):
|
||||
puts("E500");
|
||||
break;
|
||||
default:
|
||||
printf("PVR=%08x", pvr);
|
||||
puts("Unknown");
|
||||
break;
|
||||
}
|
||||
printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
|
||||
|
||||
svr = get_svr();
|
||||
ver = SVR_VER(svr);
|
||||
major = SVR_MAJ(svr);
|
||||
minor = SVR_MIN(svr);
|
||||
|
||||
puts(" System: ");
|
||||
switch (ver) {
|
||||
case SVR_8540:
|
||||
puts("8540");
|
||||
break;
|
||||
case SVR_8541:
|
||||
puts("8541");
|
||||
break;
|
||||
case SVR_8555:
|
||||
puts("8555");
|
||||
break;
|
||||
case SVR_8560:
|
||||
puts("8560");
|
||||
break;
|
||||
default:
|
||||
puts("Unknown");
|
||||
break;
|
||||
}
|
||||
printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
|
||||
|
||||
printf("\n");
|
||||
get_sys_info(&sysinfo);
|
||||
|
||||
puts(" Clocks: ");
|
||||
printf("CPU:%4lu MHz, ", sysinfo.freqProcessor / 1000000);
|
||||
printf("CCB:%4lu MHz, ", sysinfo.freqSystemBus / 1000000);
|
||||
printf("DDR:%4lu MHz, ", sysinfo.freqSystemBus / 2000000);
|
||||
|
||||
#if defined(CFG_LBC_LCRR)
|
||||
lcrr = CFG_LBC_LCRR;
|
||||
#else
|
||||
{
|
||||
volatile immap_t *immap = (immap_t *)CFG_IMMR;
|
||||
volatile ccsr_lbc_t *lbc= &immap->im_lbc;
|
||||
|
||||
lcrr = lbc->lcrr;
|
||||
}
|
||||
#endif
|
||||
clkdiv = lcrr & 0x0f;
|
||||
if (clkdiv == 2 || clkdiv == 4 || clkdiv == 8) {
|
||||
printf("LBC:%4lu MHz\n",
|
||||
sysinfo.freqSystemBus / 1000000 / clkdiv);
|
||||
} else {
|
||||
printf(" LBC: unknown (lcrr: 0x%08x)\n", lcrr);
|
||||
}
|
||||
|
||||
if (ver == SVR_8560) {
|
||||
printf(" CPM: %lu Mhz\n",
|
||||
sysinfo.freqSystemBus / 1000000);
|
||||
}
|
||||
|
||||
puts(" L1 D-cache 32KB, L1 I-cache 32KB enabled.\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
@ -57,8 +128,12 @@ int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
|
||||
* Initiate hard reset in debug control register DBCR0
|
||||
* Make sure MSR[DE] = 1
|
||||
*/
|
||||
__asm__ __volatile__("lis 3, 0x7000" ::: "r3");
|
||||
mtspr(DBCR0,3);
|
||||
unsigned long val;
|
||||
|
||||
val = mfspr(DBCR0);
|
||||
val |= 0x70000000;
|
||||
mtspr(DBCR0,val);
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
|
||||
@ -1,4 +1,5 @@
|
||||
/*
|
||||
* Copyright 2004 Freescale Semiconductor.
|
||||
* (C) Copyright 2003 Motorola Inc.
|
||||
* Xianghua Xiao (X.Xiao@motorola.com)
|
||||
*
|
||||
@ -29,15 +30,7 @@
|
||||
|
||||
#ifdef CONFIG_SPD_EEPROM
|
||||
|
||||
#undef DEBUG
|
||||
|
||||
#if defined(DEBUG)
|
||||
#define DEB(x) x
|
||||
#else
|
||||
#define DEB(x)
|
||||
#endif
|
||||
|
||||
#define ns2clk(ns) ((ns) / (2000000000 /get_bus_freq(0) + 1))
|
||||
#define ns2clk(ns) ((ns) / (2000000000 /get_bus_freq(0) + 1) + 1)
|
||||
|
||||
long int spd_sdram(void) {
|
||||
volatile immap_t *immap = (immap_t *)CFG_IMMR;
|
||||
@ -61,64 +54,62 @@ long int spd_sdram(void) {
|
||||
|
||||
ddr->cs0_bnds = ((spd.row_dens>>2) - 1);
|
||||
ddr->cs0_config = ( 1<<31 | (spd.nrow_addr-12)<<8 | (spd.ncol_addr-8) );
|
||||
DEB(printf("\n"));
|
||||
DEB(printf("cs0_bnds = 0x%08x\n",ddr->cs0_bnds));
|
||||
DEB(printf("cs0_config = 0x%08x\n",ddr->cs0_config));
|
||||
debug ("\n");
|
||||
debug ("cs0_bnds = 0x%08x\n",ddr->cs0_bnds);
|
||||
debug ("cs0_config = 0x%08x\n",ddr->cs0_config);
|
||||
if ( spd.nrows == 2 ) {
|
||||
ddr->cs1_bnds = ((spd.row_dens<<14) | ((spd.row_dens>>1) - 1));
|
||||
ddr->cs1_config = ( 1<<31 | (spd.nrow_addr-12)<<8 | (spd.ncol_addr-8) );
|
||||
DEB(printf("cs1_bnds = 0x%08x\n",ddr->cs1_bnds));
|
||||
DEB(printf("cs1_config = 0x%08x\n",ddr->cs1_config));
|
||||
debug ("cs1_bnds = 0x%08x\n",ddr->cs1_bnds);
|
||||
debug ("cs1_config = 0x%08x\n",ddr->cs1_config);
|
||||
}
|
||||
|
||||
memsize = spd.nrows * (4 * spd.row_dens);
|
||||
if( spd.mem_type == 0x07 ) {
|
||||
printf("DDR module detected, total size:%dMB.\n",memsize);
|
||||
} else {
|
||||
if( spd.mem_type != 0x07 ) {
|
||||
printf("No DDR module found!\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
switch(memsize) {
|
||||
case 16:
|
||||
tmp = 7; /* TLB size */
|
||||
tmp1 = 1; /* TLB entry number */
|
||||
tmp2 = 23; /* Local Access Window size */
|
||||
break;
|
||||
case 32:
|
||||
tmp = 7;
|
||||
tmp1 = 2;
|
||||
tmp2 = 24;
|
||||
break;
|
||||
case 64:
|
||||
tmp = 8;
|
||||
tmp1 = 1;
|
||||
tmp2 = 25;
|
||||
break;
|
||||
case 128:
|
||||
tmp = 8;
|
||||
tmp1 = 2;
|
||||
tmp2 = 26;
|
||||
break;
|
||||
case 256:
|
||||
tmp = 9;
|
||||
tmp1 = 1;
|
||||
tmp2 = 27;
|
||||
break;
|
||||
case 512:
|
||||
tmp = 9;
|
||||
tmp1 = 2;
|
||||
tmp2 = 28;
|
||||
break;
|
||||
case 1024:
|
||||
tmp = 10;
|
||||
tmp1 = 1;
|
||||
tmp2 = 29;
|
||||
break;
|
||||
default:
|
||||
printf("DDR:we only added support 16M,32M,64M,128M,256M,512M and 1G DDR I.\n");
|
||||
return 0;
|
||||
break;
|
||||
switch (memsize) {
|
||||
case 16:
|
||||
tmp = 7; /* TLB size */
|
||||
tmp1 = 1; /* TLB entry number */
|
||||
tmp2 = 23; /* Local Access Window size */
|
||||
break;
|
||||
case 32:
|
||||
tmp = 7;
|
||||
tmp1 = 2;
|
||||
tmp2 = 24;
|
||||
break;
|
||||
case 64:
|
||||
tmp = 8;
|
||||
tmp1 = 1;
|
||||
tmp2 = 25;
|
||||
break;
|
||||
case 128:
|
||||
tmp = 8;
|
||||
tmp1 = 2;
|
||||
tmp2 = 26;
|
||||
break;
|
||||
case 256:
|
||||
tmp = 9;
|
||||
tmp1 = 1;
|
||||
tmp2 = 27;
|
||||
break;
|
||||
case 512:
|
||||
tmp = 9;
|
||||
tmp1 = 2;
|
||||
tmp2 = 28;
|
||||
break;
|
||||
case 1024:
|
||||
tmp = 10;
|
||||
tmp1 = 1;
|
||||
tmp2 = 29;
|
||||
break;
|
||||
default:
|
||||
printf ("DDR:we only added support 16M,32M,64M,128M,256M,512M and 1G DDR I.\n");
|
||||
return 0;
|
||||
break;
|
||||
}
|
||||
|
||||
/* configure DDR TLB to TLB1 Entry 4,5 */
|
||||
@ -127,12 +118,12 @@ long int spd_sdram(void) {
|
||||
mtspr(MAS2, TLB1_MAS2(((CFG_DDR_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,0,0,0));
|
||||
mtspr(MAS3, TLB1_MAS3(((CFG_DDR_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1));
|
||||
asm volatile("isync;msync;tlbwe;isync");
|
||||
DEB(printf("DDR:MAS0=0x%08x\n",TLB1_MAS0(1,4,0)));
|
||||
DEB(printf("DDR:MAS1=0x%08x\n",TLB1_MAS1(1,1,0,0,tmp)));
|
||||
DEB(printf("DDR:MAS2=0x%08x\n",TLB1_MAS2(((CFG_DDR_SDRAM_BASE>>12) \
|
||||
& 0xfffff),0,0,0,0,0,0,0,0)));
|
||||
DEB(printf("DDR:MAS3=0x%08x\n",TLB1_MAS3(((CFG_DDR_SDRAM_BASE>>12) \
|
||||
& 0xfffff),0,0,0,0,0,1,0,1,0,1)));
|
||||
debug ("DDR:MAS0=0x%08x\n",TLB1_MAS0(1,4,0));
|
||||
debug ("DDR:MAS1=0x%08x\n",TLB1_MAS1(1,1,0,0,tmp));
|
||||
debug ("DDR:MAS2=0x%08x\n",TLB1_MAS2(((CFG_DDR_SDRAM_BASE>>12) \
|
||||
& 0xfffff),0,0,0,0,0,0,0,0));
|
||||
debug ("DDR:MAS3=0x%08x\n",TLB1_MAS3(((CFG_DDR_SDRAM_BASE>>12) \
|
||||
& 0xfffff),0,0,0,0,0,1,0,1,0,1));
|
||||
|
||||
if(tmp1 == 2) {
|
||||
mtspr(MAS0, TLB1_MAS0(1,5,0));
|
||||
@ -142,28 +133,28 @@ long int spd_sdram(void) {
|
||||
mtspr(MAS3, TLB1_MAS3((((CFG_DDR_SDRAM_BASE+(memsize*1024*1024)/2)>>12) \
|
||||
& 0xfffff),0,0,0,0,0,1,0,1,0,1));
|
||||
asm volatile("isync;msync;tlbwe;isync");
|
||||
DEB(printf("DDR:MAS0=0x%08x\n",TLB1_MAS0(1,5,0)));
|
||||
DEB(printf("DDR:MAS1=0x%08x\n",TLB1_MAS1(1,1,0,0,tmp)));
|
||||
DEB(printf("DDR:MAS2=0x%08x\n",TLB1_MAS2((((CFG_DDR_SDRAM_BASE \
|
||||
+(memsize*1024*1024)/2)>>12) & 0xfffff),0,0,0,0,0,0,0,0)));
|
||||
DEB(printf("DDR:MAS3=0x%08x\n",TLB1_MAS3((((CFG_DDR_SDRAM_BASE \
|
||||
+(memsize*1024*1024)/2)>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)));
|
||||
debug ("DDR:MAS0=0x%08x\n",TLB1_MAS0(1,5,0));
|
||||
debug ("DDR:MAS1=0x%08x\n",TLB1_MAS1(1,1,0,0,tmp));
|
||||
debug ("DDR:MAS2=0x%08x\n",TLB1_MAS2((((CFG_DDR_SDRAM_BASE \
|
||||
+(memsize*1024*1024)/2)>>12) & 0xfffff),0,0,0,0,0,0,0,0));
|
||||
debug ("DDR:MAS3=0x%08x\n",TLB1_MAS3((((CFG_DDR_SDRAM_BASE \
|
||||
+(memsize*1024*1024)/2)>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1));
|
||||
}
|
||||
|
||||
#if defined(CONFIG_RAM_AS_FLASH)
|
||||
ecm->lawbar2 = ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff);
|
||||
ecm->lawar2 = (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & tmp2));
|
||||
DEB(printf("DDR:LAWBAR2=0x%08x\n",ecm->lawbar2));
|
||||
DEB(printf("DDR:LARAR2=0x%08x\n",ecm->lawar2));
|
||||
debug ("DDR:LAWBAR2=0x%08x\n",ecm->lawbar2);
|
||||
debug ("DDR:LARAR2=0x%08x\n",ecm->lawar2);
|
||||
#else
|
||||
ecm->lawbar1 = ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff);
|
||||
ecm->lawar1 = (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & tmp2));
|
||||
DEB(printf("DDR:LAWBAR1=0x%08x\n",ecm->lawbar1));
|
||||
DEB(printf("DDR:LARAR1=0x%08x\n",ecm->lawar1));
|
||||
debug ("DDR:LAWBAR1=0x%08x\n",ecm->lawbar1);
|
||||
debug ("DDR:LARAR1=0x%08x\n",ecm->lawar1);
|
||||
#endif
|
||||
|
||||
tmp = 20000/(((spd.clk_cycle & 0xF0) >> 4) * 10 + (spd.clk_cycle & 0x0f));
|
||||
DEB(printf("DDR:Module maximum data rate is: %dMhz\n",tmp));
|
||||
debug ("DDR:Module maximum data rate is: %dMhz\n",tmp);
|
||||
|
||||
/* find the largest CAS */
|
||||
if(spd.cas_lat & 0x40) {
|
||||
@ -186,13 +177,16 @@ long int spd_sdram(void) {
|
||||
}
|
||||
|
||||
tmp1 = get_bus_freq(0)/1000000;
|
||||
if(tmp1<230 && tmp1>=90 && tmp>=230) { /* 90~230 range, treated as DDR 200 */
|
||||
if(tmp1<230 && tmp1>=90 && tmp>=230) {
|
||||
/* 90~230 range, treated as DDR 200 */
|
||||
if(spd.clk_cycle3 == 0xa0) caslat -= 2;
|
||||
else if(spd.clk_cycle2 == 0xa0) caslat--;
|
||||
} else if(tmp1<280 && tmp1>=230 && tmp>=280) { /* 230-280 range, treated as DDR 266 */
|
||||
} else if(tmp1<280 && tmp1>=230 && tmp>=280) {
|
||||
/* 230-280 range, treated as DDR 266 */
|
||||
if(spd.clk_cycle3 == 0x75) caslat -= 2;
|
||||
else if(spd.clk_cycle2 == 0x75) caslat--;
|
||||
} else if(tmp1<350 && tmp1>=280 && tmp>=350) { /* 280~350 range, treated as DDR 333 */
|
||||
} else if(tmp1<350 && tmp1>=280 && tmp>=350) {
|
||||
/* 280~350 range, treated as DDR 333 */
|
||||
if(spd.clk_cycle3 == 0x60) caslat -= 2;
|
||||
else if(spd.clk_cycle2 == 0x60) caslat--;
|
||||
} else if(tmp1<90 || tmp1 >=350) { /* DDR rate out-of-range */
|
||||
@ -200,9 +194,10 @@ long int spd_sdram(void) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* note: caslat must also be programmed into ddr->sdram_mode register */
|
||||
/* note: WRREC(Twr) and WRTORD(Twtr) are not in SPD,use conservative value here */
|
||||
#if 1
|
||||
/* note: caslat must also be programmed into ddr->sdram_mode
|
||||
register */
|
||||
/* note: WRREC(Twr) and WRTORD(Twtr) are not in SPD,use
|
||||
conservative value here */
|
||||
ddr->timing_cfg_1 = (((ns2clk(spd.trp/4) & 0x07) << 28 ) | \
|
||||
((ns2clk(spd.tras) & 0x0f ) << 24 ) | \
|
||||
((ns2clk(spd.trcd/4) & 0x07) << 20 ) | \
|
||||
@ -210,72 +205,66 @@ long int spd_sdram(void) {
|
||||
(((ns2clk(spd.sset[6]) - 8) & 0x0f) << 12 ) | \
|
||||
( 0x300 ) | \
|
||||
((ns2clk(spd.trrd/4) & 0x07) << 4) | 1);
|
||||
#else
|
||||
ddr->timing_cfg_1 = 0x37344321;
|
||||
caslat = 4;
|
||||
#endif
|
||||
DEB(printf("DDR:timing_cfg_1=0x%08x\n",ddr->timing_cfg_1));
|
||||
|
||||
/* note: hand-coded value for timing_cfg_2, see Errata DDR1*/
|
||||
#if defined(CONFIG_MPC85xx_REV1)
|
||||
debug ("DDR:timing_cfg_1=0x%08x\n",ddr->timing_cfg_1);
|
||||
|
||||
ddr->timing_cfg_2 = 0x00000800;
|
||||
#endif
|
||||
DEB(printf("DDR:timing_cfg_2=0x%08x\n",ddr->timing_cfg_2));
|
||||
debug ("DDR:timing_cfg_2=0x%08x\n",ddr->timing_cfg_2);
|
||||
|
||||
/* only DDR I is supported, DDR I and II have different mode-register-set definition */
|
||||
/* burst length is always 4 */
|
||||
switch(caslat) {
|
||||
case 2:
|
||||
ddr->sdram_mode = 0x52; /* 1.5 */
|
||||
break;
|
||||
case 3:
|
||||
ddr->sdram_mode = 0x22; /* 2.0 */
|
||||
break;
|
||||
case 4:
|
||||
ddr->sdram_mode = 0x62; /* 2.5 */
|
||||
break;
|
||||
case 5:
|
||||
ddr->sdram_mode = 0x32; /* 3.0 */
|
||||
break;
|
||||
default:
|
||||
printf("DDR:only CAS Latency 1.5,2.0,2.5,3.0 is supported.\n");
|
||||
return 0;
|
||||
case 2:
|
||||
ddr->sdram_mode = 0x52; /* 1.5 */
|
||||
break;
|
||||
case 3:
|
||||
ddr->sdram_mode = 0x22; /* 2.0 */
|
||||
break;
|
||||
case 4:
|
||||
ddr->sdram_mode = 0x62; /* 2.5 */
|
||||
break;
|
||||
case 5:
|
||||
ddr->sdram_mode = 0x32; /* 3.0 */
|
||||
break;
|
||||
default:
|
||||
printf("DDR:only CAS Latency 1.5,2.0,2.5,3.0 is supported.\n");
|
||||
return 0;
|
||||
}
|
||||
DEB(printf("DDR:sdram_mode=0x%08x\n",ddr->sdram_mode));
|
||||
debug ("DDR:sdram_mode=0x%08x\n",ddr->sdram_mode);
|
||||
|
||||
switch(spd.refresh) {
|
||||
case 0x00:
|
||||
case 0x80:
|
||||
tmp = ns2clk(15625);
|
||||
break;
|
||||
case 0x01:
|
||||
case 0x81:
|
||||
tmp = ns2clk(3900);
|
||||
break;
|
||||
case 0x02:
|
||||
case 0x82:
|
||||
tmp = ns2clk(7800);
|
||||
break;
|
||||
case 0x03:
|
||||
case 0x83:
|
||||
tmp = ns2clk(31300);
|
||||
break;
|
||||
case 0x04:
|
||||
case 0x84:
|
||||
tmp = ns2clk(62500);
|
||||
break;
|
||||
case 0x05:
|
||||
case 0x85:
|
||||
tmp = ns2clk(125000);
|
||||
break;
|
||||
default:
|
||||
tmp = 0x512;
|
||||
break;
|
||||
case 0x00:
|
||||
case 0x80:
|
||||
tmp = ns2clk(15625);
|
||||
break;
|
||||
case 0x01:
|
||||
case 0x81:
|
||||
tmp = ns2clk(3900);
|
||||
break;
|
||||
case 0x02:
|
||||
case 0x82:
|
||||
tmp = ns2clk(7800);
|
||||
break;
|
||||
case 0x03:
|
||||
case 0x83:
|
||||
tmp = ns2clk(31300);
|
||||
break;
|
||||
case 0x04:
|
||||
case 0x84:
|
||||
tmp = ns2clk(62500);
|
||||
break;
|
||||
case 0x05:
|
||||
case 0x85:
|
||||
tmp = ns2clk(125000);
|
||||
break;
|
||||
default:
|
||||
tmp = 0x512;
|
||||
break;
|
||||
}
|
||||
|
||||
/* set BSTOPRE to 0x100 for page mode, if auto-charge is used, set BSTOPRE = 0 */
|
||||
ddr->sdram_interval = ((tmp & 0x3fff) << 16) | 0x100;
|
||||
DEB(printf("DDR:sdram_interval=0x%08x\n",ddr->sdram_interval));
|
||||
debug ("DDR:sdram_interval=0x%08x\n",ddr->sdram_interval);
|
||||
|
||||
/* is this an ECC DDR chip? */
|
||||
#if defined(CONFIG_DDR_ECC)
|
||||
@ -283,24 +272,71 @@ long int spd_sdram(void) {
|
||||
ddr->err_disable = 0x0000000d;
|
||||
ddr->err_sbe = 0x00ff0000;
|
||||
}
|
||||
DEB(printf("DDR:err_disable=0x%08x\n",ddr->err_disable));
|
||||
DEB(printf("DDR:err_sbe=0x%08x\n",ddr->err_sbe));
|
||||
debug ("DDR:err_disable=0x%08x\n",ddr->err_disable);
|
||||
debug ("DDR:err_sbe=0x%08x\n",ddr->err_sbe);
|
||||
#endif
|
||||
asm("sync;isync;msync");
|
||||
|
||||
udelay(500);
|
||||
|
||||
/* registered or unbuffered? */
|
||||
#ifdef MPC85xx_DDR_SDRAM_CLK_CNTL
|
||||
/* Setup the clock control (8555 and later)
|
||||
* SDRAM_CLK_CNTL[0] = Source synchronous enable == 1
|
||||
* SDRAM_CLK_CNTL[5-7] = Clock Adjust == 3 (3/4 cycle late)
|
||||
*/
|
||||
ddr->sdram_clk_cntl = 0x83000000;
|
||||
#endif
|
||||
|
||||
/* Figure out the settings for the sdram_cfg register. Build up
|
||||
* the entire register in 'tmp' before writing since the write into
|
||||
* the register will actually enable the memory controller, and all
|
||||
* settings must be done before enabling.
|
||||
*
|
||||
* sdram_cfg[0] = 1 (ddr sdram logic enable)
|
||||
* sdram_cfg[1] = 1 (self-refresh-enable)
|
||||
* sdram_cfg[6:7] = 2 (SDRAM type = DDR SDRAM)
|
||||
*/
|
||||
tmp = 0xc2000000;
|
||||
|
||||
/* sdram_cfg[3] = RD_EN - registered DIMM enable
|
||||
* A value of 0x26 indicates micron registered DIMMS (micron.com)
|
||||
*/
|
||||
if (spd.mod_attr == 0x26) {
|
||||
tmp |= 0x10000000;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_DDR_ECC)
|
||||
ddr->sdram_cfg = (spd.config == 0x02)?0x20000000:0x0;
|
||||
/* If the user wanted ECC (enabled via sdram_cfg[2]) */
|
||||
if (spd.config == 0x02) {
|
||||
tmp |= 0x20000000;
|
||||
}
|
||||
#endif
|
||||
ddr->sdram_cfg = 0xc2000000|((spd.mod_attr == 0x20) ? 0x0 : \
|
||||
((spd.mod_attr == 0x26) ? 0x10000000:0x0));
|
||||
|
||||
|
||||
/*
|
||||
* REV1 uses 1T timing.
|
||||
* REV2 may use 1T or 2T as configured by the user.
|
||||
*/
|
||||
{
|
||||
uint pvr = get_pvr();
|
||||
|
||||
if (pvr != PVR_85xx_REV1) {
|
||||
#if defined(CONFIG_DDR_2T_TIMING)
|
||||
/*
|
||||
* Enable 2T timing by setting sdram_cfg[16].
|
||||
*/
|
||||
tmp |= 0x8000;
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
ddr->sdram_cfg = tmp;
|
||||
|
||||
asm("sync;isync;msync");
|
||||
|
||||
udelay(500);
|
||||
|
||||
DEB(printf("DDR:sdram_cfg=0x%08x\n",ddr->sdram_cfg));
|
||||
debug ("DDR:sdram_cfg=0x%08x\n",ddr->sdram_cfg);
|
||||
|
||||
return (memsize*1024*1024);
|
||||
}
|
||||
|
||||
@ -1,4 +1,5 @@
|
||||
/*
|
||||
* Copyright 2004 Freescale Semiconductor.
|
||||
* (C) Copyright 2003 Motorola Inc.
|
||||
* Xianghua Xiao, (X.Xiao@motorola.com)
|
||||
*
|
||||
@ -30,10 +31,9 @@
|
||||
|
||||
/* --------------------------------------------------------------- */
|
||||
|
||||
#define ONE_BILLION 1000000000
|
||||
|
||||
void get_sys_info (sys_info_t * sysInfo)
|
||||
{
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
volatile immap_t *immap = (immap_t *)CFG_IMMR;
|
||||
volatile ccsr_gur_t *gur = &immap->im_gur;
|
||||
uint plat_ratio,e500_ratio;
|
||||
|
||||
@ -1,4 +1,5 @@
|
||||
/*
|
||||
* Copyright 2004 Freescale Semiconductor.
|
||||
* Copyright (C) 2003 Motorola,Inc.
|
||||
* Xianghua Xiao<X.Xiao@motorola.com>
|
||||
*
|
||||
@ -83,18 +84,39 @@
|
||||
.globl _start_e500
|
||||
|
||||
_start_e500:
|
||||
#if defined(CONFIG_MPC85xx_REV1)
|
||||
mfspr r0, PVR
|
||||
lis r1, PVR_85xx_REV1@h
|
||||
ori r1, r1, PVR_85xx_REV1@l
|
||||
cmpw r0, r1
|
||||
bne 1f
|
||||
|
||||
/* Semi-bogus errata fixup for Rev 1 */
|
||||
li r0,0x2000
|
||||
mtspr 977,r0
|
||||
#endif
|
||||
|
||||
/* Clear and set up some registers. Note: Some registers need strict
|
||||
* synchronization by sync/mbar/msync/isync when being "mtspr".
|
||||
/*
|
||||
* Before invalidating MMU L1/L2, read TLB1 Entry 0 and then
|
||||
* write it back immediately to fixup a Rev 1 bug (Errata CPU4)
|
||||
* for this initial TLB1 entry 0, otherwise the TLB1 entry 0
|
||||
* will be invalidated (incorrectly).
|
||||
*/
|
||||
lis r2,0x1000
|
||||
mtspr MAS0,r2
|
||||
tlbre
|
||||
tlbwe
|
||||
isync
|
||||
|
||||
1:
|
||||
/*
|
||||
* Clear and set up some registers.
|
||||
* Note: Some registers need strict synchronization by
|
||||
* sync/mbar/msync/isync when being "mtspr".
|
||||
* BookE: isync before PID,tlbivax,tlbwe
|
||||
* BookE: isync after MSR,PID; msync_isync after tlbivax & tlbwe
|
||||
* E500: msync,isync before L1CSR0
|
||||
* E500: isync after BBEAR,BBTAR,BUCSR,DBCR0,DBCR1,HID0,HID1,L1CSR0
|
||||
* L1CSR1, MAS[0,1,2,3,4,6],MMUCSR0, PID[0,1,2],SPEFCSR
|
||||
* E500: isync after BBEAR,BBTAR,BUCSR,DBCR0,DBCR1,HID0,HID1,
|
||||
* L1CSR0, L1CSR1, MAS[0,1,2,3,4,6],MMUCSR0, PID[0,1,2],
|
||||
* SPEFCSR
|
||||
*/
|
||||
|
||||
/* invalidate d-cache */
|
||||
@ -173,7 +195,8 @@ _start_e500:
|
||||
isync
|
||||
|
||||
/* Setup interrupt vectors */
|
||||
mtspr IVPR, r0
|
||||
lis r1,0xfff8
|
||||
mtspr IVPR, r1
|
||||
|
||||
li r1,0x0100
|
||||
mtspr IVOR0,r1 /* 0: Critical input */
|
||||
@ -203,21 +226,15 @@ _start_e500:
|
||||
li r1,0x2000
|
||||
mtspr IVOR15,r1 /* 15: Debug */
|
||||
|
||||
/* invalidate MMU L1/L2 */
|
||||
/* Note: before invalidate MMU L1/L2, we read TLB1 Entry 0 and then
|
||||
* write it back immediately to fixup a bug(Errata CPU4) for this initial
|
||||
* TLB1 entry 0,otherwise the TLB1 entry 0 will be invalidated.
|
||||
/*
|
||||
* Invalidate MMU L1/L2
|
||||
*
|
||||
* Note: There is a fixup earlier for Errata CPU4 on
|
||||
* Rev 1 parts that must precede this MMU invalidation.
|
||||
*/
|
||||
#if defined(CONFIG_MPC85xx_REV1)
|
||||
lis r2,0x1000
|
||||
mtspr MAS0,r2
|
||||
tlbre
|
||||
tlbwe
|
||||
isync
|
||||
li r2, 0x001e
|
||||
mtspr MMUCSR0, r2
|
||||
isync
|
||||
#endif
|
||||
|
||||
/* After reset, CCSRBAR is located at CFG_CCSRBAR_DEFAULT, i.e.
|
||||
* 0xff700000-0xff800000. We need add a TLB1 entry for this 1MB
|
||||
@ -278,9 +295,11 @@ _start_e500:
|
||||
li r3,4
|
||||
li r4,0
|
||||
tlbivax r4,r3
|
||||
#if defined(CONFIG_MPC85xx_REV1) /* Errata CPU6 */
|
||||
nop
|
||||
#endif
|
||||
/*
|
||||
* To avoid REV1 Errata CPU6 issues, make sure
|
||||
* the instruction following tlbivax is not a store.
|
||||
*/
|
||||
|
||||
|
||||
/* set up local access windows, defined at board/<boardname>/init.S */
|
||||
lis r7,CFG_CCSRBAR@h
|
||||
@ -781,6 +800,11 @@ get_pvr:
|
||||
mfspr r3, PVR
|
||||
blr
|
||||
|
||||
.globl get_svr
|
||||
get_svr:
|
||||
mfspr r3, SVR
|
||||
blr
|
||||
|
||||
.globl wr_tcr
|
||||
wr_tcr:
|
||||
mtspr TCR, r3
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -7,6 +7,7 @@
|
||||
* terms of the GNU Public License, Version 2, incorporated
|
||||
* herein by reference.
|
||||
*
|
||||
* Copyright 2004 Freescale Semiconductor.
|
||||
* (C) Copyright 2003, Motorola, Inc.
|
||||
* maintained by Xianghua Xiao (x.xiao@motorola.com)
|
||||
* author Andy Fleming
|
||||
@ -19,15 +20,13 @@
|
||||
#include <net.h>
|
||||
#include <mpc85xx.h>
|
||||
|
||||
/* TSEC1 is offset 0x24000, TSEC2 is offset 0x25000
|
||||
#define TSEC_BASE_ADDR (CFG_IMMR + 0x25000)
|
||||
*/
|
||||
#define TSEC_BASE_ADDR (CFG_IMMR + 0x24000)
|
||||
#define TSEC_MEM_SIZE 0x01000
|
||||
#define TSEC_SIZE 0x01000
|
||||
|
||||
#define MAC_ADDR_LEN 6
|
||||
|
||||
#define TSEC_TIMEOUT 1000000
|
||||
/* #define TSEC_TIMEOUT 1000000 */
|
||||
#define TSEC_TIMEOUT 1000
|
||||
#define TOUT_LOOP 1000000
|
||||
|
||||
/* MAC register bits */
|
||||
@ -47,11 +46,15 @@
|
||||
#define MACCFG2_INIT_SETTINGS 0x00007205
|
||||
#define MACCFG2_FULL_DUPLEX 0x00000001
|
||||
#define MACCFG2_IF 0x00000300
|
||||
#define MACCFG2_GMII 0x00000200
|
||||
#define MACCFG2_MII 0x00000100
|
||||
|
||||
#define ECNTRL_INIT_SETTINGS 0x00001000
|
||||
#define ECNTRL_TBI_MODE 0x00000020
|
||||
|
||||
#define miim_end -2
|
||||
#define miim_read -1
|
||||
|
||||
#define TBIPA_VALUE 0x1f
|
||||
#define MIIMCFG_INIT_VALUE 0x00000003
|
||||
#define MIIMCFG_RESET 0x80000000
|
||||
@ -60,52 +63,84 @@
|
||||
#define MIIMIND_NOTVALID 0x00000004
|
||||
|
||||
#define MIIM_CONTROL 0x00
|
||||
#define MIIM_CONTROL_RESET 0x00009140
|
||||
#define MIIM_CONTROL_INIT 0x00001140
|
||||
#define MIIM_ANEN 0x00001000
|
||||
#define MIIM_CONTROL_RESET 0x00009140
|
||||
|
||||
#define MIIM_CR 0x00
|
||||
#define MIIM_CR_RST 0x00008000
|
||||
#define MIIM_CR_INIT 0x00001000
|
||||
|
||||
#define MIIM_STATUS 0x1
|
||||
#define MIIM_STATUS_AN_DONE 0x00000020
|
||||
#define MIIM_STATUS_LINK 0x0004
|
||||
|
||||
#define MIIM_GBIT_CONTROL 0x9
|
||||
#define MIIM_GBIT_CONTROL_INIT 0xe00
|
||||
#define MIIM_PHYIR1 0x2
|
||||
#define MIIM_PHYIR2 0x3
|
||||
|
||||
#define MIIM_TBI_ANEX 0x6
|
||||
#define MIIM_TBI_ANEX_NP 0x00000004
|
||||
#define MIIM_TBI_ANEX_PRX 0x00000002
|
||||
#define MIIM_ANAR 0x4
|
||||
#define MIIM_ANAR_INIT 0x1e1
|
||||
|
||||
#define MIIM_TBI_ANLPBPA 0x5
|
||||
#define MIIM_TBI_ANLPBPA_HALF 0x00000040
|
||||
#define MIIM_TBI_ANLPBPA_FULL 0x00000020
|
||||
|
||||
#ifdef CONFIG_PHY_CIS8201
|
||||
#define MIIM_AUX_CONSTAT 0x1c
|
||||
#define MIIM_AUXCONSTAT_INIT 0x0004
|
||||
#define MIIM_AUXCONSTAT_DUPLEX 0x0020
|
||||
#define MIIM_AUXCONSTAT_SPEED 0x0018
|
||||
#define MIIM_AUXCONSTAT_GBIT 0x0010
|
||||
#define MIIM_AUXCONSTAT_100 0x0008
|
||||
#define MIIM_TBI_ANEX 0x6
|
||||
#define MIIM_TBI_ANEX_NP 0x00000004
|
||||
#define MIIM_TBI_ANEX_PRX 0x00000002
|
||||
|
||||
#define MIIM_EXT_CON1 0x17
|
||||
#define MIIM_EXTCON1_INIT 0x0000
|
||||
#define MIIM_GBIT_CONTROL 0x9
|
||||
#define MIIM_GBIT_CONTROL_INIT 0xe00
|
||||
|
||||
#endif
|
||||
/* Cicada Auxiliary Control/Status Register */
|
||||
#define MIIM_CIS8201_AUX_CONSTAT 0x1c
|
||||
#define MIIM_CIS8201_AUXCONSTAT_INIT 0x0004
|
||||
#define MIIM_CIS8201_AUXCONSTAT_DUPLEX 0x0020
|
||||
#define MIIM_CIS8201_AUXCONSTAT_SPEED 0x0018
|
||||
#define MIIM_CIS8201_AUXCONSTAT_GBIT 0x0010
|
||||
#define MIIM_CIS8201_AUXCONSTAT_100 0x0008
|
||||
|
||||
#ifdef CONFIG_PHY_M88E1011
|
||||
#define MIIM_ANAR 0x4
|
||||
#define MIIM_ANAR_INIT 0x1e1
|
||||
/* Cicada Extended Control Register 1 */
|
||||
#define MIIM_CIS8201_EXT_CON1 0x17
|
||||
#define MIIM_CIS8201_EXTCON1_INIT 0x0000
|
||||
|
||||
/* Cicada 8204 Extended PHY Control Register 1 */
|
||||
#define MIIM_CIS8204_EPHY_CON 0x17
|
||||
#define MIIM_CIS8204_EPHYCON_INIT 0x0006
|
||||
|
||||
/* Cicada 8204 Serial LED Control Register */
|
||||
#define MIIM_CIS8204_SLED_CON 0x1b
|
||||
#define MIIM_CIS8204_SLEDCON_INIT 0x1115
|
||||
|
||||
#define MIIM_GBIT_CON 0x09
|
||||
#define MIIM_GBIT_CON_ADVERT 0x0e00
|
||||
|
||||
#define MIIM_PHY_STATUS 0x11
|
||||
#define MIIM_PHYSTAT_SPEED 0xc000
|
||||
#define MIIM_PHYSTAT_GBIT 0x8000
|
||||
#define MIIM_PHYSTAT_100 0x4000
|
||||
#define MIIM_PHYSTAT_DUPLEX 0x2000
|
||||
#define MIIM_PHYSTAT_SPDDONE 0x0800
|
||||
#define MIIM_PHYSTAT_LINK 0x0400
|
||||
#endif
|
||||
/* 88E1011 PHY Status Register */
|
||||
#define MIIM_88E1011_PHY_STATUS 0x11
|
||||
#define MIIM_88E1011_PHYSTAT_SPEED 0xc000
|
||||
#define MIIM_88E1011_PHYSTAT_GBIT 0x8000
|
||||
#define MIIM_88E1011_PHYSTAT_100 0x4000
|
||||
#define MIIM_88E1011_PHYSTAT_DUPLEX 0x2000
|
||||
#define MIIM_88E1011_PHYSTAT_SPDDONE 0x0800
|
||||
#define MIIM_88E1011_PHYSTAT_LINK 0x0400
|
||||
|
||||
/* DM9161 Control register values */
|
||||
#define MIIM_DM9161_CR_STOP 0x0400
|
||||
#define MIIM_DM9161_CR_RSTAN 0x1200
|
||||
|
||||
#define MIIM_DM9161_SCR 0x10
|
||||
#define MIIM_DM9161_SCR_INIT 0x0610
|
||||
|
||||
/* DM9161 Specified Configuration and Status Register */
|
||||
#define MIIM_DM9161_SCSR 0x11
|
||||
#define MIIM_DM9161_SCSR_100F 0x8000
|
||||
#define MIIM_DM9161_SCSR_100H 0x4000
|
||||
#define MIIM_DM9161_SCSR_10F 0x2000
|
||||
#define MIIM_DM9161_SCSR_10H 0x1000
|
||||
|
||||
/* DM9161 10BT Configuration/Status */
|
||||
#define MIIM_DM9161_10BTCSR 0x12
|
||||
#define MIIM_DM9161_10BTCSR_INIT 0x7800
|
||||
|
||||
#define MIIM_READ_COMMAND 0x00000001
|
||||
|
||||
@ -120,27 +155,6 @@
|
||||
#define TSTAT_CLEAR_THALT 0x80000000
|
||||
#define RSTAT_CLEAR_RHALT 0x00800000
|
||||
|
||||
/* Write value to the PHY at phyid to the register at offset, */
|
||||
/* using the register space defined in regbase. Note that */
|
||||
/* miimcfg needs to have the clock speed setup correctly. This */
|
||||
/* macro will wait until the write is done before it finishes */
|
||||
#define write_phy_reg(regbase, phyid, offset, value) do { \
|
||||
int timeout=1000000; \
|
||||
regbase->miimadd = (phyid << 8) | offset; \
|
||||
regbase->miimcon = value; \
|
||||
asm("msync"); \
|
||||
while((regbase->miimind & MIIMIND_BUSY) && timeout--); \
|
||||
} while(0)
|
||||
|
||||
|
||||
/* This works around errata in reseting the PHY */
|
||||
#define RESET_ERRATA(regs, ID) do { \
|
||||
write_phy_reg(regs, (ID), 0x1d, 0x1f); \
|
||||
write_phy_reg(regs, (ID), 0x1e, 0x200c); \
|
||||
write_phy_reg(regs, (ID), 0x1d, 0x5); \
|
||||
write_phy_reg(regs, (ID), 0x1e, 0x0); \
|
||||
write_phy_reg(regs, (ID), 0x1e, 0x100); \
|
||||
} while(0)
|
||||
|
||||
#define IEVENT_INIT_CLEAR 0xffffffff
|
||||
#define IEVENT_BABR 0x80000000
|
||||
@ -402,4 +416,63 @@ typedef struct tsec
|
||||
uint resc00[256];
|
||||
} tsec_t;
|
||||
|
||||
struct tsec_private {
|
||||
volatile tsec_t *regs;
|
||||
volatile tsec_t *phyregs;
|
||||
struct phy_info *phyinfo;
|
||||
uint phyaddr;
|
||||
uint gigabit;
|
||||
uint link;
|
||||
uint duplexity;
|
||||
uint speed;
|
||||
};
|
||||
|
||||
|
||||
/*
|
||||
* struct phy_cmd: A command for reading or writing a PHY register
|
||||
*
|
||||
* mii_reg: The register to read or write
|
||||
*
|
||||
* mii_data: For writes, the value to put in the register.
|
||||
* A value of -1 indicates this is a read.
|
||||
*
|
||||
* funct: A function pointer which is invoked for each command.
|
||||
* For reads, this function will be passed the value read
|
||||
* from the PHY, and process it.
|
||||
* For writes, the result of this function will be written
|
||||
* to the PHY register
|
||||
*/
|
||||
struct phy_cmd {
|
||||
uint mii_reg;
|
||||
uint mii_data;
|
||||
uint (*funct) (uint mii_reg, struct tsec_private* priv);
|
||||
};
|
||||
|
||||
/* struct phy_info: a structure which defines attributes for a PHY
|
||||
*
|
||||
* id will contain a number which represents the PHY. During
|
||||
* startup, the driver will poll the PHY to find out what its
|
||||
* UID--as defined by registers 2 and 3--is. The 32-bit result
|
||||
* gotten from the PHY will be shifted right by "shift" bits to
|
||||
* discard any bits which may change based on revision numbers
|
||||
* unimportant to functionality
|
||||
*
|
||||
* The struct phy_cmd entries represent pointers to an arrays of
|
||||
* commands which tell the driver what to do to the PHY.
|
||||
*/
|
||||
struct phy_info {
|
||||
uint id;
|
||||
char *name;
|
||||
uint shift;
|
||||
/* Called to configure the PHY, and modify the controller
|
||||
* based on the results */
|
||||
struct phy_cmd *config;
|
||||
|
||||
/* Called when starting up the controller */
|
||||
struct phy_cmd *startup;
|
||||
|
||||
/* Called when bringing down the controller */
|
||||
struct phy_cmd *shutdown;
|
||||
};
|
||||
|
||||
#endif /* __TSEC_H */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user