leandrof/u-boot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Merge branch 'master' of git://git.denx.de/u-boot-arm

Browse Source
This commit is contained in:
Tom Rini 2014-05-24 06:34:08 -04:00
commit 9665fa8f9e
78 changed files with 2390 additions and 534 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
Makefile
View File

@ -753,6 +753,9 @@ ALL-$(CONFIG_SPL) += spl/u-boot-spl.bin
ALL-$(CONFIG_SPL_FRAMEWORK) += u-boot.img
ALL-$(CONFIG_TPL) += tpl/u-boot-tpl.bin
ALL-$(CONFIG_OF_SEPARATE) += u-boot.dtb u-boot-dtb.bin
ifeq ($(CONFIG_SPL_FRAMEWORK),y)
ALL-$(CONFIG_OF_SEPARATE) += u-boot-dtb.img
endif
ALL-$(CONFIG_OF_HOSTFILE) += u-boot.dtb
ifneq ($(CONFIG_SPL_TARGET),)
ALL-$(CONFIG_SPL) += $(CONFIG_SPL_TARGET:"%"=%)
@ -855,6 +858,11 @@ MKIMAGEFLAGS_u-boot.pbl = -n $(srctree)/$(CONFIG_SYS_FSL_PBL_RCW:"%"=%) \
u-boot.img u-boot.kwb u-boot.pbl: u-boot.bin FORCE
$(call if_changed,mkimage)
MKIMAGEFLAGS_u-boot-dtb.img = $(MKIMAGEFLAGS_u-boot.img)
u-boot-dtb.img: u-boot-dtb.bin FORCE
$(call if_changed,mkimage)
u-boot.sha1: u-boot.bin
tools/ubsha1 u-boot.bin

1
arch/arm/cpu/armv7/am33xx/Makefile
View File

@ -14,7 +14,6 @@ endif
obj-$(CONFIG_TI816X) += clock_ti816x.o
obj-y += sys_info.o
obj-y += mem.o
obj-y += ddr.o
obj-y += emif4.o
obj-y += board.o

98
arch/arm/cpu/armv7/am33xx/mem.c
View File

@ -1,98 +0,0 @@
/*
* (C) Copyright 2010
* Texas Instruments, <www.ti.com>
*
* Author :
* Mansoor Ahamed <mansoor.ahamed@ti.com>
*
* Initial Code from:
* Manikandan Pillai <mani.pillai@ti.com>
* Richard Woodruff <r-woodruff2@ti.com>
* Syed Mohammed Khasim <khasim@ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/cpu.h>
#include <asm/arch/mem.h>
#include <asm/arch/sys_proto.h>
#include <command.h>
struct gpmc *gpmc_cfg;
void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
u32 size)
{
writel(0, &cs->config7);
sdelay(1000);
/* Delay for settling */
writel(gpmc_config[0], &cs->config1);
writel(gpmc_config[1], &cs->config2);
writel(gpmc_config[2], &cs->config3);
writel(gpmc_config[3], &cs->config4);
writel(gpmc_config[4], &cs->config5);
writel(gpmc_config[5], &cs->config6);
/* Enable the config */
writel((((size & 0xF) << 8) | ((base >> 24) & 0x3F) |
(1 << 6)), &cs->config7);
sdelay(2000);
}
/*****************************************************
* gpmc_init(): init gpmc bus
* Init GPMC for x16, MuxMode (SDRAM in x32).
* This code can only be executed from SRAM or SDRAM.
*****************************************************/
void gpmc_init(void)
{
/* putting a blanket check on GPMC based on ZeBu for now */
gpmc_cfg = (struct gpmc *)GPMC_BASE;
#if defined(CONFIG_NOR)
/* configure GPMC for NOR */
const u32 gpmc_regs[GPMC_MAX_REG] = { STNOR_GPMC_CONFIG1,
STNOR_GPMC_CONFIG2,
STNOR_GPMC_CONFIG3,
STNOR_GPMC_CONFIG4,
STNOR_GPMC_CONFIG5,
STNOR_GPMC_CONFIG6,
STNOR_GPMC_CONFIG7
};
u32 size = GPMC_SIZE_16M;
u32 base = CONFIG_SYS_FLASH_BASE;
#elif defined(CONFIG_NAND)
/* configure GPMC for NAND */
const u32 gpmc_regs[GPMC_MAX_REG] = { M_NAND_GPMC_CONFIG1,
M_NAND_GPMC_CONFIG2,
M_NAND_GPMC_CONFIG3,
M_NAND_GPMC_CONFIG4,
M_NAND_GPMC_CONFIG5,
M_NAND_GPMC_CONFIG6,
0
};
u32 size = GPMC_SIZE_256M;
u32 base = CONFIG_SYS_NAND_BASE;
#else
const u32 gpmc_regs[GPMC_MAX_REG] = { 0, 0, 0, 0, 0, 0, 0 };
u32 size = 0;
u32 base = 0;
#endif
/* global settings */
writel(0x00000008, &gpmc_cfg->sysconfig);
writel(0x00000000, &gpmc_cfg->irqstatus);
writel(0x00000000, &gpmc_cfg->irqenable);
#ifdef CONFIG_NOR
writel(0x00000200, &gpmc_cfg->config);
#else
writel(0x00000012, &gpmc_cfg->config);
#endif
/*
* Disable the GPMC0 config set by ROM code
*/
writel(0, &gpmc_cfg->cs[0].config7);
sdelay(1000);
/* enable chip-select specific configurations */
enable_gpmc_cs_config(gpmc_regs, &gpmc_cfg->cs[0], base, size);
}

41
arch/arm/cpu/armv7/am33xx/sys_info.c
View File

@ -79,12 +79,24 @@ u32 get_sysboot_value(void)
}
#ifdef CONFIG_DISPLAY_CPUINFO
static char *cpu_revs[] = {
"1.0",
"2.0",
"2.1"};
static char *dev_types[] = {
"TST",
"EMU",
"HS",
"GP"};
/**
* Print CPU information
*/
int print_cpuinfo(void)
{
char *cpu_s, *sec_s;
char *cpu_s, *sec_s, *rev_s;
switch (get_cpu_type()) {
case AM335X:
@ -94,28 +106,21 @@ int print_cpuinfo(void)
cpu_s = "TI81XX";
break;
default:
cpu_s = "Unknown cpu type";
cpu_s = "Unknown CPU type";
break;
}
switch (get_device_type()) {
case TST_DEVICE:
sec_s = "TST";
break;
case EMU_DEVICE:
sec_s = "EMU";
break;
case HS_DEVICE:
sec_s = "HS";
break;
case GP_DEVICE:
sec_s = "GP";
break;
default:
if (get_cpu_rev() < ARRAY_SIZE(cpu_revs))
rev_s = cpu_revs[get_cpu_rev()];
else
rev_s = "?";
if (get_device_type() < ARRAY_SIZE(dev_types))
sec_s = dev_types[get_device_type()];
else
sec_s = "?";
}
printf("%s-%s rev %d\n", cpu_s, sec_s, get_cpu_rev());
printf("%s-%s rev %s\n", cpu_s, sec_s, rev_s);
return 0;
}

4
arch/arm/cpu/armv7/omap-common/Makefile
View File

@ -27,8 +27,4 @@ obj-y += boot-common.o
obj-y += lowlevel_init.o
endif
ifndef CONFIG_SPL_BUILD
ifneq ($(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),)
obj-y += mem-common.o
endif
endif

2
arch/arm/cpu/armv7/omap-common/emif-common.c
View File

@ -1384,7 +1384,9 @@ void sdram_init(void)
if (sdram_type == EMIF_SDRAM_TYPE_DDR3 &&
(!in_sdram && !warm_reset())) {
if (emif1_enabled)
do_bug0039_workaround(EMIF1_BASE);
if (emif2_enabled)
do_bug0039_workaround(EMIF2_BASE);
}

15
arch/arm/cpu/armv7/omap-common/hwinit-common.c
View File

@ -185,7 +185,7 @@ u32 omap_sdram_size(void)
{
u32 section, i, valid;
u64 sdram_start = 0, sdram_end = 0, addr,
size, total_size = 0, trap_size = 0;
size, total_size = 0, trap_size = 0, trap_start = 0;
for (i = 0; i < 4; i++) {
section = __raw_readl(DMM_BASE + i*4);
@ -194,8 +194,8 @@ u32 omap_sdram_size(void)
addr = section & EMIF_SYS_ADDR_MASK;
/* See if the address is valid */
if ((addr >= DRAM_ADDR_SPACE_START) &&
(addr < DRAM_ADDR_SPACE_END)) {
if ((addr >= TI_ARMV7_DRAM_ADDR_SPACE_START) &&
(addr < TI_ARMV7_DRAM_ADDR_SPACE_END)) {
size = ((section & EMIF_SYS_SIZE_MASK) >>
EMIF_SYS_SIZE_SHIFT);
size = 1 << size;
@ -208,12 +208,15 @@ u32 omap_sdram_size(void)
sdram_end = addr + size;
} else {
trap_size = size;
trap_start = addr;
}
}
}
}
}
if ((trap_start >= sdram_start) && (trap_start < sdram_end))
total_size = (sdram_end - sdram_start) - (trap_size);
else
total_size = sdram_end - sdram_start;
return total_size;
}

117
arch/arm/cpu/armv7/omap-common/mem-common.c
View File

@ -2,31 +2,136 @@
* (C) Copyright 2010
* Texas Instruments, <www.ti.com>
*
* Steve Sakoman <steve@sakoman.com>
* Author :
* Mansoor Ahamed <mansoor.ahamed@ti.com>
*
* Initial Code from:
* Manikandan Pillai <mani.pillai@ti.com>
* Richard Woodruff <r-woodruff2@ti.com>
* Syed Mohammed Khasim <khasim@ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/cpu.h>
#include <asm/arch/mem.h>
#include <asm/arch/sys_proto.h>
#include <command.h>
#include <linux/mtd/omap_gpmc.h>
struct gpmc *gpmc_cfg;
#if defined(CONFIG_OMAP34XX)
/********************************************************
* mem_ok() - test used to see if timings are correct
* for a part. Helps in guessing which part
* we are currently using.
*******************************************************/
u32 mem_ok(u32 cs)
{
u32 val1, val2, addr;
u32 pattern = 0x12345678;
addr = OMAP34XX_SDRC_CS0 + get_sdr_cs_offset(cs);
writel(0x0, addr + 0x400); /* clear pos A */
writel(pattern, addr); /* pattern to pos B */
writel(0x0, addr + 4); /* remove pattern off the bus */
val1 = readl(addr + 0x400); /* get pos A value */
val2 = readl(addr); /* get val2 */
writel(0x0, addr + 0x400); /* clear pos A */
if ((val1 != 0) || (val2 != pattern)) /* see if pos A val changed */
return 0;
else
return 1;
}
#endif
void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
u32 size)
{
writel(0, &cs->config7);
sdelay(1000);
/* Delay for settling */
writel(gpmc_config[0], &cs->config1);
writel(gpmc_config[1], &cs->config2);
writel(gpmc_config[2], &cs->config3);
writel(gpmc_config[3], &cs->config4);
writel(gpmc_config[4], &cs->config5);
writel(gpmc_config[5], &cs->config6);
/* Enable the config */
writel((((size & 0xF) << 8) | ((base >> 24) & 0x3F) |
(1 << 6)), &cs->config7);
sdelay(2000);
}
/*****************************************************
* gpmc_init(): init gpmc bus
* Init GPMC for x16, MuxMode (SDRAM in x32).
* This code can only be executed from SRAM or SDRAM.
*****************************************************/
void gpmc_init(void)
{
/* putting a blanket check on GPMC based on ZeBu for now */
gpmc_cfg = (struct gpmc *)GPMC_BASE;
#if defined(CONFIG_NOR)
/* configure GPMC for NOR */
const u32 gpmc_regs[GPMC_MAX_REG] = { STNOR_GPMC_CONFIG1,
STNOR_GPMC_CONFIG2,
STNOR_GPMC_CONFIG3,
STNOR_GPMC_CONFIG4,
STNOR_GPMC_CONFIG5,
STNOR_GPMC_CONFIG6,
STNOR_GPMC_CONFIG7
};
u32 size = GPMC_SIZE_16M;
u32 base = CONFIG_SYS_FLASH_BASE;
#elif defined(CONFIG_NAND)
/* configure GPMC for NAND */
const u32 gpmc_regs[GPMC_MAX_REG] = { M_NAND_GPMC_CONFIG1,
M_NAND_GPMC_CONFIG2,
M_NAND_GPMC_CONFIG3,
M_NAND_GPMC_CONFIG4,
M_NAND_GPMC_CONFIG5,
M_NAND_GPMC_CONFIG6,
0
};
u32 size = GPMC_SIZE_256M;
u32 base = CONFIG_SYS_NAND_BASE;
#elif defined(CONFIG_CMD_ONENAND)
const u32 gpmc_regs[GPMC_MAX_REG] = { ONENAND_GPMC_CONFIG1,
ONENAND_GPMC_CONFIG2,
ONENAND_GPMC_CONFIG3,
ONENAND_GPMC_CONFIG4,
ONENAND_GPMC_CONFIG5,
ONENAND_GPMC_CONFIG6,
0
};
u32 base = PISMO1_ONEN_BASE;
u32 size = PISMO1_ONEN_SIZE;
#else
const u32 gpmc_regs[GPMC_MAX_REG] = { 0, 0, 0, 0, 0, 0, 0 };
u32 size = 0;
u32 base = 0;
#endif
/* global settings */
writel(0, &gpmc_cfg->irqenable); /* isr's sources masked */
writel(0, &gpmc_cfg->timeout_control);/* timeout disable */
writel(0x00000008, &gpmc_cfg->sysconfig);
writel(0x00000000, &gpmc_cfg->irqstatus);
writel(0x00000000, &gpmc_cfg->irqenable);
writel(0x00000000, &gpmc_cfg->timeout_control);
#ifdef CONFIG_NOR
writel(0x00000200, &gpmc_cfg->config);
#else
writel(0x00000012, &gpmc_cfg->config);
#endif
/*
* Disable the GPMC0 config set by ROM code
* It conflicts with our MPDB (both at 0x08000000)
*/
writel(0, &gpmc_cfg->cs[0].config7);
sdelay(1000);
/* enable chip-select specific configurations */
enable_gpmc_cs_config(gpmc_regs, &gpmc_cfg->cs[0], base, size);
}

1
arch/arm/cpu/armv7/omap3/Makefile
View File

@ -9,7 +9,6 @@ obj-y := lowlevel_init.o
obj-y += board.o
obj-y += clock.o
obj-y += mem.o
obj-y += sys_info.o
ifdef CONFIG_SPL_BUILD
obj-$(CONFIG_SPL_OMAP3_ID_NAND) += spl_id_nand.o

40
arch/arm/cpu/armv7/omap5/hw_data.c
View File

@ -372,6 +372,38 @@ struct vcores_data dra752_volts = {
.iva.pmic = &tps659038,
};
struct vcores_data dra722_volts = {
.mpu.value = 1000,
.mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU_NOM,
.mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.mpu.addr = 0x23,
.mpu.pmic = &tps659038,
.eve.value = 1000,
.eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
.eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.eve.addr = 0x2f,
.eve.pmic = &tps659038,
.gpu.value = 1000,
.gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU_NOM,
.gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.gpu.addr = 0x2f,
.gpu.pmic = &tps659038,
.core.value = 1000,
.core.efuse.reg = STD_FUSE_OPP_VMIN_CORE_NOM,
.core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.core.addr = 0x27,
.core.pmic = &tps659038,
.iva.value = 1000,
.iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA_NOM,
.iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.iva.addr = 0x2f,
.iva.pmic = &tps659038,
};
/*
* Enable essential clock domains, modules and
* do some additional special settings needed
@ -558,6 +590,13 @@ void hw_data_init(void)
*ctrl = &dra7xx_ctrl;
break;
case DRA722_ES1_0:
*prcm = &dra7xx_prcm;
*dplls_data = &dra7xx_dplls;
*omap_vcores = &dra722_volts;
*ctrl = &dra7xx_ctrl;
break;
default:
printf("\n INVALID OMAP REVISION ");
}
@ -580,6 +619,7 @@ void get_ioregs(const struct ctrl_ioregs **regs)
break;
case DRA752_ES1_0:
case DRA752_ES1_1:
case DRA722_ES1_0:
*regs = &ioregs_dra7xx_es1;
break;

3
arch/arm/cpu/armv7/omap5/hwinit.c
View File

@ -336,6 +336,9 @@ void init_omap_revision(void)
case DRA752_CONTROL_ID_CODE_ES1_1:
*omap_si_rev = DRA752_ES1_1;
break;
case DRA722_CONTROL_ID_CODE_ES1_0:
*omap_si_rev = DRA722_ES1_0;
break;
default:
*omap_si_rev = OMAP5430_SILICON_ID_INVALID;
}

8
arch/arm/cpu/armv7/omap5/prcm-regs.c
View File

@ -447,10 +447,10 @@ struct omap_sys_ctrl_regs const dra7xx_ctrl = {
.control_wkup_control_spare_r = 0x4AE0C5B4,
.control_wkup_control_spare_r_c0 = 0x4AE0C5B8,
.control_srcomp_east_side_wkup = 0x4AE0C5BC,
.control_efuse_1 = 0x4AE0C5C0,
.control_efuse_2 = 0x4AE0C5C4,
.control_efuse_3 = 0x4AE0C5C8,
.control_efuse_4 = 0x4AE0C5CC,
.control_efuse_1 = 0x4AE0C5C8,
.control_efuse_2 = 0x4AE0C5CC,
.control_efuse_3 = 0x4AE0C5D0,
.control_efuse_4 = 0x4AE0C5D4,
.control_efuse_13 = 0x4AE0C5F0,
};

19
arch/arm/cpu/armv7/omap5/sdram.c
View File

@ -229,6 +229,17 @@ const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2 = {
.is_ma_present = 0x1
};
/*
* DRA722 EVM EMIF1 CONFIGURATION
*/
const struct dmm_lisa_map_regs lisa_map_2G_x_2 = {
.dmm_lisa_map_0 = 0x0,
.dmm_lisa_map_1 = 0x0,
.dmm_lisa_map_2 = 0x80600100,
.dmm_lisa_map_3 = 0xFF020100,
.is_ma_present = 0x1
};
static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs)
{
switch (omap_revision()) {
@ -255,6 +266,7 @@ static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs)
break;
}
break;
case DRA722_ES1_0:
default:
*regs = &emif_1_regs_ddr3_532_mhz_1cs_dra_es1;
}
@ -275,8 +287,11 @@ static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs
break;
case DRA752_ES1_0:
case DRA752_ES1_1:
default:
*dmm_lisa_regs = &lisa_map_2G_x_2_x_2_2G_x_1_x_2;
break;
case DRA722_ES1_0:
default:
*dmm_lisa_regs = &lisa_map_2G_x_2;
}
}
@ -463,6 +478,7 @@ static void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr,
break;
case DRA752_ES1_0:
case DRA752_ES1_1:
case DRA722_ES1_0:
if (emif_nr == 1) {
*regs = dra_ddr3_ext_phy_ctrl_const_base_es1_emif1;
*size =
@ -630,6 +646,7 @@ const struct read_write_regs *get_bug_regs(u32 *iterations)
break;
case DRA752_ES1_0:
case DRA752_ES1_1:
case DRA722_ES1_0:
bug_00339_regs_ptr = dra_bug_00339_regs;
*iterations = sizeof(dra_bug_00339_regs)/
sizeof(dra_bug_00339_regs[0]);

2
arch/arm/cpu/armv7/rmobile/pfc-r8a7791.c
View File

@ -913,7 +913,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
/* SEL_SCIF3 [2] */
FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3,
/* SEL_IEB [2] */
FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2,
FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0,
/* SEL_MMC [1] */
FN_SEL_MMC_0, FN_SEL_MMC_1,
/* SEL_SCIF5 [1] */

13
arch/arm/cpu/armv7/zynq/cpu.c
View File

@ -14,6 +14,9 @@ void lowlevel_init(void)
{
}
#define ZYNQ_SILICON_VER_MASK 0xF0000000
#define ZYNQ_SILICON_VER_SHIFT 28
int arch_cpu_init(void)
{
zynq_slcr_unlock();
@ -42,6 +45,16 @@ int arch_cpu_init(void)
return 0;
}
unsigned int zynq_get_silicon_version(void)
{
unsigned int ver;
ver = (readl(&devcfg_base->mctrl) &
ZYNQ_SILICON_VER_MASK) >> ZYNQ_SILICON_VER_SHIFT;
return ver;
}
void reset_cpu(ulong addr)
{
zynq_slcr_cpu_reset();

5
arch/arm/cpu/armv7/zynq/ddrc.c
View File

@ -40,11 +40,8 @@ void zynq_ddrc_init(void)
* first stage bootloader. To get ECC to work all memory has
* been initialized by writing any value.
*/
memset(0, 0, 1 * 1024 * 1024);
memset((void *)0, 0, 1 * 1024 * 1024);
} else {
puts("Memory: ECC disabled\n");
}
if (width == ZYNQ_DDRC_CTRLREG_BUSWIDTH_16BIT)
gd->ram_size /= 2;
}

87
arch/arm/cpu/armv7/zynq/slcr.c
View File

@ -8,26 +8,75 @@
#include <asm/io.h>
#include <malloc.h>
#include <asm/arch/hardware.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/clk.h>
#define SLCR_LOCK_MAGIC 0x767B
#define SLCR_UNLOCK_MAGIC 0xDF0D
#define SLCR_USB_L1_SEL 0x04
#define SLCR_IDCODE_MASK 0x1F000
#define SLCR_IDCODE_SHIFT 12
/*
* zynq_slcr_mio_get_status - Get the status of MIO peripheral.
*
* @peri_name: Name of the peripheral for checking MIO status
* @get_pins: Pointer to array of get pin for this peripheral
* @num_pins: Number of pins for this peripheral
* @mask: Mask value
* @check_val: Required check value to get the status of periph
*/
struct zynq_slcr_mio_get_status {
const char *peri_name;
const int *get_pins;
int num_pins;
u32 mask;
u32 check_val;
};
static const int usb0_pins[] = {
28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39
};
static const int usb1_pins[] = {
40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51
};
static const struct zynq_slcr_mio_get_status mio_periphs[] = {
{
"usb0",
usb0_pins,
ARRAY_SIZE(usb0_pins),
SLCR_USB_L1_SEL,
SLCR_USB_L1_SEL,
},
{
"usb1",
usb1_pins,
ARRAY_SIZE(usb1_pins),
SLCR_USB_L1_SEL,
SLCR_USB_L1_SEL,
},
};
static int slcr_lock = 1; /* 1 means locked, 0 means unlocked */
void zynq_slcr_lock(void)
{
if (!slcr_lock)
if (!slcr_lock) {
writel(SLCR_LOCK_MAGIC, &slcr_base->slcr_lock);
slcr_lock = 1;
}
}
void zynq_slcr_unlock(void)
{
if (slcr_lock)
if (slcr_lock) {
writel(SLCR_UNLOCK_MAGIC, &slcr_base->slcr_unlock);
slcr_lock = 0;
}
}
/* Reset the entire system */
@ -82,7 +131,7 @@ void zynq_slcr_devcfg_disable(void)
{
zynq_slcr_unlock();
/* Disable AXI interface */
/* Disable AXI interface by asserting FPGA resets */
writel(0xFFFFFFFF, &slcr_base->fpga_rst_ctrl);
/* Set Level Shifters DT618760 */
@ -98,7 +147,7 @@ void zynq_slcr_devcfg_enable(void)
/* Set Level Shifters DT618760 */
writel(0xF, &slcr_base->lvl_shftr_en);
/* Disable AXI interface */
/* Enable AXI interface by de-asserting FPGA resets */
writel(0x0, &slcr_base->fpga_rst_ctrl);
zynq_slcr_lock();
@ -115,3 +164,33 @@ u32 zynq_slcr_get_idcode(void)
return (readl(&slcr_base->pss_idcode) & SLCR_IDCODE_MASK) >>
SLCR_IDCODE_SHIFT;
}
/*
* zynq_slcr_get_mio_pin_status - Get the MIO pin status of peripheral.
*
* @periph: Name of the peripheral
*
* Returns count to indicate the number of pins configured for the
* given @periph.
*/
int zynq_slcr_get_mio_pin_status(const char *periph)
{
const struct zynq_slcr_mio_get_status *mio_ptr;
int val, i, j;
int mio = 0;
for (i = 0; i < ARRAY_SIZE(mio_periphs); i++) {
if (strcmp(periph, mio_periphs[i].peri_name) == 0) {
mio_ptr = &mio_periphs[i];
for (j = 0; j < mio_ptr->num_pins; j++) {
val = readl(&slcr_base->mio_pin
[mio_ptr->get_pins[j]]);
if ((val & mio_ptr->mask) == mio_ptr->check_val)
mio++;
}
break;
}
}
return mio;
}

15
arch/arm/cpu/armv7/zynq/spl.c
View File

@ -28,6 +28,13 @@ void board_init_f(ulong dummy)
board_init_r(NULL, 0);
}
#ifdef CONFIG_SPL_BOARD_INIT
void spl_board_init(void)
{
board_init();
}
#endif
u32 spl_boot_device(void)
{
u32 mode;
@ -67,3 +74,11 @@ int spl_start_uboot(void)
return 0;
}
#endif
__weak void ps7_init(void)
{
/*
* This function is overridden by the one in
* board/xilinx/zynq/ps7_init.c, if it exists.
*/
}

194
arch/arm/dts/zynq-7000.dtsi
View File

@ -10,4 +10,198 @@
/ {
compatible = "xlnx,zynq-7000";
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <0>;
clocks = <&clkc 3>;
clock-latency = <1000>;
operating-points = <
/* kHz uV */
666667 1000000
333334 1000000
222223 1000000
>;
};
cpu@1 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <1>;
clocks = <&clkc 3>;
};
};
pmu {
compatible = "arm,cortex-a9-pmu";
interrupts = <0 5 4>, <0 6 4>;
interrupt-parent = <&intc>;
reg = < 0xf8891000 0x1000 0xf8893000 0x1000 >;
};
amba {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&intc>;
ranges;
i2c0: zynq-i2c@e0004000 {
compatible = "cdns,i2c-r1p10";
status = "disabled";
clocks = <&clkc 38>;
interrupt-parent = <&intc>;
interrupts = <0 25 4>;
reg = <0xe0004000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c1: zynq-i2c@e0005000 {
compatible = "cdns,i2c-r1p10";
status = "disabled";
clocks = <&clkc 39>;
interrupt-parent = <&intc>;
interrupts = <0 48 4>;
reg = <0xe0005000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
};
intc: interrupt-controller@f8f01000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>;
#address-cells = <1>;
interrupt-controller;
reg = <0xF8F01000 0x1000>,
<0xF8F00100 0x100>;
};
L2: cache-controller {
compatible = "arm,pl310-cache";
reg = <0xF8F02000 0x1000>;
arm,data-latency = <3 2 2>;
arm,tag-latency = <2 2 2>;
cache-unified;
cache-level = <2>;
};
uart0: uart@e0000000 {
compatible = "xlnx,xuartps";
status = "disabled";
clocks = <&clkc 23>, <&clkc 40>;
clock-names = "ref_clk", "aper_clk";
reg = <0xE0000000 0x1000>;
interrupts = <0 27 4>;
};
uart1: uart@e0001000 {
compatible = "xlnx,xuartps";
status = "disabled";
clocks = <&clkc 24>, <&clkc 41>;
clock-names = "ref_clk", "aper_clk";
reg = <0xE0001000 0x1000>;
interrupts = <0 50 4>;
};
gem0: ethernet@e000b000 {
compatible = "cdns,gem";
reg = <0xe000b000 0x4000>;
status = "disabled";
interrupts = <0 22 4>;
clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;
clock-names = "pclk", "hclk", "tx_clk";
};
gem1: ethernet@e000c000 {
compatible = "cdns,gem";
reg = <0xe000c000 0x4000>;
status = "disabled";
interrupts = <0 45 4>;
clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>;
clock-names = "pclk", "hclk", "tx_clk";
};
sdhci0: ps7-sdhci@e0100000 {
compatible = "arasan,sdhci-8.9a";
status = "disabled";
clock-names = "clk_xin", "clk_ahb";
clocks = <&clkc 21>, <&clkc 32>;
interrupt-parent = <&intc>;
interrupts = <0 24 4>;
reg = <0xe0100000 0x1000>;
} ;
sdhci1: ps7-sdhci@e0101000 {
compatible = "arasan,sdhci-8.9a";
status = "disabled";
clock-names = "clk_xin", "clk_ahb";
clocks = <&clkc 22>, <&clkc 33>;
interrupt-parent = <&intc>;
interrupts = <0 47 4>;
reg = <0xe0101000 0x1000>;
} ;
slcr: slcr@f8000000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "xlnx,zynq-slcr", "syscon";
reg = <0xF8000000 0x1000>;
ranges;
clkc: clkc@100 {
#clock-cells = <1>;
compatible = "xlnx,ps7-clkc";
ps-clk-frequency = <33333333>;
fclk-enable = <0>;
clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
"cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
"dci", "lqspi", "smc", "pcap", "gem0", "gem1",
"fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",
"sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1",
"dma", "usb0_aper", "usb1_aper", "gem0_aper",
"gem1_aper", "sdio0_aper", "sdio1_aper",
"spi0_aper", "spi1_aper", "can0_aper", "can1_aper",
"i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper",
"gpio_aper", "lqspi_aper", "smc_aper", "swdt",
"dbg_trc", "dbg_apb";
reg = <0x100 0x100>;
};
};
global_timer: timer@f8f00200 {
compatible = "arm,cortex-a9-global-timer";
reg = <0xf8f00200 0x20>;
interrupts = <1 11 0x301>;
interrupt-parent = <&intc>;
clocks = <&clkc 4>;
};
ttc0: ttc0@f8001000 {
interrupt-parent = <&intc>;
interrupts = < 0 10 4 0 11 4 0 12 4 >;
compatible = "cdns,ttc";
clocks = <&clkc 6>;
reg = <0xF8001000 0x1000>;
};
ttc1: ttc1@f8002000 {
interrupt-parent = <&intc>;
interrupts = < 0 37 4 0 38 4 0 39 4 >;
compatible = "cdns,ttc";
clocks = <&clkc 6>;
reg = <0xF8002000 0x1000>;
};
scutimer: scutimer@f8f00600 {
interrupt-parent = <&intc>;
interrupts = < 1 13 0x301 >;
compatible = "arm,cortex-a9-twd-timer";
reg = < 0xf8f00600 0x20 >;
clocks = <&clkc 4>;
} ;
};
};

9
arch/arm/dts/zynq-microzed.dts
View File

@ -11,4 +11,13 @@
/ {
model = "Zynq MicroZED Board";
compatible = "xlnx,zynq-microzed", "xlnx,zynq-7000";
aliases {
serial0 = &uart1;
};
memory {
device_type = "memory";
reg = <0 0x40000000>;
};
};

9
arch/arm/dts/zynq-zc702.dts
View File

@ -11,4 +11,13 @@
/ {
model = "Zynq ZC702 Board";
compatible = "xlnx,zynq-zc702", "xlnx,zynq-7000";
aliases {
serial0 = &uart1;
};
memory {
device_type = "memory";
reg = <0 0x40000000>;
};
};

9
arch/arm/dts/zynq-zc706.dts
View File

@ -11,4 +11,13 @@
/ {
model = "Zynq ZC706 Board";
compatible = "xlnx,zynq-zc706", "xlnx,zynq-7000";
aliases {
serial0 = &uart1;
};
memory {
device_type = "memory";
reg = <0 0x40000000>;
};
};

9
arch/arm/dts/zynq-zc770-xm010.dts
View File

@ -11,4 +11,13 @@
/ {
model = "Zynq ZC770 XM010 Board";
compatible = "xlnx,zynq-zc770-xm010", "xlnx,zynq-7000";
aliases {
serial0 = &uart1;
};
memory {
device_type = "memory";
reg = <0 0x40000000>;
};
};

9
arch/arm/dts/zynq-zc770-xm012.dts
View File

@ -11,4 +11,13 @@
/ {
model = "Zynq ZC770 XM012 Board";
compatible = "xlnx,zynq-zc770-xm012", "xlnx,zynq-7000";
aliases {
serial0 = &uart1;
};
memory {
device_type = "memory";
reg = <0 0x40000000>;
};
};

9
arch/arm/dts/zynq-zc770-xm013.dts
View File

@ -11,4 +11,13 @@
/ {
model = "Zynq ZC770 XM013 Board";
compatible = "xlnx,zynq-zc770-xm013", "xlnx,zynq-7000";
aliases {
serial0 = &uart0;
};
memory {
device_type = "memory";
reg = <0 0x40000000>;
};
};

9
arch/arm/dts/zynq-zed.dts
View File

@ -11,4 +11,13 @@
/ {
model = "Zynq ZED Board";
compatible = "xlnx,zynq-zed", "xlnx,zynq-7000";
aliases {
serial0 = &uart1;
};
memory {
device_type = "memory";
reg = <0 0x20000000>;
};
};

1
arch/arm/include/asm/arch-am33xx/sys_proto.h
View File

@ -11,6 +11,7 @@
#ifndef _SYS_PROTO_H_
#define _SYS_PROTO_H_
#include <linux/mtd/omap_gpmc.h>
#include <asm/ti-common/sys_proto.h>
#include <asm/arch/cpu.h>
#define BOARD_REV_ID 0x0

1
arch/arm/include/asm/arch-omap3/mem.h
View File

@ -344,6 +344,7 @@ enum {
* MAP - Map this CS to which address(GPMC address space)- Absolute address
* >>24 before being used.
*/
#define GPMC_SIZE_256M 0x0
#define GPMC_SIZE_128M 0x8
#define GPMC_SIZE_64M 0xC
#define GPMC_SIZE_32M 0xE

5
arch/arm/include/asm/arch-omap4/cpu.h
View File

@ -12,6 +12,8 @@
#include <asm/types.h>
#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
#include <asm/arch/hardware.h>
#ifndef __KERNEL_STRICT_NAMES
#ifndef __ASSEMBLY__
struct gptimer {
@ -57,9 +59,6 @@ struct watchdog {
#define TCLR_AR (0x1 << 1)
#define TCLR_PRE (0x1 << 5)
/* GPMC BASE */
#define GPMC_BASE (OMAP44XX_GPMC_BASE)
/* I2C base */
#define I2C_BASE1 (OMAP44XX_L4_PER_BASE + 0x70000)
#define I2C_BASE2 (OMAP44XX_L4_PER_BASE + 0x72000)

26
arch/arm/include/asm/arch-omap4/hardware.h Normal file
View File

@ -0,0 +1,26 @@
/*
* hardware.h
*
* hardware specific header
*
* Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __OMAP_HARDWARE_H
#define __OMAP_HARDWARE_H
#include <asm/arch/omap.h>
/*
* Common hardware definitions
*/
/* BCH Error Location Module */
#define ELM_BASE 0x48078000
/* GPMC Base address */
#define GPMC_BASE 0x50000000
#endif

62
arch/arm/include/asm/arch-omap4/mem.h Normal file
View File

@ -0,0 +1,62 @@
/*
* (C) Copyright 2006-2008
* Texas Instruments, <www.ti.com>
*
* Author
* Mansoor Ahamed <mansoor.ahamed@ti.com>
*
* Initial Code from:
* Richard Woodruff <r-woodruff2@ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _MEM_H_
#define _MEM_H_
/*
* GPMC settings -
* Definitions is as per the following format
* #define <PART>_GPMC_CONFIG<x> <value>
* Where:
* PART is the part name e.g. STNOR - Intel Strata Flash
* x is GPMC config registers from 1 to 6 (there will be 6 macros)
* Value is corresponding value
*
* For every valid PRCM configuration there should be only one definition of
* the same. if values are independent of the board, this definition will be
* present in this file if values are dependent on the board, then this should
* go into corresponding mem-boardName.h file
*
* Currently valid part Names are (PART):
* M_NAND - Micron NAND
* STNOR - STMicrolelctronics M29W128GL
*/
#define GPMC_SIZE_256M 0x0
#define GPMC_SIZE_128M 0x8
#define GPMC_SIZE_64M 0xC
#define GPMC_SIZE_32M 0xE
#define GPMC_SIZE_16M 0xF
#define M_NAND_GPMC_CONFIG1 0x00000800
#define M_NAND_GPMC_CONFIG2 0x001e1e00
#define M_NAND_GPMC_CONFIG3 0x001e1e00
#define M_NAND_GPMC_CONFIG4 0x16051807
#define M_NAND_GPMC_CONFIG5 0x00151e1e
#define M_NAND_GPMC_CONFIG6 0x16000f80
#define M_NAND_GPMC_CONFIG7 0x00000008
#define STNOR_GPMC_CONFIG1 0x00001200
#define STNOR_GPMC_CONFIG2 0x00101000
#define STNOR_GPMC_CONFIG3 0x00030301
#define STNOR_GPMC_CONFIG4 0x10041004
#define STNOR_GPMC_CONFIG5 0x000C1010
#define STNOR_GPMC_CONFIG6 0x08070280
#define STNOR_GPMC_CONFIG7 0x00000F48
/* max number of GPMC Chip Selects */
#define GPMC_MAX_CS 8
/* max number of GPMC regs */
#define GPMC_MAX_REG 7
#endif /* endif _MEM_H_ */

3
arch/arm/include/asm/arch-omap4/omap.h
View File

@ -60,9 +60,6 @@
/* Watchdog Timer2 - MPU watchdog */
#define WDT2_BASE (OMAP44XX_L4_WKUP_BASE + 0x14000)
/* GPMC */
#define OMAP44XX_GPMC_BASE 0x50000000
/*
* Hardware Register Details
*/

51
arch/arm/include/asm/arch-omap4/sys_proto.h
View File

@ -14,6 +14,7 @@
#include <asm/omap_common.h>
#include <linux/mtd/omap_gpmc.h>
#include <asm/arch/mux_omap4.h>
#include <asm/ti-common/sys_proto.h>
DECLARE_GLOBAL_DATA_PTR;
@ -53,54 +54,4 @@ int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data);
u32 warm_reset(void);
void force_emif_self_refresh(void);
void setup_warmreset_time(void);
static inline u32 running_from_sdram(void)
{
u32 pc;
asm volatile ("mov %0, pc" : "=r" (pc));
return ((pc >= OMAP44XX_DRAM_ADDR_SPACE_START) &&
(pc < OMAP44XX_DRAM_ADDR_SPACE_END));
}
static inline u8 uboot_loaded_by_spl(void)
{
/*
* u-boot can be running from sdram either because of configuration
* Header or by SPL. If because of CH, then the romcode sets the
* CHSETTINGS executed bit to true in the boot parameter structure that
* it passes to the bootloader.This parameter is stored in the ch_flags
* variable by both SPL and u-boot.Check out for CHSETTINGS, which is a
* mandatory section if CH is present.
*/
if ((gd->arch.omap_boot_params.ch_flags) & (CH_FLAGS_CHSETTINGS))
return 0;
else
return running_from_sdram();
}
/*
* The basic hardware init of OMAP(s_init()) can happen in 4
* different contexts:
* 1. SPL running from SRAM
* 2. U-Boot running from FLASH
* 3. Non-XIP U-Boot loaded to SDRAM by SPL
* 4. Non-XIP U-Boot loaded to SDRAM by ROM code using the
* Configuration Header feature
*
* This function finds this context.
* Defining as inline may help in compiling out unused functions in SPL
*/
static inline u32 omap_hw_init_context(void)
{
#ifdef CONFIG_SPL_BUILD
return OMAP_INIT_CONTEXT_SPL;
#else
if (uboot_loaded_by_spl())
return OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL;
else if (running_from_sdram())
return OMAP_INIT_CONTEXT_UBOOT_AFTER_CH;
else
return OMAP_INIT_CONTEXT_UBOOT_FROM_NOR;
#endif
}
#endif

5
arch/arm/include/asm/arch-omap5/cpu.h
View File

@ -14,6 +14,8 @@
#include <asm/types.h>
#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
#include <asm/arch/hardware.h>
#ifndef __KERNEL_STRICT_NAMES
#ifndef __ASSEMBLY__
struct gptimer {
@ -63,9 +65,6 @@ struct watchdog {
#define TCLR_AR (0x1 << 1)
#define TCLR_PRE (0x1 << 5)
/* GPMC BASE */
#define GPMC_BASE (OMAP54XX_GPMC_BASE)
/* I2C base */
#define I2C_BASE1 (OMAP54XX_L4_PER_BASE + 0x70000)
#define I2C_BASE2 (OMAP54XX_L4_PER_BASE + 0x72000)

26
arch/arm/include/asm/arch-omap5/hardware.h Normal file
View File

@ -0,0 +1,26 @@
/*
* hardware.h
*
* hardware specific header
*
* Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __OMAP_HARDWARE_H
#define __OMAP_HARDWARE_H
#include <asm/arch/omap.h>
/*
* Common hardware definitions
*/
/* BCH Error Location Module */
#define ELM_BASE 0x48078000
/* GPMC Base address */
#define GPMC_BASE 0x50000000
#endif

62
arch/arm/include/asm/arch-omap5/mem.h Normal file
View File

@ -0,0 +1,62 @@
/*
* (C) Copyright 2006-2008
* Texas Instruments, <www.ti.com>
*
* Author
* Mansoor Ahamed <mansoor.ahamed@ti.com>
*
* Initial Code from:
* Richard Woodruff <r-woodruff2@ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _MEM_H_
#define _MEM_H_
/*
* GPMC settings -
* Definitions is as per the following format
* #define <PART>_GPMC_CONFIG<x> <value>
* Where:
* PART is the part name e.g. STNOR - Intel Strata Flash
* x is GPMC config registers from 1 to 6 (there will be 6 macros)
* Value is corresponding value
*
* For every valid PRCM configuration there should be only one definition of
* the same. if values are independent of the board, this definition will be
* present in this file if values are dependent on the board, then this should
* go into corresponding mem-boardName.h file
*
* Currently valid part Names are (PART):
* M_NAND - Micron NAND
* STNOR - STMicrolelctronics M29W128GL
*/
#define GPMC_SIZE_256M 0x0
#define GPMC_SIZE_128M 0x8
#define GPMC_SIZE_64M 0xC
#define GPMC_SIZE_32M 0xE
#define GPMC_SIZE_16M 0xF
#define M_NAND_GPMC_CONFIG1 0x00000800
#define M_NAND_GPMC_CONFIG2 0x001e1e00
#define M_NAND_GPMC_CONFIG3 0x001e1e00
#define M_NAND_GPMC_CONFIG4 0x16051807
#define M_NAND_GPMC_CONFIG5 0x00151e1e
#define M_NAND_GPMC_CONFIG6 0x16000f80
#define M_NAND_GPMC_CONFIG7 0x00000008
#define STNOR_GPMC_CONFIG1 0x00001200
#define STNOR_GPMC_CONFIG2 0x00101000
#define STNOR_GPMC_CONFIG3 0x00030301
#define STNOR_GPMC_CONFIG4 0x10041004
#define STNOR_GPMC_CONFIG5 0x000C1010
#define STNOR_GPMC_CONFIG6 0x08070280
#define STNOR_GPMC_CONFIG7 0x00000F48
/* max number of GPMC Chip Selects */
#define GPMC_MAX_CS 8
/* max number of GPMC regs */
#define GPMC_MAX_REG 7
#endif /* endif _MEM_H_ */

9
arch/arm/include/asm/arch-omap5/omap.h
View File

@ -23,11 +23,6 @@
#define OMAP54XX_L4_WKUP_BASE 0x4Ae00000
#define OMAP54XX_L4_PER_BASE 0x48000000
#define OMAP54XX_DRAM_ADDR_SPACE_START 0x80000000
#define OMAP54XX_DRAM_ADDR_SPACE_END 0xFFFFFFFF
#define DRAM_ADDR_SPACE_START OMAP54XX_DRAM_ADDR_SPACE_START
#define DRAM_ADDR_SPACE_END OMAP54XX_DRAM_ADDR_SPACE_END
/* CONTROL ID CODE */
#define CONTROL_CORE_ID_CODE 0x4A002204
#define CONTROL_WKUP_ID_CODE 0x4AE0C204
@ -45,6 +40,7 @@
#define OMAP5432_CONTROL_ID_CODE_ES2_0 0x1B99802F
#define DRA752_CONTROL_ID_CODE_ES1_0 0x0B99002F
#define DRA752_CONTROL_ID_CODE_ES1_1 0x1B99002F
#define DRA722_CONTROL_ID_CODE_ES1_0 0x0B9BC02F
/* UART */
#define UART1_BASE (OMAP54XX_L4_PER_BASE + 0x6a000)
@ -60,9 +56,6 @@
/* Watchdog Timer2 - MPU watchdog */
#define WDT2_BASE (OMAP54XX_L4_WKUP_BASE + 0x14000)
/* GPMC */
#define OMAP54XX_GPMC_BASE 0x50000000
/* QSPI */
#define QSPI_BASE 0x4B300000

50
arch/arm/include/asm/arch-omap5/sys_proto.h
View File

@ -14,6 +14,7 @@
#include <asm/omap_common.h>
#include <linux/mtd/omap_gpmc.h>
#include <asm/arch/clock.h>
#include <asm/ti-common/sys_proto.h>
DECLARE_GLOBAL_DATA_PTR;
@ -56,55 +57,6 @@ void get_ioregs(const struct ctrl_ioregs **regs);
void srcomp_enable(void);
void setup_warmreset_time(void);
static inline u32 running_from_sdram(void)
{
u32 pc;
asm volatile ("mov %0, pc" : "=r" (pc));
return ((pc >= OMAP54XX_DRAM_ADDR_SPACE_START) &&
(pc < OMAP54XX_DRAM_ADDR_SPACE_END));
}
static inline u8 uboot_loaded_by_spl(void)
{
/*
* u-boot can be running from sdram either because of configuration
* Header or by SPL. If because of CH, then the romcode sets the
* CHSETTINGS executed bit to true in the boot parameter structure that
* it passes to the bootloader.This parameter is stored in the ch_flags
* variable by both SPL and u-boot.Check out for CHSETTINGS, which is a
* mandatory section if CH is present.
*/
if ((gd->arch.omap_boot_params.ch_flags) & (CH_FLAGS_CHSETTINGS))
return 0;
else
return running_from_sdram();
}
/*
* The basic hardware init of OMAP(s_init()) can happen in 4
* different contexts:
* 1. SPL running from SRAM
* 2. U-Boot running from FLASH
* 3. Non-XIP U-Boot loaded to SDRAM by SPL
* 4. Non-XIP U-Boot loaded to SDRAM by ROM code using the
* Configuration Header feature
*
* This function finds this context.
* Defining as inline may help in compiling out unused functions in SPL
*/
static inline u32 omap_hw_init_context(void)
{
#ifdef CONFIG_SPL_BUILD
return OMAP_INIT_CONTEXT_SPL;
#else
if (uboot_loaded_by_spl())
return OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL;
else if (running_from_sdram())
return OMAP_INIT_CONTEXT_UBOOT_AFTER_CH;
else
return OMAP_INIT_CONTEXT_UBOOT_FROM_NOR;
#endif
}
static inline u32 div_round_up(u32 num, u32 den)
{
return (num + den - 1)/den;

6
arch/arm/include/asm/arch-rmobile/r8a7790-gpio.h
View File

@ -1,5 +1,5 @@
#ifndef __ASM_R8A7790_H__
#define __ASM_R8A7790_H__
#ifndef __ASM_R8A7790_GPIO_H__
#define __ASM_R8A7790_GPIO_H__
/* Pin Function Controller:
* GPIO_FN_xx - GPIO used to select pin function
@ -384,4 +384,4 @@ enum {
GPIO_FN_TCLK1_B,
};
#endif /* __ASM_R8A7790_H__ */
#endif /* __ASM_R8A7790_GPIO_H__ */

6
arch/arm/include/asm/arch-rmobile/r8a7791-gpio.h
View File

@ -1,5 +1,5 @@
#ifndef __ASM_R8A7791_H__
#define __ASM_R8A7791_H__
#ifndef __ASM_R8A7791_GPIO_H__
#define __ASM_R8A7791_GPIO_H__
/* Pin Function Controller:
* GPIO_FN_xx - GPIO used to select pin function
@ -435,4 +435,4 @@ enum {
GPIO_FN_MLB_DAT, GPIO_FN_CAN1_RX_B,
};
#endif /* __ASM_R8A7791_H__ */
#endif /* __ASM_R8A7791_GPIO_H__ */

1
arch/arm/include/asm/arch-rmobile/r8a7791.h
View File

@ -45,6 +45,7 @@
#define DBSC3_1_QOS_W13_BASE 0xE67A2D00
#define DBSC3_1_QOS_W14_BASE 0xE67A2E00
#define DBSC3_1_QOS_W15_BASE 0xE67A2F00
#define DBSC3_1_DBADJ2 0xE67A00C8
#define R8A7791_CUT_ES2X 2
#define IS_R8A7791_ES2() \

8
arch/arm/include/asm/arch-rmobile/rcar-base.h
View File

@ -21,6 +21,14 @@
#define GPIO5_BASE 0xE6055000
#define SH_QSPI_BASE 0xE6B10000
/* SCIF */
#define SCIF0_BASE 0xE6E60000
#define SCIF1_BASE 0xE6E68000
#define SCIF2_BASE 0xE6E58000
#define SCIF3_BASE 0xE6EA8000
#define SCIF4_BASE 0xE6EE0000
#define SCIF5_BASE 0xE6EE8000
#define S3C_BASE 0xE6784000
#define S3C_INT_BASE 0xE6784A00
#define S3C_MEDIA_BASE 0xE6784B00

13
arch/arm/include/asm/arch-zynq/hardware.h
View File

@ -22,9 +22,12 @@
#define ZYNQ_SPI_BASEADDR0 0xE0006000
#define ZYNQ_SPI_BASEADDR1 0xE0007000
#define ZYNQ_DDRC_BASEADDR 0xF8006000
#define ZYNQ_EFUSE_BASEADDR 0xF800D000
#define ZYNQ_USB_BASEADDR0 0xE0002000
#define ZYNQ_USB_BASEADDR1 0xE0003000
/* Bootmode setting values */
#define ZYNQ_BM_MASK 0xF
#define ZYNQ_BM_MASK 0x7
#define ZYNQ_BM_NOR 0x2
#define ZYNQ_BM_SD 0x5
#define ZYNQ_BM_JTAG 0x0
@ -130,4 +133,12 @@ struct ddrc_regs {
};
#define ddrc_base ((struct ddrc_regs *)ZYNQ_DDRC_BASEADDR)
struct efuse_reg {
u32 reserved1[4];
u32 status;
u32 reserved2[3];
};
#define efuse_base ((struct efuse_reg *)ZYNQ_EFUSE_BASEADDR)
#endif /* _ASM_ARCH_HARDWARE_H */

2
arch/arm/include/asm/arch-zynq/sys_proto.h
View File

@ -15,7 +15,9 @@ extern void zynq_slcr_devcfg_disable(void);
extern void zynq_slcr_devcfg_enable(void);
extern u32 zynq_slcr_get_boot_mode(void);
extern u32 zynq_slcr_get_idcode(void);
extern int zynq_slcr_get_mio_pin_status(const char *periph);
extern void zynq_ddrc_init(void);
extern unsigned int zynq_get_silicon_version(void);
/* Driver extern functions */
extern int zynq_sdhci_init(u32 regbase);

7
arch/arm/include/asm/omap_common.h
View File

@ -576,12 +576,6 @@ s8 abb_setup_ldovbb(u32 fuse, u32 ldovbb);
void usb_fake_mac_from_die_id(u32 *id);
/* HW Init Context */
#define OMAP_INIT_CONTEXT_SPL 0
#define OMAP_INIT_CONTEXT_UBOOT_FROM_NOR 1
#define OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL 2
#define OMAP_INIT_CONTEXT_UBOOT_AFTER_CH 3
/* ABB */
#define OMAP_ABB_NOMINAL_OPP 0
#define OMAP_ABB_FAST_OPP 1
@ -645,6 +639,7 @@ static inline u8 is_dra7xx(void)
/* DRA7XX */
#define DRA752_ES1_0 0x07520100
#define DRA752_ES1_1 0x07520110
#define DRA722_ES1_0 0x07220100
/*
* SRAM scratch space entries

72
arch/arm/include/asm/ti-common/sys_proto.h Normal file
View File

@ -0,0 +1,72 @@
/*
* (C) Copyright 2014
* Texas Instruments, <www.ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _TI_COMMON_SYS_PROTO_H_
#define _TI_COMMON_SYS_PROTO_H_
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_OMAP_COMMON
#define TI_ARMV7_DRAM_ADDR_SPACE_START 0x80000000
#define TI_ARMV7_DRAM_ADDR_SPACE_END 0xFFFFFFFF
#define OMAP_INIT_CONTEXT_SPL 0
#define OMAP_INIT_CONTEXT_UBOOT_FROM_NOR 1
#define OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL 2
#define OMAP_INIT_CONTEXT_UBOOT_AFTER_CH 3
static inline u32 running_from_sdram(void)
{
u32 pc;
asm volatile ("mov %0, pc" : "=r" (pc));
return ((pc >= TI_ARMV7_DRAM_ADDR_SPACE_START) &&
(pc < TI_ARMV7_DRAM_ADDR_SPACE_END));
}
static inline u8 uboot_loaded_by_spl(void)
{
/*
* u-boot can be running from sdram either because of configuration
* Header or by SPL. If because of CH, then the romcode sets the
* CHSETTINGS executed bit to true in the boot parameter structure that
* it passes to the bootloader.This parameter is stored in the ch_flags
* variable by both SPL and u-boot.Check out for CHSETTINGS, which is a
* mandatory section if CH is present.
*/
if ((gd->arch.omap_boot_params.ch_flags) & (CH_FLAGS_CHSETTINGS))
return 0;
else
return running_from_sdram();
}
/*
* The basic hardware init of OMAP(s_init()) can happen in 4
* different contexts:
* 1. SPL running from SRAM
* 2. U-Boot running from FLASH
* 3. Non-XIP U-Boot loaded to SDRAM by SPL
* 4. Non-XIP U-Boot loaded to SDRAM by ROM code using the
* Configuration Header feature
*
* This function finds this context.
* Defining as inline may help in compiling out unused functions in SPL
*/
static inline u32 omap_hw_init_context(void)
{
#ifdef CONFIG_SPL_BUILD
return OMAP_INIT_CONTEXT_SPL;
#else
if (uboot_loaded_by_spl())
return OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL;
else if (running_from_sdram())
return OMAP_INIT_CONTEXT_UBOOT_AFTER_CH;
else
return OMAP_INIT_CONTEXT_UBOOT_FROM_NOR;
#endif
}
#endif
#endif

10
board/compulab/cm_t54/Makefile Normal file
View File

@ -0,0 +1,10 @@
#
# Copyright (C) 2014 Compulab Ltd - http://compulab.co.il/
#
# Author: Dmitry Lifshitz <lifshitz@compulab.co.il>
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += cm_t54.o
obj-$(CONFIG_SPL_BUILD) += mux.o spl.o

262
board/compulab/cm_t54/cm_t54.c Normal file
View File

@ -0,0 +1,262 @@
/*
* Board functions for Compulab CM-T54 board
*
* Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
*
* Author: Dmitry Lifshitz <lifshitz@compulab.co.il>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <fdt_support.h>
#include <usb.h>
#include <mmc.h>
#include <palmas.h>
#include <spl.h>
#include <asm/gpio.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/clock.h>
#include <asm/arch/ehci.h>
#include <asm/ehci-omap.h>
#include "../common/eeprom.h"
#define DIE_ID_REG_BASE (OMAP54XX_L4_CORE_BASE + 0x2000)
#define DIE_ID_REG_OFFSET 0x200
DECLARE_GLOBAL_DATA_PTR;
#if !defined(CONFIG_SPL_BUILD)
inline void set_muxconf_regs_essential(void){};
#endif
const struct omap_sysinfo sysinfo = {
"Board: CM-T54\n"
};
/*
* Routine: board_init
* Description: hardware init.
*/
int board_init(void)
{
gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100); /* boot param addr */
return 0;
}
/*
* Routine: cm_t54_palmas_regulator_set
* Description: select voltage and turn on/off Palmas PMIC regulator.
*/
static int cm_t54_palmas_regulator_set(u8 vreg, u8 vval, u8 creg, u8 cval)
{
int err;
/* Setup voltage */
err = palmas_i2c_write_u8(TWL603X_CHIP_P1, vreg, vval);
if (err) {
printf("cm_t54: could not set regulator 0x%02x voltage : %d\n",
vreg, err);
return err;
}
/* Turn on/off regulator */
err = palmas_i2c_write_u8(TWL603X_CHIP_P1, creg, cval);
if (err) {
printf("cm_t54: could not turn on/off regulator 0x%02x : %d\n",
creg, err);
return err;
}
return 0;
}
/*
* Routine: mmc_get_env_part
* Description: setup environment storage device partition.
*/
#ifdef CONFIG_SYS_MMC_ENV_PART
uint mmc_get_env_part(struct mmc *mmc)
{
u32 bootmode = gd->arch.omap_boot_params.omap_bootmode;
uint bootpart = CONFIG_SYS_MMC_ENV_PART;
/*
* If booted from eMMC boot partition then force eMMC
* FIRST boot partition to be env storage
*/
if (bootmode == BOOT_DEVICE_MMC2_2)
bootpart = 1;
return bootpart;
}
#endif
#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
#define SB_T54_CD_GPIO 228
#define SB_T54_WP_GPIO 229
int board_mmc_getcd(struct mmc *mmc)
{
return !gpio_get_value(SB_T54_CD_GPIO);
}
int board_mmc_init(bd_t *bis)
{
int ret0, ret1;
ret0 = omap_mmc_init(0, 0, 0, -1, SB_T54_WP_GPIO);
if (ret0)
printf("cm_t54: failed to initialize mmc0\n");
ret1 = omap_mmc_init(1, 0, 0, -1, -1);
if (ret1)
printf("cm_t54: failed to initialize mmc1\n");
if (ret0 && ret1)
return -1;
return 0;
}
#endif
#ifdef CONFIG_USB_HOST_ETHER
void ft_board_setup(void *blob, bd_t *bd)
{
uint8_t enetaddr[6];
/* MAC addr */
if (eth_getenv_enetaddr("usbethaddr", enetaddr)) {
fdt_find_and_setprop(blob, "/smsc95xx@0", "mac-address",
enetaddr, 6, 1);
}
}
static void generate_mac_addr(uint8_t *enetaddr)
{
int reg;
reg = DIE_ID_REG_BASE + DIE_ID_REG_OFFSET;
/*
* create a fake MAC address from the processor ID code.
* first byte is 0x02 to signify locally administered.
*/
enetaddr[0] = 0x02;
enetaddr[1] = readl(reg + 0x10) & 0xff;
enetaddr[2] = readl(reg + 0xC) & 0xff;
enetaddr[3] = readl(reg + 0x8) & 0xff;
enetaddr[4] = readl(reg) & 0xff;
enetaddr[5] = (readl(reg) >> 8) & 0xff;
}
/*
* Routine: handle_mac_address
* Description: prepare MAC address for on-board Ethernet.
*/
static int handle_mac_address(void)
{
uint8_t enetaddr[6];
int ret;
ret = eth_getenv_enetaddr("usbethaddr", enetaddr);
if (ret)
return 0;
ret = cl_eeprom_read_mac_addr(enetaddr);
if (!ret || !is_valid_ether_addr(enetaddr))
generate_mac_addr(enetaddr);
if (!is_valid_ether_addr(enetaddr))
return -1;
return eth_setenv_enetaddr("usbethaddr", enetaddr);
}
int board_eth_init(bd_t *bis)
{
return handle_mac_address();
}
#endif
#ifdef CONFIG_USB_EHCI
static struct omap_usbhs_board_data usbhs_bdata = {
.port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
.port_mode[1] = OMAP_EHCI_PORT_MODE_HSIC,
.port_mode[2] = OMAP_EHCI_PORT_MODE_HSIC,
};
static void setup_host_clocks(bool enable)
{
int usbhost_clk = OPTFCLKEN_HSIC60M_P3_CLK |
OPTFCLKEN_HSIC480M_P3_CLK |
OPTFCLKEN_HSIC60M_P2_CLK |
OPTFCLKEN_HSIC480M_P2_CLK |
OPTFCLKEN_UTMI_P3_CLK |
OPTFCLKEN_UTMI_P2_CLK;
int usbtll_clk = OPTFCLKEN_USB_CH1_CLK_ENABLE |
OPTFCLKEN_USB_CH2_CLK_ENABLE;
int usbhub_clk = CKOBUFFER_CLK_ENABLE_MASK;
if (enable) {
/* Enable port 2 and 3 clocks*/
setbits_le32((*prcm)->cm_l3init_hsusbhost_clkctrl, usbhost_clk);
/* Enable port 2 and 3 usb host ports tll clocks*/
setbits_le32((*prcm)->cm_l3init_hsusbtll_clkctrl, usbtll_clk);
/* Request FREF_XTAL_CLK clock for HSIC USB Hub */
setbits_le32((*ctrl)->control_ckobuffer, usbhub_clk);
} else {
clrbits_le32((*ctrl)->control_ckobuffer, usbhub_clk);
clrbits_le32((*prcm)->cm_l3init_hsusbtll_clkctrl, usbtll_clk);
clrbits_le32((*prcm)->cm_l3init_hsusbhost_clkctrl, usbhost_clk);
}
}
int ehci_hcd_init(int index, enum usb_init_type init,
struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
int ret;
/* VCC_3V3_ETH */
cm_t54_palmas_regulator_set(SMPS9_VOLTAGE, SMPS_VOLT_3V3, SMPS9_CTRL,
SMPS_MODE_SLP_AUTO | SMPS_MODE_ACT_AUTO);
setup_host_clocks(true);
ret = omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
if (ret < 0)
printf("cm_t54: Failed to initialize ehci : %d\n", ret);
return ret;
}
int ehci_hcd_stop(void)
{
int ret = omap_ehci_hcd_stop();
setup_host_clocks(false);
cm_t54_palmas_regulator_set(SMPS9_VOLTAGE, SMPS_VOLT_OFF,
SMPS9_CTRL, SMPS_MODE_SLP_AUTO);
return ret;
}
void usb_hub_reset_devices(int port)
{
/* The LAN9730 needs to be reset after the port power has been set. */
if (port == 3) {
gpio_direction_output(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO, 0);
udelay(10);
gpio_direction_output(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO, 1);
}
}
#endif

94
board/compulab/cm_t54/mux.c Normal file
View File

@ -0,0 +1,94 @@
/*
* Pinmux configuration for Compulab CM-T54 board
*
* Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
*
* Author: Dmitry Lifshitz <lifshitz@compulab.co.il>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _CM_T54_MUX_DATA_H
#define _CM_T54_MUX_DATA_H
#include <asm/arch/mux_omap5.h>
#include <asm/arch/sys_proto.h>
const struct pad_conf_entry core_padconf_array_essential[] = {
/* MMC1 - SD CARD */
{SDCARD_CLK, (PTU | IEN | M0)}, /* SDCARD_CLK */
{SDCARD_CMD, (PTU | IEN | M0)}, /* SDCARD_CMD */
{SDCARD_DATA0, (PTU | IEN | M0)}, /* SDCARD_DATA0 */
{SDCARD_DATA1, (PTU | IEN | M0)}, /* SDCARD_DATA1 */
{SDCARD_DATA2, (PTU | IEN | M0)}, /* SDCARD_DATA2 */
{SDCARD_DATA3, (PTU | IEN | M0)}, /* SDCARD_DATA3 */
/* SD CARD CD and WP GPIOs*/
{TIMER5_PWM_EVT, (PTU | IEN | M6)}, /* GPIO8_228 */
{TIMER6_PWM_EVT, (PTU | IEN | M6)}, /* GPIO8_229 */
/* MMC2 - eMMC */
{EMMC_CLK, (PTU | IEN | M0)}, /* EMMC_CLK */
{EMMC_CMD, (PTU | IEN | M0)}, /* EMMC_CMD */
{EMMC_DATA0, (PTU | IEN | M0)}, /* EMMC_DATA0 */
{EMMC_DATA1, (PTU | IEN | M0)}, /* EMMC_DATA1 */
{EMMC_DATA2, (PTU | IEN | M0)}, /* EMMC_DATA2 */
{EMMC_DATA3, (PTU | IEN | M0)}, /* EMMC_DATA3 */
{EMMC_DATA4, (PTU | IEN | M0)}, /* EMMC_DATA4 */
{EMMC_DATA5, (PTU | IEN | M0)}, /* EMMC_DATA5 */
{EMMC_DATA6, (PTU | IEN | M0)}, /* EMMC_DATA6 */
{EMMC_DATA7, (PTU | IEN | M0)}, /* EMMC_DATA7 */
/* UART4 */
{I2C5_SCL, (PTU | IEN | M2)}, /* UART4_RX */
{I2C5_SDA, (M2)}, /* UART4_TX */
/* Led */
{HSI2_CAFLAG, (PTU | M6)}, /* GPIO3_80 */
/* I2C1 */
{I2C1_PMIC_SCL, (PTU | IEN | M0)}, /* I2C1_PMIC_SCL */
{I2C1_PMIC_SDA, (PTU | IEN | M0)}, /* I2C1_PMIC_SDA */
/* USBB2, USBB3 */
{USBB2_HSIC_STROBE, (PTU | IEN | M0)}, /* USBB2_HSIC_STROBE */
{USBB2_HSIC_DATA, (PTU | IEN | M0)}, /* USBB2_HSIC_DATA */
{USBB3_HSIC_STROBE, (PTU | IEN | M0)}, /* USBB3_HSIC_STROBE */
{USBB3_HSIC_DATA, (PTU | IEN | M0)}, /* USBB3_HSIC_DATA */
/* USB Hub and USB Eth reset GPIOs */
{HSI2_CAREADY, (PTD | M6)}, /* GPIO3_76 */
{HSI2_ACDATA, (PTD | M6)}, /* GPIO3_83 */
/* I2C4 */
{I2C4_SCL, (PTU | IEN | M0)}, /* I2C4_SCL */
{I2C4_SDA, (PTU | IEN | M0)}, /* I2C4_SDA */
};
const struct pad_conf_entry wkup_padconf_array_essential[] = {
{SR_PMIC_SCL, (PTU | IEN | M0)}, /* SR_PMIC_SCL */
{SR_PMIC_SDA, (PTU | IEN | M0)}, /* SR_PMIC_SDA */
{SYS_32K, (IEN | M0)}, /* SYS_32K */
/* USB Hub clock */
{FREF_CLK1_OUT, (PTD | IEN | M0)}, /* FREF_CLK1_OUT */
};
/*
* Routine: set_muxconf_regs_essential
* Description: setup board pinmux configuration.
*/
void set_muxconf_regs_essential(void)
{
do_set_mux((*ctrl)->control_padconf_core_base,
core_padconf_array_essential,
sizeof(core_padconf_array_essential) /
sizeof(struct pad_conf_entry));
do_set_mux((*ctrl)->control_padconf_wkup_base,
wkup_padconf_array_essential,
sizeof(wkup_padconf_array_essential) /
sizeof(struct pad_conf_entry));
}
#endif /* _CM_T54_MUX_DATA_H */

66
board/compulab/cm_t54/spl.c Normal file
View File

@ -0,0 +1,66 @@
/*
* SPL specific code for Compulab CM-T54 board
*
* Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
*
* Author: Dmitry Lifshitz <lifshitz@compulab.co.il>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <asm/emif.h>
const struct emif_regs emif_regs_ddr3_532_mhz_cm_t54 = {
#if defined(CONFIG_DRAM_1G) || defined(CONFIG_DRAM_512M)
.sdram_config_init = 0x618522B2,
.sdram_config = 0x618522B2,
#elif defined(CONFIG_DRAM_2G)
.sdram_config_init = 0x618522BA,
.sdram_config = 0x618522BA,
#endif
.sdram_config2 = 0x0,
.ref_ctrl = 0x00001040,
.sdram_tim1 = 0xEEEF36F3,
.sdram_tim2 = 0x348F7FDA,
.sdram_tim3 = 0x027F88A8,
.read_idle_ctrl = 0x00050000,
.zq_config = 0x1007190B,
.temp_alert_config = 0x00000000,
.emif_ddr_phy_ctlr_1_init = 0x0030400B,
.emif_ddr_phy_ctlr_1 = 0x0034400B,
.emif_ddr_ext_phy_ctrl_1 = 0x04040100,
.emif_ddr_ext_phy_ctrl_2 = 0x00000000,
.emif_ddr_ext_phy_ctrl_3 = 0x00000000,
.emif_ddr_ext_phy_ctrl_4 = 0x00000000,
.emif_ddr_ext_phy_ctrl_5 = 0x4350D435,
.emif_rd_wr_lvl_rmp_win = 0x00000000,
.emif_rd_wr_lvl_rmp_ctl = 0x80000000,
.emif_rd_wr_lvl_ctl = 0x00000000,
.emif_rd_wr_exec_thresh = 0x40000305,
};
const struct dmm_lisa_map_regs lisa_map_cm_t54 = {
.dmm_lisa_map_0 = 0x0,
.dmm_lisa_map_1 = 0x0,
#ifdef CONFIG_DRAM_2G
.dmm_lisa_map_2 = 0x80740300,
#elif defined(CONFIG_DRAM_1G)
.dmm_lisa_map_2 = 0x80640300,
#elif defined(CONFIG_DRAM_512M)
.dmm_lisa_map_2 = 0x80500100,
#endif
.dmm_lisa_map_3 = 0x00000000,
.is_ma_present = 0x1,
};
void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
{
*regs = &emif_regs_ddr3_532_mhz_cm_t54;
}
void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
{
*dmm_lisa_regs = &lisa_map_cm_t54;
}

2
board/compulab/common/Makefile
View File

@ -6,5 +6,5 @@
# SPDX-License-Identifier: GPL-2.0+
#
obj-$(CONFIG_SYS_I2C_OMAP34XX) += eeprom.o
obj-$(CONFIG_SYS_I2C) += eeprom.o
obj-$(CONFIG_LCD) += omap3_display.o

5
board/compulab/common/eeprom.c
View File

@ -10,6 +10,11 @@
#include <common.h>
#include <i2c.h>
#ifndef CONFIG_SYS_I2C_EEPROM_ADDR
# define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
# define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#endif
#define EEPROM_LAYOUT_VER_OFFSET 44
#define BOARD_SERIAL_OFFSET 20
#define BOARD_SERIAL_OFFSET_LEGACY 8

2
board/compulab/common/eeprom.h
View File

@ -10,7 +10,7 @@
#ifndef _EEPROM_
#define _EEPROM_
#ifdef CONFIG_SYS_I2C_OMAP34XX
#ifdef CONFIG_SYS_I2C
int cl_eeprom_read_mac_addr(uchar *buf);
u32 cl_eeprom_get_board_rev(void);
#else

8
board/gumstix/duovero/Makefile Normal file
View File

@ -0,0 +1,8 @@
#
# (C) Copyright 2000, 2001, 2002
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y := duovero.o

264
board/gumstix/duovero/duovero.c Normal file
View File

@ -0,0 +1,264 @@
/*
* (C) Copyright 2013
* Gumstix Inc. <www.gumstix.com>
* Maintainer: Ash Charles <ash@gumstix.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <netdev.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/mmc_host_def.h>
#include <twl6030.h>
#include <asm/emif.h>
#include <asm/arch/clock.h>
#include <asm/arch/gpio.h>
#include <asm/gpio.h>
#include "duovero_mux_data.h"
#define WIFI_EN 43
#if defined(CONFIG_CMD_NET)
#define SMSC_NRESET 45
static void setup_net_chip(void);
#endif
#ifdef CONFIG_USB_EHCI
#include <usb.h>
#include <asm/arch/ehci.h>
#include <asm/ehci-omap.h>
#endif
DECLARE_GLOBAL_DATA_PTR;
const struct omap_sysinfo sysinfo = {
"Board: duovero\n"
};
struct omap4_scrm_regs *const scrm = (struct omap4_scrm_regs *)0x4a30a000;
/**
* @brief board_init
*
* @return 0
*/
int board_init(void)
{
gpmc_init();
gd->bd->bi_arch_number = MACH_TYPE_OMAP4_DUOVERO;
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
return 0;
}
/**
* @brief misc_init_r - Configure board specific configurations
* such as power configurations, ethernet initialization as phase2 of
* boot sequence
*
* @return 0
*/
int misc_init_r(void)
{
int ret = 0;
u8 val;
/* wifi setup: first enable 32Khz clock from 6030 pmic */
val = 0xe1;
ret = i2c_write(TWL6030_CHIP_PM, 0xbe, 1, &val, 1);
if (ret)
printf("Failed to enable 32Khz clock to wifi module\n");
/* then setup WIFI_EN as an output pin and send reset pulse */
if (!gpio_request(WIFI_EN, "")) {
gpio_direction_output(WIFI_EN, 0);
gpio_set_value(WIFI_EN, 1);
udelay(1);
gpio_set_value(WIFI_EN, 0);
udelay(1);
gpio_set_value(WIFI_EN, 1);
}
#if defined(CONFIG_CMD_NET)
setup_net_chip();
#endif
return 0;
}
void set_muxconf_regs_essential(void)
{
do_set_mux((*ctrl)->control_padconf_core_base,
core_padconf_array_essential,
sizeof(core_padconf_array_essential) /
sizeof(struct pad_conf_entry));
do_set_mux((*ctrl)->control_padconf_wkup_base,
wkup_padconf_array_essential,
sizeof(wkup_padconf_array_essential) /
sizeof(struct pad_conf_entry));
do_set_mux((*ctrl)->control_padconf_core_base,
core_padconf_array_non_essential,
sizeof(core_padconf_array_non_essential) /
sizeof(struct pad_conf_entry));
do_set_mux((*ctrl)->control_padconf_wkup_base,
wkup_padconf_array_non_essential,
sizeof(wkup_padconf_array_non_essential) /
sizeof(struct pad_conf_entry));
}
#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
int board_mmc_init(bd_t *bis)
{
return omap_mmc_init(0, 0, 0, -1, -1);
}
#endif
#if defined(CONFIG_CMD_NET)
#define GPMC_SIZE_16M 0xF
#define GPMC_BASEADDR_MASK 0x3F
#define GPMC_CS_ENABLE 0x1
static void enable_gpmc_net_config(const u32 *gpmc_config, struct gpmc_cs *cs,
u32 base, u32 size)
{
writel(0, &cs->config7);
sdelay(1000);
/* Delay for settling */
writel(gpmc_config[0], &cs->config1);
writel(gpmc_config[1], &cs->config2);
writel(gpmc_config[2], &cs->config3);
writel(gpmc_config[3], &cs->config4);
writel(gpmc_config[4], &cs->config5);
writel(gpmc_config[5], &cs->config6);
/*
* Enable the config. size is the CS size and goes in
* bits 11:8. We set bit 6 to enable this CS and the base
* address goes into bits 5:0.
*/
writel((size << 8) | (GPMC_CS_ENABLE << 6) |
((base >> 24) & GPMC_BASEADDR_MASK),
&cs->config7);
sdelay(2000);
}
/* GPMC CS configuration for an SMSC LAN9221 ethernet controller */
#define NET_LAN9221_GPMC_CONFIG1 0x2a001203
#define NET_LAN9221_GPMC_CONFIG2 0x000a0a02
#define NET_LAN9221_GPMC_CONFIG3 0x00020200
#define NET_LAN9221_GPMC_CONFIG4 0x0a030a03
#define NET_LAN9221_GPMC_CONFIG5 0x000a0a0a
#define NET_LAN9221_GPMC_CONFIG6 0x8a070707
#define NET_LAN9221_GPMC_CONFIG7 0x00000f6c
/* GPMC definitions for LAN9221 chips on expansion boards */
static const u32 gpmc_lan_config[] = {
NET_LAN9221_GPMC_CONFIG1,
NET_LAN9221_GPMC_CONFIG2,
NET_LAN9221_GPMC_CONFIG3,
NET_LAN9221_GPMC_CONFIG4,
NET_LAN9221_GPMC_CONFIG5,
NET_LAN9221_GPMC_CONFIG6,
/*CONFIG7- computed as params */
};
/*
* Routine: setup_net_chip
* Description: Setting up the configuration GPMC registers specific to the
* Ethernet hardware.
*/
static void setup_net_chip(void)
{
enable_gpmc_net_config(gpmc_lan_config, &gpmc_cfg->cs[5], 0x2C000000,
GPMC_SIZE_16M);
/* Make GPIO SMSC_NRESET as output pin and send reset pulse */
if (!gpio_request(SMSC_NRESET, "")) {
gpio_direction_output(SMSC_NRESET, 0);
gpio_set_value(SMSC_NRESET, 1);
udelay(1);
gpio_set_value(SMSC_NRESET, 0);
udelay(1);
gpio_set_value(SMSC_NRESET, 1);
}
}
#endif
int board_eth_init(bd_t *bis)
{
int rc = 0;
#ifdef CONFIG_SMC911X
rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
#endif
return rc;
}
#ifdef CONFIG_USB_EHCI
static struct omap_usbhs_board_data usbhs_bdata = {
.port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
.port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED,
.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
};
int ehci_hcd_init(int index, enum usb_init_type init,
struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
int ret;
unsigned int utmi_clk;
u32 auxclk, altclksrc;
/* Now we can enable our port clocks */
utmi_clk = readl((void *)CM_L3INIT_HSUSBHOST_CLKCTRL);
utmi_clk |= HSUSBHOST_CLKCTRL_CLKSEL_UTMI_P1_MASK;
setbits_le32((void *)CM_L3INIT_HSUSBHOST_CLKCTRL, utmi_clk);
auxclk = readl(&scrm->auxclk3);
/* Select sys_clk */
auxclk &= ~AUXCLK_SRCSELECT_MASK;
auxclk |= AUXCLK_SRCSELECT_SYS_CLK << AUXCLK_SRCSELECT_SHIFT;
/* Set the divisor to 2 */
auxclk &= ~AUXCLK_CLKDIV_MASK;
auxclk |= AUXCLK_CLKDIV_2 << AUXCLK_CLKDIV_SHIFT;
/* Request auxilary clock #3 */
auxclk |= AUXCLK_ENABLE_MASK;
writel(auxclk, &scrm->auxclk3);
altclksrc = readl(&scrm->altclksrc);
/* Activate alternate system clock supplier */
altclksrc &= ~ALTCLKSRC_MODE_MASK;
altclksrc |= ALTCLKSRC_MODE_ACTIVE;
/* enable clocks */
altclksrc |= ALTCLKSRC_ENABLE_INT_MASK | ALTCLKSRC_ENABLE_EXT_MASK;
writel(altclksrc, &scrm->altclksrc);
ret = omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
if (ret < 0)
return ret;
return 0;
}
int ehci_hcd_stop(int index)
{
return omap_ehci_hcd_stop();
}
#endif
/*
* get_board_rev() - get board revision
*/
u32 get_board_rev(void)
{
return 0x20;
}

199
board/gumstix/duovero/duovero_mux_data.h Normal file
View File

@ -0,0 +1,199 @@
/*
* (C) Copyright 2012
* Gumstix Incorporated, <www.gumstix.com>
* Maintainer: Ash Charles <ash@gumstix.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _DUOVERO_MUX_DATA_H_
#define _DUOVERO_MUX_DATA_H_
#include <asm/arch/mux_omap4.h>
const struct pad_conf_entry core_padconf_array_essential[] = {
{SDMMC1_CLK, (PTU | OFF_EN | OFF_OUT_PTD | M0)}, /* sdmmc1_clk */
{SDMMC1_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_cmd */
{SDMMC1_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat0 */
{SDMMC1_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat1 */
{SDMMC1_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat2 */
{SDMMC1_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat3 */
{I2C1_SCL, (PTU | IEN | M0)}, /* i2c1_scl */
{I2C1_SDA, (PTU | IEN | M0)}, /* i2c1_sda */
{I2C2_SCL, (PTU | IEN | M0)}, /* i2c2_scl */
{I2C2_SDA, (PTU | IEN | M0)}, /* i2c2_sda */
{I2C3_SCL, (PTU | IEN | M0)}, /* i2c3_scl */
{I2C3_SDA, (PTU | IEN | M0)}, /* i2c3_sda */
{I2C4_SCL, (PTU | IEN | M0)}, /* i2c4_scl */
{I2C4_SDA, (PTU | IEN | M0)}, /* i2c4_sda */
{UART3_CTS_RCTX, (PTU | IEN | M0)}, /* uart3_tx */
{UART3_RTS_SD, (M0)}, /* uart3_rts_sd */
{UART3_RX_IRRX, (PTU | IEN | M0)}, /* uart3_rx */
{UART3_TX_IRTX, (M0)} /* uart3_tx */
};
const struct pad_conf_entry wkup_padconf_array_essential[] = {
{PAD1_SR_SCL, (PTU | IEN | M0)}, /* sr_scl */
{PAD0_SR_SDA, (PTU | IEN | M0)}, /* sr_sda */
{PAD1_SYS_32K, (IEN | M0)} /* sys_32k */
};
const struct pad_conf_entry core_padconf_array_non_essential[] = {
{GPMC_AD0, (PTU | IEN | M0)}, /* gpmc_ad0 */
{GPMC_AD1, (PTU | IEN | M0)}, /* gpmc_ad1 */
{GPMC_AD2, (PTU | IEN | M0)}, /* gpmc_ad2 */
{GPMC_AD3, (PTU | IEN | M0)}, /* gpmc_ad3 */
{GPMC_AD4, (PTU | IEN | M0)}, /* gpmc_ad4 */
{GPMC_AD5, (PTU | IEN | M0)}, /* gpmc_ad5 */
{GPMC_AD6, (PTU | IEN | M0)}, /* gpmc_ad6 */
{GPMC_AD7, (PTU | IEN | M0)}, /* gpmc_ad7 */
{GPMC_AD8, (PTU | IEN | M0)}, /* gpmc_ad8 */
{GPMC_AD9, (PTU | IEN | M0)}, /* gpmc_ad9 */
{GPMC_AD10, (PTU | IEN | M0)}, /* gpmc_ad10 */
{GPMC_AD11, (PTU | IEN | M0)}, /* gpmc_ad11 */
{GPMC_AD12, (PTU | IEN | M0)}, /* gpmc_ad12 */
{GPMC_AD13, (PTU | IEN | M0)}, /* gpmc_ad13 */
{GPMC_AD14, (PTU | IEN | M0)}, /* gpmc_ad14 */
{GPMC_AD15, (PTU | IEN | M0)}, /* gpmc_ad15 */
{GPMC_A16, (PTU | IEN | M3)}, /* gpio_40 */
{GPMC_A17, (PTU | IEN | M3)}, /* gpio_41 - hdmi_ls_oe */
{GPMC_A18, (PTU | IEN | M3)}, /* gpio_42 */
{GPMC_A19, (PTU | IEN | M3)}, /* gpio_43 - wifi_en */
{GPMC_A20, (PTU | IEN | M3)}, /* gpio_44 - eth_irq */
{GPMC_A21, (PTU | IEN | M3)}, /* gpio_45 - eth_nreset */
{GPMC_A22, (PTU | IEN | M3)}, /* gpio_46 - eth_pme */
{GPMC_A23, (PTU | IEN | M3)}, /* gpio_47 */
{GPMC_A24, (PTU | IEN | M3)}, /* gpio_48 - eth_mdix */
{GPMC_A25, (PTU | IEN | M3)}, /* gpio_49 - bt_wakeup */
{GPMC_NCS0, (PTU | M0)}, /* gpmc_ncs0 */
{GPMC_NCS1, (PTU | M0)}, /* gpmc_ncs1 */
{GPMC_NCS2, (PTU | M0)}, /* gpmc_ncs2 */
{GPMC_NCS3, (PTU | IEN | M3)}, /* gpio_53 */
{C2C_DATA12, (PTU | M0)}, /* gpmc_ncs4 */
{C2C_DATA13, (PTU | M0)}, /* gpmc_ncs5 - eth_cs */
{GPMC_NWP, (PTU | IEN | M0)}, /* gpmc_nwp */
{GPMC_CLK, (PTU | IEN | M0)}, /* gpmc_clk */
{GPMC_NADV_ALE, (PTU | M0)}, /* gpmc_nadv_ale */
{GPMC_NBE0_CLE, (PTU | M0)}, /* gpmc_nbe0_cle */
{GPMC_NBE1, (PTU | M0)}, /* gpmc_nbe1 */
{GPMC_WAIT0, (PTU | IEN | M0)}, /* gpmc_wait0 */
{GPMC_WAIT1, (PTU | IEN | M0)}, /* gpio_62 - usbh_nreset */
{GPMC_NOE, (PTU | M0)}, /* gpmc_noe */
{GPMC_NWE, (PTU | M0)}, /* gpmc_nwe */
{HDMI_HPD, (PTD | IEN | M3)}, /* gpio_63 - hdmi_hpd */
{HDMI_CEC, (PTU | IEN | M0)}, /* hdmi_cec */
{HDMI_DDC_SCL, (M0)}, /* hdmi_ddc_scl */
{HDMI_DDC_SDA, (IEN | M0)}, /* hdmi_ddc_sda */
{CSI21_DX0, (IEN | M0)}, /* csi21_dx0 */
{CSI21_DY0, (IEN | M0)}, /* csi21_dy0 */
{CSI21_DX1, (IEN | M0)}, /* csi21_dx1 */
{CSI21_DY1, (IEN | M0)}, /* csi21_dy1 */
{CSI21_DX2, (IEN | M0)}, /* csi21_dx2 */
{CSI21_DY2, (IEN | M0)}, /* csi21_dy2 */
{CSI21_DX3, (IEN | M0)}, /* csi21_dx3 */
{CSI21_DY3, (IEN | M0)}, /* csi21_dy3 */
{CSI21_DX4, (IEN | M0)}, /* csi21_dx4 */
{CSI21_DY4, (IEN | M0)}, /* csi21_dy4 */
{CSI22_DX0, (IEN | M0)}, /* csi22_dx0 */
{CSI22_DY0, (IEN | M0)}, /* csi22_dy0 */
{CSI22_DX1, (IEN | M0)}, /* csi22_dx1 */
{CSI22_DY1, (IEN | M0)}, /* csi22_dy1 */
{USBB1_ULPITLL_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)},/* usbb1_ulpiphy_clk */
{USBB1_ULPITLL_STP, (OFF_EN | OFF_OUT_PTD | M4)}, /* usbb1_ulpiphy_stp */
{USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dir */
{USBB1_ULPITLL_NXT, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_nxt */
{USBB1_ULPITLL_DAT0, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat0 */
{USBB1_ULPITLL_DAT1, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat1 */
{USBB1_ULPITLL_DAT2, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat2 */
{USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat3 */
{USBB1_ULPITLL_DAT4, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat4 */
{USBB1_ULPITLL_DAT5, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat5 */
{USBB1_ULPITLL_DAT6, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat6 */
{USBB1_ULPITLL_DAT7, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat7 */
{USBB1_HSIC_DATA, (PTU | IEN | M3)}, /* gpio_96 - usbh_cpen */
{USBB1_HSIC_STROBE, (PTU | IEN | M3)}, /* gpio_97 - usbh_reset */
{ABE_MCBSP2_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp2_clkx */
{ABE_MCBSP2_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dr */
{ABE_MCBSP2_DX, (OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dx */
{ABE_MCBSP2_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp2_fsx */
{ABE_PDM_UL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_ul_data */
{ABE_PDM_DL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_dl_data */
{ABE_PDM_FRAME, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_frame */
{ABE_PDM_LB_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_lb_clk */
{ABE_CLKS, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_clks */
{ABE_DMIC_CLK1, (M0)}, /* abe_dmic_clk1 */
{ABE_DMIC_DIN1, (IEN | M0)}, /* abe_dmic_din1 */
{ABE_DMIC_DIN2, (IEN | M0)}, /* abe_dmic_din2 */
{ABE_DMIC_DIN3, (IEN | M0)}, /* abe_dmic_din3 */
{UART2_CTS, (PTU | IEN | M0)}, /* uart2_cts */
{UART2_RTS, (M0)}, /* uart2_rts */
{UART2_RX, (PTU | IEN | M0)}, /* uart2_rx */
{UART2_TX, (M0)}, /* uart2_tx */
{HDQ_SIO, (M0)}, /* hdq-sio */
{MCSPI1_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_clk */
{MCSPI1_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_somi */
{MCSPI1_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_simo */
{MCSPI1_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_cs0 */
{MCSPI1_CS1, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_cs1 */
{SDMMC5_CLK, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_clk */
{SDMMC5_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_cmd */
{SDMMC5_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat0 */
{SDMMC5_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat1 */
{SDMMC5_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat2 */
{SDMMC5_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat3 */
{MCSPI4_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_clk */
{MCSPI4_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_simo */
{MCSPI4_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_somi */
{MCSPI4_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_cs0 */
{UART4_RX, (IEN | PTU | M0)}, /* uart4_rx */
{UART4_TX, (M0)}, /* uart4_tx */
{USBB2_ULPITLL_CLK, (PTU | IEN | M3)}, /* gpio_157 - start_adc */
{USBB2_ULPITLL_STP, (PTU | IEN | M3)}, /* gpio_158 - spi_nirq */
{USBB2_ULPITLL_DIR, (PTU | IEN | M3)}, /* gpio_159 - bt_nreset */
{USBB2_ULPITLL_NXT, (PTU | IEN | M3)}, /* gpio_160 - audio_pwron*/
{USBB2_ULPITLL_DAT0, (PTU | IEN | M3)}, /* gpio_161 - bid_0 */
{USBB2_ULPITLL_DAT1, (PTU | IEN | M3)}, /* gpio_162 - bid_1 */
{USBB2_ULPITLL_DAT2, (PTU | IEN | M3)}, /* gpio_163 - bid_2 */
{USBB2_ULPITLL_DAT3, (PTU | IEN | M3)}, /* gpio_164 - bid_3 */
{USBB2_ULPITLL_DAT4, (PTU | IEN | M3)}, /* gpio_165 - bid_4 */
{USBB2_ULPITLL_DAT5, (PTU | IEN | M3)}, /* gpio_166 - ts_irq*/
{USBB2_ULPITLL_DAT6, (PTU | IEN | M3)}, /* gpio_167 - gps_pps */
{USBB2_ULPITLL_DAT7, (PTU | IEN | M3)}, /* gpio_168 */
{USBB2_HSIC_DATA, (PTU | IEN | M3)}, /* gpio_169 */
{USBB2_HSIC_STROBE, (PTU | IEN | M3)}, /* gpio_170 */
{UNIPRO_TX1, (PTU | IEN | M3)}, /* gpio_173 */
{USBA0_OTG_CE, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* usba0_otg_ce */
{USBA0_OTG_DP, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dp */
{USBA0_OTG_DM, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dm */
{SYS_NIRQ1, (PTU | IEN | M0)}, /* sys_nirq1 */
{SYS_NIRQ2, (PTU | IEN | M0)}, /* sys_nirq2 */
{SYS_BOOT0, (M0)}, /* sys_boot0 */
{SYS_BOOT1, (M0)}, /* sys_boot1 */
{SYS_BOOT2, (M0)}, /* sys_boot2 */
{SYS_BOOT3, (M0)}, /* sys_boot3 */
{SYS_BOOT4, (M0)}, /* sys_boot4 */
{SYS_BOOT5, (M0)}, /* sys_boot5 */
{DPM_EMU0, (IEN | M0)}, /* dpm_emu0 */
{DPM_EMU1, (IEN | M0)}, /* dpm_emu1 */
{DPM_EMU16, (PTU | IEN | M3)}, /* gpio_27 */
{DPM_EMU17, (PTU | IEN | M3)}, /* gpio_28 */
{DPM_EMU18, (PTU | IEN | M3)}, /* gpio_29 */
{DPM_EMU19, (PTU | IEN | M3)}, /* gpio_30 */
};
const struct pad_conf_entry wkup_padconf_array_non_essential[] = {
{PAD1_FREF_XTAL_IN, (M0)}, /* fref_xtal_in */
{PAD0_FREF_SLICER_IN, (M0)}, /* fref_slicer_in */
{PAD1_FREF_CLK_IOREQ, (M0)}, /* fref_clk_ioreq */
{PAD0_FREF_CLK0_OUT, (M7)}, /* safe mode */
{PAD1_FREF_CLK3_REQ, M7}, /* safe mode */
{PAD0_FREF_CLK3_OUT, (M0)}, /* fref_clk3_out */
{PAD0_SYS_NRESPWRON, (M0)}, /* sys_nrespwron */
{PAD1_SYS_NRESWARM, (M0)}, /* sys_nreswarm */
{PAD0_SYS_PWR_REQ, (PTU | M0)}, /* sys_pwr_req */
{PAD1_SYS_PWRON_RESET, (M3)}, /* gpio_wk29 */
{PAD0_SYS_BOOT6, (M0)}, /* sys_boot6 */
{PAD1_SYS_BOOT7, (M0)}, /* sys_boot7 */
};
#endif /* _DUOVERO_MUX_DATA_H_ */

43
board/overo/overo.c
View File

@ -39,6 +39,11 @@ DECLARE_GLOBAL_DATA_PTR;
#define GUMSTIX_CHESTNUT43 0x06000200
#define GUMSTIX_PINTO 0x07000200
#define GUMSTIX_GALLOP43 0x08000200
#define GUMSTIX_ALTO35 0x09000200
#define GUMSTIX_STAGECOACH 0x0A000200
#define GUMSTIX_THUMBO 0x0B000200
#define GUMSTIX_TURTLECORE 0x0C000200
#define GUMSTIX_ARBOR43C 0x0D000200
#define ETTUS_USRP_E 0x01000300
@ -141,6 +146,7 @@ void get_board_mem_timings(struct board_sdrc_timings *timings)
timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
break;
case REVISION_1: /* Micron 256MB/512MB, 1/2 banks of 256MB */
case REVISION_4:
timings->mcfg = MICRON_V_MCFG_200(256 << 20);
timings->ctrla = MICRON_V_ACTIMA_200;
timings->ctrlb = MICRON_V_ACTIMB_200;
@ -230,6 +236,8 @@ unsigned int get_expansion_id(void)
*/
int misc_init_r(void)
{
unsigned int expansion_id;
twl4030_power_init();
twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON);
@ -252,7 +260,8 @@ int misc_init_r(void)
puts("Unable to detect mmc2 connection type\n");
}
switch (get_expansion_id()) {
expansion_id = get_expansion_id();
switch (expansion_id) {
case GUMSTIX_SUMMIT:
printf("Recognized Summit expansion board (rev %d %s)\n",
expansion_config.revision,
@ -302,6 +311,35 @@ int misc_init_r(void)
expansion_config.fab_revision);
setenv("defaultdisplay", "lcd43");
break;
case GUMSTIX_ALTO35:
printf("Recognized Alto35 expansion board (rev %d %s)\n",
expansion_config.revision,
expansion_config.fab_revision);
MUX_ALTO35();
setenv("defaultdisplay", "lcd35");
break;
case GUMSTIX_STAGECOACH:
printf("Recognized Stagecoach expansion board (rev %d %s)\n",
expansion_config.revision,
expansion_config.fab_revision);
break;
case GUMSTIX_THUMBO:
printf("Recognized Thumbo expansion board (rev %d %s)\n",
expansion_config.revision,
expansion_config.fab_revision);
break;
case GUMSTIX_TURTLECORE:
printf("Recognized Turtlecore expansion board (rev %d %s)\n",
expansion_config.revision,
expansion_config.fab_revision);
break;
case GUMSTIX_ARBOR43C:
printf("Recognized Arbor43C expansion board (rev %d %s)\n",
expansion_config.revision,
expansion_config.fab_revision);
MUX_ARBOR43C();
setenv("defaultdisplay", "lcd43");
break;
case ETTUS_USRP_E:
printf("Recognized Ettus Research USRP-E (rev %d %s)\n",
expansion_config.revision,
@ -313,7 +351,8 @@ int misc_init_r(void)
puts("No EEPROM on expansion board\n");
break;
default:
puts("Unrecognized expansion board\n");
printf("Unrecognized expansion board 0x%08x\n", expansion_id);
break;
}
if (expansion_config.content == 1)

17
board/overo/overo.h
View File

@ -22,6 +22,7 @@ const omap3_sysinfo sysinfo = {
#define REVISION_1 0x1
#define REVISION_2 0x2
#define REVISION_3 0x3
#define REVISION_4 0x4
/*
* IEN - Input Enable
@ -404,4 +405,20 @@ const omap3_sysinfo sysinfo = {
MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M4)) /*GPIO_173 */\
MUX_VAL(CP(MCSPI1_CS1), (IDIS | PTD | EN | M4)) /*GPIO_175 */\
#define MUX_ALTO35() \
MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTU | EN | M4)) /*GPIO_10-BTN*/\
MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M4)) /*GPIO_148-RED LED*/\
MUX_VAL(CP(UART1_CTS), (IDIS | PTD | DIS | M4)) /*GPIO_150-YELLOW LED*/\
MUX_VAL(CP(UART1_RX), (IDIS | PTD | DIS | M4)) /*GPIO_151-BLUE LED*/\
MUX_VAL(CP(HDQ_SIO), (IDIS | PTD | DIS | M4)) /*GPIO_170-GREEN LED*/\
MUX_VAL(CP(MCSPI1_CS1), (IDIS | PTD | EN | M4)) /*GPIO_175*/\
#define MUX_ARBOR43C() \
MUX_VAL(CP(CSI2_DX1), (IDIS | PTD | DIS | M4)) /*GPIO_114-RED LED*/\
MUX_VAL(CP(UART1_CTS), (IDIS | PTD | DIS | M4)) /*GPIO_150-YELLOW LED*/\
MUX_VAL(CP(HDQ_SIO), (IEN | PTU | EN | M4)) /*GPIO_170-BUTTON */\
MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTD | DIS | M4)) /*GPIO_186-BLUE LED*/\
MUX_VAL(CP(JTAG_EMU1), (IDIS | PTD | DIS | M4)) /*GPIO_31-CAP WAKE*/\
MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTU | EN | M4)) /*GPIO_10-CAP IRQ*/\
#endif

1
board/renesas/koelsch/qos.c
View File

@ -111,6 +111,7 @@ void qos_init(void)
/* DBSC DBADJ2 */
writel(0x20042004, DBSC3_0_DBADJ2);
writel(0x20042004, DBSC3_1_DBADJ2);
/* S3C -QoS */
s3c = (struct rcar_s3c *)S3C_BASE;

1
board/xilinx/zynq/.gitignore vendored Normal file
View File

@ -0,0 +1 @@
ps7_init.[ch]

5
board/xilinx/zynq/Makefile
View File

@ -6,4 +6,7 @@
#
obj-y := board.o
obj-$(CONFIG_SPL_BUILD) += ps7_init.o
# Please copy ps7_init.c/h from hw project to this directory
obj-$(CONFIG_SPL_BUILD) += \
$(if $(wildcard $(srctree)/$(src)/ps7_init.c), ps7_init.o)

25
board/xilinx/zynq/board.c
View File

@ -6,6 +6,8 @@
#include <common.h>
#include <fdtdec.h>
#include <fpga.h>
#include <mmc.h>
#include <netdev.h>
#include <zynqpl.h>
#include <asm/arch/hardware.h>
@ -13,21 +15,23 @@
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_FPGA
xilinx_desc fpga;
#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
(defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
static xilinx_desc fpga;
/* It can be done differently */
xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10);
xilinx_desc fpga015 = XILINX_XC7Z015_DESC(0x15);
xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20);
xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30);
xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45);
xilinx_desc fpga100 = XILINX_XC7Z100_DESC(0x100);
static xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10);
static xilinx_desc fpga015 = XILINX_XC7Z015_DESC(0x15);
static xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20);
static xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30);
static xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45);
static xilinx_desc fpga100 = XILINX_XC7Z100_DESC(0x100);
#endif
int board_init(void)
{
#ifdef CONFIG_FPGA
#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
(defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
u32 idcode;
idcode = zynq_slcr_get_idcode();
@ -54,7 +58,8 @@ int board_init(void)
}
#endif
#ifdef CONFIG_FPGA
#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
(defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
fpga_init();
fpga_add(fpga_xilinx, &fpga);
#endif

12
board/xilinx/zynq/ps7_init.c
View File

@ -1,12 +0,0 @@
/*
* (C) Copyright 2014 Xilinx, Inc. Michal Simek
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/arch/spl.h>
__weak void ps7_init(void)
{
puts("Please copy ps7_init.c/h from hw project\n");
}

13
board/xilinx/zynq/xil_io.h Normal file
View File

@ -0,0 +1,13 @@
/*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef XIL_IO_H /* prevent circular inclusions */
#define XIL_IO_H
/*
* This empty file is here because ps7_init.c exported by hw project
* has #include "xil_io.h" line.
*/
#endif /* XIL_IO_H */

2
boards.cfg
View File

@ -362,8 +362,10 @@ Active arm armv7 omap3 ti evm
Active arm armv7 omap3 ti evm omap3_evm_quick_nand - -
Active arm armv7 omap3 ti sdp3430 omap3_sdp3430 - Nishanth Menon <nm@ti.com>
Active arm armv7 omap3 timll devkit8000 devkit8000 - Thomas Weber <weber@corscience.de>
Active arm armv7 omap4 gumstix duovero duovero - Ash Charles <ash@gumstix.com>
Active arm armv7 omap4 ti panda omap4_panda - Sricharan R <r.sricharan@ti.com>
Active arm armv7 omap4 ti sdp4430 omap4_sdp4430 - Sricharan R <r.sricharan@ti.com>
Active arm armv7 omap5 compulab cm_t54 cm_t54 - Dmitry Lifshitz <lifshitz@compulab.co.il>
Active arm armv7 omap5 ti dra7xx dra7xx_evm dra7xx_evm:CONS_INDEX=1 Lokesh Vutla <lokeshvutla@ti.com>
Active arm armv7 omap5 ti dra7xx dra7xx_evm_qspiboot dra7xx_evm:CONS_INDEX=1,QSPI_BOOT Lokesh Vutla <lokeshvutla@ti.com>
Active arm armv7 omap5 ti dra7xx dra7xx_evm_uart3 dra7xx_evm:CONS_INDEX=3,SPL_YMODEM_SUPPORT Lokesh Vutla <lokeshvutla@ti.com>

1
drivers/usb/host/Makefile
View File

@ -37,6 +37,7 @@ obj-$(CONFIG_USB_EHCI_SPEAR) += ehci-spear.o
obj-$(CONFIG_USB_EHCI_TEGRA) += ehci-tegra.o
obj-$(CONFIG_USB_EHCI_VCT) += ehci-vct.o
obj-$(CONFIG_USB_EHCI_RMOBILE) += ehci-rmobile.o
obj-$(CONFIG_USB_EHCI_ZYNQ) += ehci-zynq.o
# xhci
obj-$(CONFIG_USB_XHCI) += xhci.o xhci-mem.o xhci-ring.o

104
drivers/usb/host/ehci-zynq.c Normal file
View File

@ -0,0 +1,104 @@
/*
* (C) Copyright 2014, Xilinx, Inc
*
* USB Low level initialization(Specific to zynq)
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/arch/hardware.h>
#include <asm/arch/sys_proto.h>
#include <asm/io.h>
#include <usb.h>
#include <usb/ehci-fsl.h>
#include <usb/ulpi.h>
#include "ehci.h"
#define ZYNQ_USB_USBCMD_RST 0x0000002
#define ZYNQ_USB_USBCMD_STOP 0x0000000
#define ZYNQ_USB_NUM_MIO 12
/*
* Create the appropriate control structures to manage
* a new EHCI host controller.
*/
int ehci_hcd_init(int index, enum usb_init_type init, struct ehci_hccr **hccr,
struct ehci_hcor **hcor)
{
struct usb_ehci *ehci;
struct ulpi_viewport ulpi_vp;
int ret, mio_usb;
/* Used for writing the ULPI data address */
struct ulpi_regs *ulpi = (struct ulpi_regs *)0;
if (!index) {
mio_usb = zynq_slcr_get_mio_pin_status("usb0");
if (mio_usb != ZYNQ_USB_NUM_MIO) {
printf("usb0 wrong num MIO: %d, Index %d\n", mio_usb,
index);
return -1;
}
ehci = (struct usb_ehci *)ZYNQ_USB_BASEADDR0;
} else {
mio_usb = zynq_slcr_get_mio_pin_status("usb1");
if (mio_usb != ZYNQ_USB_NUM_MIO) {
printf("usb1 wrong num MIO: %d, Index %d\n", mio_usb,
index);
return -1;
}
ehci = (struct usb_ehci *)ZYNQ_USB_BASEADDR1;
}
*hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
*hcor = (struct ehci_hcor *)((uint32_t) *hccr +
HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
ulpi_vp.viewport_addr = (u32)&ehci->ulpi_viewpoint;
ulpi_vp.port_num = 0;
ret = ulpi_init(&ulpi_vp);
if (ret) {
puts("zynq ULPI viewport init failed\n");
return -1;
}
/* ULPI set flags */
ulpi_write(&ulpi_vp, &ulpi->otg_ctrl,
ULPI_OTG_DP_PULLDOWN | ULPI_OTG_DM_PULLDOWN |
ULPI_OTG_EXTVBUSIND);
ulpi_write(&ulpi_vp, &ulpi->function_ctrl,
ULPI_FC_FULL_SPEED | ULPI_FC_OPMODE_NORMAL |
ULPI_FC_SUSPENDM);
ulpi_write(&ulpi_vp, &ulpi->iface_ctrl, 0);
/* Set VBus */
ulpi_write(&ulpi_vp, &ulpi->otg_ctrl_set,
ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
return 0;
}
/*
* Destroy the appropriate control structures corresponding
* the the EHCI host controller.
*/
int ehci_hcd_stop(int index)
{
struct usb_ehci *ehci;
if (!index)
ehci = (struct usb_ehci *)ZYNQ_USB_BASEADDR0;
else
ehci = (struct usb_ehci *)ZYNQ_USB_BASEADDR1;
/* Stop controller */
writel(ZYNQ_USB_USBCMD_STOP, &ehci->usbcmd);
udelay(1000);
/* Initiate controller reset */
writel(ZYNQ_USB_USBCMD_RST, &ehci->usbcmd);
return 0;
}

1
include/configs/armadillo-800eva.h
View File

@ -48,6 +48,7 @@
#define CONFIG_USE_ARCH_MEMCPY
#define CONFIG_TMU_TIMER
#define CONFIG_SYS_DCACHE_OFF
#define CONFIG_SYS_GENERIC_BOARD
/* STACK */
#define CONFIG_SYS_INIT_SP_ADDR 0xE8083000

149
include/configs/cm_t54.h Normal file
View File

@ -0,0 +1,149 @@
/*
* Config file for Compulab CM-T54 board
*
* Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
*
* Author: Dmitry Lifshitz <lifshitz@compulab.co.il>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CONFIG_CM_T54_H
#define __CONFIG_CM_T54_H
#define CONFIG_CM_T54
#define CONFIG_DRAM_2G
#include <configs/ti_omap5_common.h>
#undef CONFIG_MISC_INIT_R
#undef CONFIG_SPL_OS_BOOT
/* Device Tree defines */
#define CONFIG_OF_LIBFDT
#define CONFIG_OF_BOARD_SETUP
/* EEPROM related defines */
#define CONFIG_SYS_I2C_OMAP34XX
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
/* Enable SD/MMC CD and WP GPIOs */
#define OMAP_HSMMC_USE_GPIO
/* UART setup */
#define CONFIG_CONS_INDEX 4
#define CONFIG_SYS_NS16550_COM4 UART4_BASE
#define CONFIG_BAUDRATE 115200
/* SD/MMC RAW boot */
#undef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR
#undef CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200 /* 0x40000 - 256 KB */
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x300 /* 384 KB */
/* MMC ENV related defines */
#undef CONFIG_ENV_OFFSET
#undef CONFIG_ENV_SIZE
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 1 /* SLOT2: eMMC(1) */
#define CONFIG_SYS_MMC_ENV_PART 0
#define CONFIG_ENV_OFFSET 0xc0000 /* (in bytes) 768 KB */
#define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
#define CONFIG_CMD_SAVEENV
/* Enhance our eMMC support / experience. */
#define CONFIG_HSMMC2_8BIT
#define CONFIG_SUPPORT_EMMC_BOOT
/* USB UHH support options */
#define CONFIG_CMD_USB
#define CONFIG_USB_HOST
#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_OMAP
#define CONFIG_USB_STORAGE
#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_OMAP_EHCI_PHY2_RESET_GPIO 76 /* HSIC2 HUB #RESET */
#define CONFIG_OMAP_EHCI_PHY3_RESET_GPIO 83 /* HSIC3 ETH #RESET */
/* Enabled commands */
#define CONFIG_CMD_DHCP /* DHCP Support */
#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
#define CONFIG_CMD_PING
/* USB Networking options */
#define CONFIG_USB_HOST_ETHER
#define CONFIG_USB_ETHER_SMSC95XX
#define CONFIG_USB_ETHER_RNDIS
#define CONFIG_USB_ETHER_ASIX
#define CONFIG_USB_ETHER_MCS7830
/* Max time to hold reset on this board, see doc/README.omap-reset-time */
#define CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC 16296
/*
* Miscellaneous configurable options
*/
#undef CONFIG_SYS_AUTOLOAD
#undef CONFIG_SYS_PROMPT
#undef CONFIG_EXTRA_ENV_SETTINGS
#undef CONFIG_BOOTCOMMAND
#undef CONFIG_BOOTDELAY
#define CONFIG_BOOTDELAY 3
#define CONFIG_SYS_AUTOLOAD "no"
#define CONFIG_SYS_PROMPT "CM-T54 # "
#define CONFIG_EXTRA_ENV_SETTINGS \
DEFAULT_LINUX_BOOT_ENV \
"baudrate=115200\0" \
"bootdelay=3\0" \
"autoload=no\0" \
"bootscr=bootscr.img\0" \
"fdtfile=omap5-sbc-t54.dtb\0" \
"kernel=zImage-cm-t54\0" \
"ramdisk=ramdisk-cm-t54.img\0" \
"console=ttyO3\0" \
"ramdisksize=16384\0" \
"mmcdev=0\0" \
"mmcroot=/dev/mmcblk1p2\0" \
"mmcargs=setenv bootargs console=${console} " \
"root=${mmcroot} rw rootwait\0" \
"ramroot=/dev/ram0\0" \
"ramargs=setenv bootargs console=${console} " \
"root=${ramroot} ramdisk_size=${ramdisksize} rw\0" \
"mmcloadkernel=load mmc ${mmcdev} ${loadaddr} ${kernel}\0" \
"mmcloadfdt=load mmc ${mmcdev} ${fdtaddr} ${fdtfile}\0" \
"mmcloadramdisk=load mmc ${mmcdev} ${rdaddr} ${ramdisk}\0" \
"mmcloadbootscript=load mmc ${mmcdev} ${loadaddr} ${bootsrc}\0" \
"mmcbootscript=echo Running bootscript from mmc${mmcdev}...; " \
"source ${loadaddr}\0" \
"mmcbootlinux=echo Booting from mmc${mmcdev} ...; " \
"bootz ${loadaddr} ${rdaddr} ${fdtaddr}\0" \
"mmcboot=if mmc dev ${mmcdev} && mmc rescan; then " \
"if run mmcloadbootscript; " \
"then run mmcbootscript; " \
"fi; " \
"if run mmcloadkernel; then " \
"if run mmcloadfdt; then " \
"if run mmcloadramdisk; then " \
"run ramargs; " \
"run mmcbootlinux; " \
"fi; " \
"run mmcargs; " \
"setenv rdaddr - ; " \
"run mmcbootlinux; " \
"fi; " \
"fi; " \
"fi;\0"
#define CONFIG_BOOTCOMMAND \
"bootcmd=run mmcboot || setenv mmcdev 1; setenv mmcroot /dev/mmcblk0p2; run mmcboot;"
#endif /* __CONFIG_CM_T54_H */

62
include/configs/duovero.h Normal file
View File

@ -0,0 +1,62 @@
/*
* (C) Copyright: 2013
* Gumstix, Inc - http://www.gumstix.com
* Maintainer: Ash Charles <ash@gumstix.com>
*
* Configuration settings for the Gumstix DuoVero board.
* See omap4_common.h for OMAP4 common part
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CONFIG_DUOVERO_H
#define __CONFIG_DUOVERO_H
/*
* High Level Configuration Options
*/
#define CONFIG_DUOVERO
#define MACH_TYPE_OMAP4_DUOVERO 4097 /* Until the next sync */
#define CONFIG_MACH_TYPE MACH_TYPE_OMAP4_DUOVERO
#include <configs/ti_omap4_common.h>
#undef CONFIG_SPL_OS_BOOT
#undef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
#define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION
#define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
#undef CONFIG_SYS_PROMPT
#define CONFIG_SYS_PROMPT "duovero # "
/* USB UHH support options */
#define CONFIG_CMD_USB
#define CONFIG_USB_HOST
#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_OMAP
#define CONFIG_USB_STORAGE
#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 1
#define CONFIG_OMAP_EHCI_PHY2_RESET_GPIO 62
#define CONFIG_SYS_ENABLE_PADS_ALL
#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_NET
#define CONFIG_SMC911X
#define CONFIG_SMC911X_32_BIT
#define CONFIG_SMC911X_BASE 0x2C000000
/* GPIO */
#define CONFIG_CMD_GPIO
/* ENV related config options */
#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
#endif /* __CONFIG_DUOVERO_H */

23
include/configs/koelsch.h
View File

@ -31,10 +31,22 @@
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_NFS
#define CONFIG_CMD_BOOTZ
#define CONFIG_CMD_USB
#define CONFIG_CMD_FAT
#define CONFIG_CMD_SF
#define CONFIG_CMD_SPI
#define CONFIG_FAT_WRITE
#define CONFIG_EXT4_WRITE
#define CONFIG_SYS_TEXT_BASE 0xE6304000
#define CONFIG_SYS_THUMB_BUILD
#define CONFIG_SYS_GENERIC_BOARD
/* Support File sytems */
#define CONFIG_DOS_PARTITION
#define CONFIG_SUPPORT_VFAT
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
@ -55,8 +67,6 @@
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_USE_ARCH_MEMSET
#define CONFIG_USE_ARCH_MEMCPY
#define CONFIG_TMU_TIMER
/* STACK */
@ -80,7 +90,6 @@
/* SCIF */
#define CONFIG_SCIF_CONSOLE
#define CONFIG_CONS_SCIF0
#define SCIF0_BASE 0xe6e60000
#undef CONFIG_SYS_CONSOLE_INFO_QUIET
#undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
#undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE
@ -159,4 +168,10 @@
#define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */
/* USB */
#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_RMOBILE
#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
#define CONFIG_USB_STORAGE
#endif /* __KOELSCH_H */

22
include/configs/lager.h
View File

@ -32,10 +32,21 @@
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_NFS
#define CONFIG_CMD_BOOTZ
#define CONFIG_CMD_USB
#define CONFIG_CMD_FAT
#define CONFIG_CMD_SF
#define CONFIG_CMD_SPI
#define CONFIG_FAT_WRITE
#define CONFIG_EXT4_WRITE
#define CONFIG_SYS_TEXT_BASE 0xE8080000
#define CONFIG_SYS_THUMB_BUILD
#define CONFIG_SYS_GENERIC_BOARD
/* Support File sytems */
#define CONFIG_DOS_PARTITION
#define CONFIG_SUPPORT_VFAT
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
@ -57,8 +68,6 @@
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_USE_ARCH_MEMSET
#define CONFIG_USE_ARCH_MEMCPY
#define CONFIG_TMU_TIMER
/* STACK */
@ -82,7 +91,6 @@
/* SCIF */
#define CONFIG_SCIF_CONSOLE
#define CONFIG_CONS_SCIF0
#define SCIF0_BASE 0xe6e60000
#undef CONFIG_SYS_CONSOLE_INFO_QUIET
#undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
#undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE
@ -164,4 +172,10 @@
#define CONFIG_SYS_TMU_CLK_DIV 4
/* USB */
#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_RMOBILE
#define CONFIG_USB_MAX_CONTROLLER_COUNT 4
#define CONFIG_USB_STORAGE
#endif /* __LAGER_H */

308
include/configs/omap3_overo.h
View File

@ -7,135 +7,88 @@
#ifndef __CONFIG_H
#define __CONFIG_H
/*
* High Level Configuration Options
*/
#define CONFIG_OMAP /* in a TI OMAP core */
#define CONFIG_OMAP34XX /* which is a 34XX */
#define CONFIG_OMAP3_OVERO /* working with overo */
#define CONFIG_OMAP_GPIO
#define CONFIG_OMAP_COMMON
#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
#define CONFIG_NAND
#define CONFIG_SDRC /* The chip has SDRC controller */
#include <configs/ti_omap3_common.h>
#include <asm/arch/cpu.h> /* get chip and board defs */
#include <asm/arch/omap3.h>
/*
* Display CPU and Board information
*/
/* Display CPU and Board information */
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
/* Clock Defines */
#define V_OSCK 26000000 /* Clock output from T2 */
#define V_SCLK (V_OSCK >> 1)
/* call misc_init_r */
#define CONFIG_MISC_INIT_R
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
/* pass the revision tag */
#define CONFIG_REVISION_TAG
#define CONFIG_OF_LIBFDT
/* override size of malloc() pool */
#undef CONFIG_SYS_MALLOC_LEN
#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */
/* Shift 128 << 15 provides 4 MiB heap to support UBI commands.
* Shift 128 << 10 provides 128 KiB heap for limited-memory devices. */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 15))
/*
* Size of malloc() pool
*/
#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
/* Sector */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
/*
* Hardware drivers
*/
/*
* NS16550 Configuration
*/
#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
/*
* select serial console configuration
*/
#define CONFIG_CONS_INDEX 3
#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
#define CONFIG_SERIAL3 3
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \
115200}
#define CONFIG_GENERIC_MMC
#define CONFIG_MMC
#define CONFIG_OMAP_HSMMC
#define CONFIG_DOS_PARTITION
/* commands to include */
#include <config_cmd_default.h>
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_EXT2 /* EXT2 Support */
#define CONFIG_CMD_FAT /* FAT support */
#define CONFIG_CMD_JFFS2 /* JFFS2 Support */
#define CONFIG_CMD_I2C /* I2C serial bus support */
#define CONFIG_CMD_MMC /* MMC support */
#define CONFIG_CMD_NAND /* NAND support */
#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
#undef CONFIG_CMD_IMI /* iminfo */
#undef CONFIG_CMD_IMLS /* List all found images */
#undef CONFIG_CMD_NFS /* NFS support */
#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
#define CONFIG_SYS_NO_FLASH
#define CONFIG_SYS_I2C
#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
/* I2C Support */
#define CONFIG_SYS_I2C_OMAP34XX
/*
* TWL4030
*/
#define CONFIG_TWL4030_POWER
/* TWL4030 LED */
#define CONFIG_TWL4030_LED
/*
* Board NAND Info.
/* Initialize GPIOs by default */
#define CONFIG_OMAP3_GPIO_2 /* GPIO32..63 is in GPIO Bank 2 */
#define CONFIG_OMAP3_GPIO_3 /* GPIO64..95 is in GPIO Bank 3 */
#define CONFIG_OMAP3_GPIO_4 /* GPIO96..127 is in GPIO Bank 4 */
#define CONFIG_OMAP3_GPIO_5 /* GPIO128..159 is in GPIO Bank 5 */
#define CONFIG_OMAP3_GPIO_6 /* GPIO160..191 is in GPIO Bank 6 */
/* commands to include */
#define CONFIG_CMD_CACHE
#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
#undef CONFIG_CMD_IMI /* iminfo */
#undef CONFIG_CMD_NFS /* NFS support */
#ifdef CONFIG_NAND
#define CONFIG_CMD_UBI /* UBI-formated MTD partition support */
#define CONFIG_CMD_UBIFS /* Read-only UBI volume operations */
#define CONFIG_RBTREE /* required by CONFIG_CMD_UBI */
#define CONFIG_LZO /* required by CONFIG_CMD_UBIFS */
#define CONFIG_MTD_PARTITIONS /* required for UBI partition support */
/* NAND block size is 128 KiB. Synchronize these values with
* overo_nand_partitions in mach-omap2/board-overo.c in Linux:
* xloader 4 * NAND_BLOCK_SIZE = 512 KiB
* uboot 14 * NAND_BLOCK_SIZE = 1792 KiB
* uboot environtment 2 * NAND_BLOCK_SIZE = 256 KiB
* linux 64 * NAND_BLOCK_SIZE = 8 MiB
* rootfs remainder
*/
#define MTDIDS_DEFAULT "nand0=omap2-nand.0"
#define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:" \
"512k(xloader)," \
"1792k(u-boot)," \
"256k(environ)," \
"8m(linux)," \
"-(rootfs)"
#else /* CONFIG_NAND */
#define MTDPARTS_DEFAULT
#endif /* CONFIG_NAND */
/* Board NAND Info. */
#define CONFIG_SYS_NAND_QUIET_TEST
#define CONFIG_NAND_OMAP_GPMC
#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
/* to access nand */
#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
/* to access nand */
/* at CS0 */
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
/* devices */
#define CONFIG_JFFS2_NAND
/* nand device jffs2 lives on */
#define CONFIG_JFFS2_DEV "nand0"
/* start of jffs2 partition */
#define CONFIG_JFFS2_PART_OFFSET 0x680000
#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */
/* partition */
/* Environment information */
#define CONFIG_BOOTDELAY 5
#define CONFIG_EXTRA_ENV_SETTINGS \
"loadaddr=0x82000000\0" \
DEFAULT_LINUX_BOOT_ENV \
"fdtfile=overo.dtb\0" \
"bootdir=/boot\0" \
"bootfile=zImage\0" \
"usbtty=cdc_acm\0" \
"console=ttyO2,115200n8\0" \
"mpurate=500\0" \
"mpurate=auto\0" \
"optargs=\0" \
"vram=12M\0" \
"dvimode=1024x768MR-16@60\0" \
@ -145,6 +98,7 @@
"mmcrootfstype=ext3 rootwait\0" \
"nandroot=ubi0:rootfs ubi.mtd=4\0" \
"nandrootfstype=ubifs\0" \
"mtdparts=" MTDPARTS_DEFAULT "\0" \
"mmcargs=setenv bootargs console=${console} " \
"${optargs} " \
"mpurate=${mpurate} " \
@ -161,80 +115,69 @@
"omapdss.def_disp=${defaultdisplay} " \
"root=${nandroot} " \
"rootfstype=${nandrootfstype}\0" \
"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
"bootscript=echo Running bootscript from mmc ...; " \
"loadbootscript=load mmc ${mmcdev} ${loadaddr} boot.scr\0" \
"bootscript=echo Running boot script from mmc ...; " \
"source ${loadaddr}\0" \
"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
"mmcboot=echo Booting from mmc ...; " \
"loadbootenv=load mmc ${mmcdev} ${loadaddr} uEnv.txt\0" \
"importbootenv=echo Importing environment from mmc ...; " \
"env import -t ${loadaddr} ${filesize}\0" \
"loaduimage=load mmc ${mmcdev} ${loadaddr} uImage\0" \
"mmcboot=echo Booting from mmc...; " \
"run mmcargs; " \
"bootm ${loadaddr}\0" \
"loadzimage=load mmc ${mmcdev}:2 ${loadaddr} ${bootdir}/${bootfile}\0" \
"loadfdt=load mmc ${mmcdev}:2 ${fdtaddr} ${bootdir}/${fdtfile}\0" \
"mmcbootfdt=echo Booting with DT from mmc ...; " \
"run mmcargs; " \
"bootz ${loadaddr} - ${fdtaddr}\0" \
"nandboot=echo Booting from nand ...; " \
"run nandargs; " \
"nand read ${loadaddr} 280000 400000; " \
"nand read ${loadaddr} linux; " \
"bootm ${loadaddr}\0" \
#define CONFIG_BOOTCOMMAND \
"mmc dev ${mmcdev}; if mmc rescan; then " \
"if run loadbootscript; then " \
"run bootscript; " \
"else " \
"fi;" \
"if run loadbootenv; then " \
"echo Loaded environment from ${bootenv};" \
"run importbootenv;" \
"fi;" \
"if test -n $uenvcmd; then " \
"echo Running uenvcmd ...;" \
"run uenvcmd;" \
"fi;" \
"if run loaduimage; then " \
"run mmcboot; " \
"else run nandboot; " \
"fi; " \
"fi; " \
"else run nandboot; fi"
"run mmcboot;" \
"fi;" \
"if run loadzimage; then " \
"if test -n $fdtfile; then " \
"if run loadfdt; then " \
"run mmcbootfdt;" \
"fi;" \
"fi;" \
"fi;" \
"fi;" \
"run nandboot; " \
#define CONFIG_AUTO_COMPLETE 1
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
#undef CONFIG_SYS_PROMPT
#define CONFIG_SYS_PROMPT "Overo # "
#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS 16 /* max number of command */
/* args */
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
/* memtest works on */
#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0)
#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
0x01F00000) /* 31MB */
#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */
/* address */
/*
* OMAP3 has 12 GP timers, they can be driven by the system clock
* (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
* This rate is divided by a local divisor.
*/
#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2
#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
/*-----------------------------------------------------------------------
* FLASH and environment organization
*/
/* **** PISMO SUPPORT *** */
/* FLASH and environment organization */
/* Configure the PISMO */
#define PISMO1_NAND_SIZE GPMC_SIZE_128M
#define PISMO1_ONEN_SIZE GPMC_SIZE_128M
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
#if defined(CONFIG_CMD_NAND)
#if defined(CONFIG_NAND)
#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE
#endif
@ -250,67 +193,18 @@
#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
/* Configure SMSC9211 ethernet */
#if defined(CONFIG_CMD_NET)
/*----------------------------------------------------------------------------
* SMSC9211 Ethernet from SMSC9118 family
*----------------------------------------------------------------------------
*/
#define CONFIG_SMC911X
#define CONFIG_SMC911X_32_BIT
#define CONFIG_SMC911X_BASE 0x2C000000
#endif /* (CONFIG_CMD_NET) */
/*
* Leave it at 0x80008000 to allow booting new u-boot.bin with X-loader
* and older u-boot.bin with the new U-Boot SPL.
*/
#define CONFIG_SYS_TEXT_BASE 0x80008000
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
/* Initial RAM setup */
#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
#define CONFIG_SYS_INIT_RAM_SIZE 0x800
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - \
GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_CACHELINE_SIZE 64
/* Defines for SPL */
#define CONFIG_SPL
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_NAND_SIMPLE
#define CONFIG_SPL_TEXT_BASE 0x40200800
#define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */
#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
/* move malloc and bss high to prevent clashing with the main image */
#define CONFIG_SYS_SPL_MALLOC_START 0x87000000
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
#define CONFIG_SPL_BSS_START_ADDR 0x87080000 /* end of minimum RAM */
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1
#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_LIBDISK_SUPPORT
#define CONFIG_SPL_I2C_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_MMC_SUPPORT
#define CONFIG_SPL_FAT_SUPPORT
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SPL_NAND_BASE
#define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_SPL_NAND_ECC
#define CONFIG_SPL_GPIO_SUPPORT
#define CONFIG_SPL_POWER_SUPPORT
#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
/* NAND boot config */
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_COUNT 64

2
include/configs/siemens-am33x-common.h
View File

@ -46,6 +46,8 @@
#define CONFIG_CMD_ECHO
#define CONFIG_CMD_CACHE
#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_ENV_VARS_UBOOT_CONFIG
#ifndef CONFIG_SPL_BUILD
#define CONFIG_ROOTPATH "/opt/eldk"

9
include/configs/ti_omap4_common.h
View File

@ -109,9 +109,13 @@
"importbootenv=echo Importing environment from mmc${mmcdev} ...; " \
"env import -t ${loadaddr} ${filesize}\0" \
"loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \
"loaduimage=load mmc ${mmcdev} ${loadaddr} uImage\0" \
"mmcboot=echo Booting from mmc${mmcdev} ...; " \
"run mmcargs; " \
"bootz ${loadaddr} - ${fdtaddr}\0" \
"uimageboot=echo Booting from mmc${mmcdev} ...; " \
"run mmcargs; " \
"bootm ${loadaddr}\0" \
"findfdt="\
"if test $board_name = sdp4430; then " \
"setenv fdtfile omap4-sdp.dtb; fi; " \
@ -121,6 +125,8 @@
"setenv fdtfile omap4-panda-a4.dtb; fi;" \
"if test $board_name = panda-es; then " \
"setenv fdtfile omap4-panda-es.dtb; fi;" \
"if test $board_name = duovero; then " \
"setenv fdtfile omap4-duovero.dtb; fi;" \
"if test $fdtfile = undefined; then " \
"echo WARNING: Could not determine device tree to use; fi; \0" \
"loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \
@ -144,6 +150,9 @@
"run loadfdt;" \
"run mmcboot; " \
"fi; " \
"if run loaduimage; then " \
"run uimageboot;" \
"fi; " \
"fi"
/*

52
include/configs/zynq-common.h
View File

@ -83,10 +83,27 @@
# define CONFIG_SDHCI
# define CONFIG_ZYNQ_SDHCI
# define CONFIG_CMD_MMC
# define CONFIG_CMD_FAT
#endif
#ifdef CONFIG_ZYNQ_USB
# define CONFIG_USB_EHCI
# define CONFIG_CMD_USB
# define CONFIG_USB_STORAGE
# define CONFIG_USB_EHCI_ZYNQ
# define CONFIG_USB_ULPI_VIEWPORT
# define CONFIG_USB_ULPI
# define CONFIG_EHCI_IS_TDI
# define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#endif
#if defined(CONFIG_ZYNQ_SDHCI) || defined(CONFIG_ZYNQ_USB)
# define CONFIG_SUPPORT_VFAT
# define CONFIG_CMD_FAT
# define CONFIG_CMD_EXT2
# define CONFIG_FAT_WRITE
# define CONFIG_DOS_PARTITION
# define CONFIG_CMD_EXT4
# define CONFIG_CMD_EXT4_WRITE
#endif
#define CONFIG_SYS_I2C_ZYNQ
@ -150,7 +167,13 @@
"bootm ${load_addr}\0" \
"jtagboot=echo TFTPing FIT to RAM... && " \
"tftpboot ${load_addr} ${fit_image} && " \
"bootm ${load_addr}\0"
"bootm ${load_addr}\0" \
"usbboot=if usb start; then " \
"echo Copying FIT from USB to RAM... && " \
"fatload usb 0 ${load_addr} ${fit_image} && " \
"bootm ${load_addr}\0" \
"fi\0"
#define CONFIG_BOOTCOMMAND "run $modeboot"
#define CONFIG_BOOTDELAY 3 /* -1 to Disable autoboot */
#define CONFIG_SYS_LOAD_ADDR 0 /* default? */
@ -165,7 +188,7 @@
#define CONFIG_SYS_LONGHELP
#define CONFIG_CLOCKS
#define CONFIG_CMD_CLK
#define CONFIG_SYS_MAXARGS 15 /* max number of command args */
#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
@ -213,7 +236,7 @@
#define CONFIG_RSA
/* Extend size of kernel image for uncompression */
#define CONFIG_SYS_BOOTM_LEN (20 * 1024 * 1024)
#define CONFIG_SYS_BOOTM_LEN (60 * 1024 * 1024)
/* Boot FreeBSD/vxWorks from an ELF image */
#if defined(CONFIG_ZYNQ_BOOT_FREEBSD)
@ -239,16 +262,10 @@
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/zynq/u-boot-spl.lds"
/* Disable dcache for SPL just for sure */
#ifdef CONFIG_SPL_BUILD
#define CONFIG_SYS_DCACHE_OFF
#undef CONFIG_FPGA
#undef CONFIG_OF_CONTROL
#endif
/* MMC support */
#ifdef CONFIG_ZYNQ_SDHCI0
#define CONFIG_SPL_MMC_SUPPORT
@ -257,7 +274,18 @@
#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1
#define CONFIG_SPL_LIBDISK_SUPPORT
#define CONFIG_SPL_FAT_SUPPORT
#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
#if defined(CONFIG_OF_CONTROL) && defined(CONFIG_OF_SEPARATE)
# define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot-dtb.img"
#else
# define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
#endif
#endif
/* Disable dcache for SPL just for sure */
#ifdef CONFIG_SPL_BUILD
#define CONFIG_SYS_DCACHE_OFF
#undef CONFIG_FPGA
#undef CONFIG_OF_CONTROL
#endif
/* Address in RAM where the parameters must be copied by SPL. */

1
include/configs/zynq_zc70x.h
View File

@ -19,6 +19,7 @@
#define CONFIG_SYS_NO_FLASH
#define CONFIG_ZYNQ_SDHCI0
#define CONFIG_ZYNQ_USB
#define CONFIG_ZYNQ_I2C0
#define CONFIG_ZYNQ_EEPROM
#define CONFIG_ZYNQ_BOOT_FREEBSD

1
include/configs/zynq_zed.h
View File

@ -18,6 +18,7 @@
#define CONFIG_SYS_NO_FLASH
#define CONFIG_ZYNQ_USB
#define CONFIG_ZYNQ_SDHCI0
#define CONFIG_ZYNQ_BOOT_FREEBSD
#define CONFIG_DEFAULT_DEVICE_TREE zynq-zed