ARM: OMAP: I2C: New read, write and probe functions
New i2c_read, i2c_write and i2c_probe functions, tested on OMAP4 (4430/60/70), OMAP5 (5430) and AM335X (3359); should work on older OMAPs and derivatives as well. The only anticipated exception would be the OMAP2420, which shall require driver modification. - Rewritten i2c_read to operate correctly with all types of chips (old function could not read consistent data from some I2C slaves). - Optimised i2c_write. - New i2c_probe, performs write access vs read. The old probe could hang the system under certain conditions (e.g. unconfigured pads). - The read/write/probe functions try to identify unconfigured bus. - Status functions now read irqstatus_raw as per TRM guidelines (except for OMAP243X and OMAP34XX). - Driver now supports up to I2C5 (OMAP5). Signed-off-by: Lubomir Popov <lpopov@mm-sol.com> Tested-by: Heiko Schocher <hs@denx.de>
This commit is contained in:
Lubomir Popov
Tom Rini
parent
7f5eef93af
commit
960187ffa1
@ -18,6 +18,20 @@
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*
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* Adapted for OMAP2420 I2C, r-woodruff2@ti.com
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*
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* Copyright (c) 2013 Lubomir Popov <lpopov@mm-sol.com>, MM Solutions
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* New i2c_read, i2c_write and i2c_probe functions, tested on OMAP4
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* (4430/60/70), OMAP5 (5430) and AM335X (3359); should work on older
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* OMAPs and derivatives as well. The only anticipated exception would
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* be the OMAP2420, which shall require driver modification.
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* - Rewritten i2c_read to operate correctly with all types of chips
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* (old function could not read consistent data from some I2C slaves).
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* - Optimized i2c_write.
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* - New i2c_probe, performs write access vs read. The old probe could
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* hang the system under certain conditions (e.g. unconfigured pads).
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* - The read/write/probe functions try to identify unconfigured bus.
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* - Status functions now read irqstatus_raw as per TRM guidelines
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* (except for OMAP243X and OMAP34XX).
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* - Driver now supports up to I2C5 (OMAP5).
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*/
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#include <common.h>
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@ -31,8 +45,11 @@ DECLARE_GLOBAL_DATA_PTR;
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#define I2C_TIMEOUT 1000
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/* Absolutely safe for status update at 100 kHz I2C: */
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#define I2C_WAIT 200
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static int wait_for_bb(void);
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static u16 wait_for_pin(void);
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static u16 wait_for_event(void);
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static void flush_fifo(void);
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/*
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@ -137,10 +154,14 @@ void i2c_init(int speed, int slaveadd)
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/* own address */
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writew(slaveadd, &i2c_base->oa);
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writew(I2C_CON_EN, &i2c_base->con);
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/* have to enable intrrupts or OMAP i2c module doesn't work */
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#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX)
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/*
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* Have to enable interrupts for OMAP2/3, these IPs don't have
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* an 'irqstatus_raw' register and we shall have to poll 'stat'
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*/
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writew(I2C_IE_XRDY_IE | I2C_IE_RRDY_IE | I2C_IE_ARDY_IE |
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I2C_IE_NACK_IE | I2C_IE_AL_IE, &i2c_base->ie);
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I2C_IE_NACK_IE | I2C_IE_AL_IE, &i2c_base->ie);
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#endif
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udelay(1000);
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flush_fifo();
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writew(0xFFFF, &i2c_base->stat);
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@ -150,88 +171,6 @@ void i2c_init(int speed, int slaveadd)
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bus_initialized[current_bus] = 1;
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}
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static int i2c_read_byte(u8 devaddr, u16 regoffset, u8 alen, u8 *value)
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{
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int i2c_error = 0;
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u16 status;
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int i = 2 - alen;
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u8 tmpbuf[2] = {(regoffset) >> 8, regoffset & 0xff};
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u16 w;
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/* wait until bus not busy */
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if (wait_for_bb())
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return 1;
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/* one byte only */
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writew(alen, &i2c_base->cnt);
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/* set slave address */
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writew(devaddr, &i2c_base->sa);
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/* no stop bit needed here */
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writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT |
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I2C_CON_TRX, &i2c_base->con);
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/* send register offset */
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while (1) {
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status = wait_for_pin();
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if (status == 0 || status & I2C_STAT_NACK) {
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i2c_error = 1;
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goto read_exit;
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}
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if (status & I2C_STAT_XRDY) {
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w = tmpbuf[i++];
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#if !(defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \
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defined(CONFIG_OMAP44XX) || defined(CONFIG_AM33XX) || \
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defined(CONFIG_OMAP54XX))
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w |= tmpbuf[i++] << 8;
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#endif
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writew(w, &i2c_base->data);
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writew(I2C_STAT_XRDY, &i2c_base->stat);
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}
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if (status & I2C_STAT_ARDY) {
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writew(I2C_STAT_ARDY, &i2c_base->stat);
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break;
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}
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}
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/* set slave address */
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writew(devaddr, &i2c_base->sa);
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/* read one byte from slave */
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writew(1, &i2c_base->cnt);
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/* need stop bit here */
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writew(I2C_CON_EN | I2C_CON_MST |
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I2C_CON_STT | I2C_CON_STP,
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&i2c_base->con);
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/* receive data */
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while (1) {
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status = wait_for_pin();
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if (status == 0 || status & I2C_STAT_NACK) {
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i2c_error = 1;
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goto read_exit;
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}
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if (status & I2C_STAT_RRDY) {
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#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \
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defined(CONFIG_OMAP44XX) || defined(CONFIG_AM33XX) || \
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defined(CONFIG_OMAP54XX)
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*value = readb(&i2c_base->data);
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#else
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*value = readw(&i2c_base->data);
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#endif
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writew(I2C_STAT_RRDY, &i2c_base->stat);
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}
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if (status & I2C_STAT_ARDY) {
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writew(I2C_STAT_ARDY, &i2c_base->stat);
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break;
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}
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}
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read_exit:
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flush_fifo();
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writew(0xFFFF, &i2c_base->stat);
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writew(0, &i2c_base->cnt);
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return i2c_error;
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}
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static void flush_fifo(void)
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{ u16 stat;
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@ -241,13 +180,7 @@ static void flush_fifo(void)
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while (1) {
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stat = readw(&i2c_base->stat);
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if (stat == I2C_STAT_RRDY) {
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#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \
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defined(CONFIG_OMAP44XX) || defined(CONFIG_AM33XX) || \
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defined(CONFIG_OMAP54XX)
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readb(&i2c_base->data);
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#else
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readw(&i2c_base->data);
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#endif
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writew(I2C_STAT_RRDY, &i2c_base->stat);
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udelay(1000);
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} else
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@ -255,6 +188,10 @@ static void flush_fifo(void)
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}
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}
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/*
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* i2c_probe: Use write access. Allows to identify addresses that are
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* write-only (like the config register of dual-port EEPROMs)
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*/
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int i2c_probe(uchar chip)
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{
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u16 status;
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@ -263,61 +200,81 @@ int i2c_probe(uchar chip)
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if (chip == readw(&i2c_base->oa))
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return res;
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/* wait until bus not busy */
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/* Wait until bus is free */
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if (wait_for_bb())
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return res;
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/* try to read one byte */
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writew(1, &i2c_base->cnt);
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/* set slave address */
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/* No data transfer, slave addr only */
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writew(0, &i2c_base->cnt);
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/* Set slave address */
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writew(chip, &i2c_base->sa);
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/* stop bit needed here */
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writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP, &i2c_base->con);
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/* Stop bit needed here */
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writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX |
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I2C_CON_STP, &i2c_base->con);
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while (1) {
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status = wait_for_pin();
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if (status == 0 || status & I2C_STAT_AL) {
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res = 1;
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goto probe_exit;
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}
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if (status & I2C_STAT_NACK) {
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res = 1;
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writew(0xff, &i2c_base->stat);
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writew (readw (&i2c_base->con) | I2C_CON_STP, &i2c_base->con);
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status = wait_for_event();
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if (wait_for_bb())
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res = 1;
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if ((status & ~I2C_STAT_XRDY) == 0 || (status & I2C_STAT_AL)) {
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/*
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* With current high-level command implementation, notifying
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* the user shall flood the console with 127 messages. If
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* silent exit is desired upon unconfigured bus, remove the
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* following 'if' section:
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*/
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if (status == I2C_STAT_XRDY)
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printf("i2c_probe: pads on bus %d probably not configured (status=0x%x)\n",
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current_bus, status);
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break;
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}
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if (status & I2C_STAT_ARDY) {
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writew(I2C_STAT_ARDY, &i2c_base->stat);
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break;
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}
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if (status & I2C_STAT_RRDY) {
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res = 0;
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#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \
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defined(CONFIG_OMAP44XX) || defined(CONFIG_AM33XX) || \
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defined(CONFIG_OMAP54XX)
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readb(&i2c_base->data);
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#else
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readw(&i2c_base->data);
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#endif
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writew(I2C_STAT_RRDY, &i2c_base->stat);
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}
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goto pr_exit;
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}
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probe_exit:
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/* Check for ACK (!NAK) */
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if (!(status & I2C_STAT_NACK)) {
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res = 0; /* Device found */
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udelay(I2C_WAIT); /* Required by AM335X in SPL */
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/* Abort transfer (force idle state) */
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writew(I2C_CON_MST | I2C_CON_TRX, &i2c_base->con); /* Reset */
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udelay(1000);
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writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_TRX |
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I2C_CON_STP, &i2c_base->con); /* STP */
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}
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pr_exit:
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flush_fifo();
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/* don't allow any more data in... we don't want it. */
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writew(0, &i2c_base->cnt);
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writew(0xFFFF, &i2c_base->stat);
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writew(0, &i2c_base->cnt);
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return res;
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}
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/*
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* i2c_read: Function now uses a single I2C read transaction with bulk transfer
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* of the requested number of bytes (note that the 'i2c md' command
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* limits this to 16 bytes anyway). If CONFIG_I2C_REPEATED_START is
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* defined in the board config header, this transaction shall be with
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* Repeated Start (Sr) between the address and data phases; otherwise
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* Stop-Start (P-S) shall be used (some I2C chips do require a P-S).
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* The address (reg offset) may be 0, 1 or 2 bytes long.
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* Function now reads correctly from chips that return more than one
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* byte of data per addressed register (like TI temperature sensors),
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* or that do not need a register address at all (such as some clock
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* distributors).
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*/
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int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
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{
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int i;
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int i2c_error = 0;
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u16 status;
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if (alen < 0) {
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puts("I2C read: addr len < 0\n");
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return 1;
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}
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if (len < 0) {
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puts("I2C read: data len < 0\n");
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return 1;
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}
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if (buffer == NULL) {
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puts("I2C read: NULL pointer passed\n");
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return 1;
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}
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if (alen > 2) {
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printf("I2C read: addr len %d not supported\n", alen);
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@ -329,24 +286,122 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
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return 1;
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}
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for (i = 0; i < len; i++) {
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if (i2c_read_byte(chip, addr + i, alen, &buffer[i])) {
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puts("I2C read: I/O error\n");
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i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
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return 1;
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/* Wait until bus not busy */
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if (wait_for_bb())
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return 1;
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/* Zero, one or two bytes reg address (offset) */
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writew(alen, &i2c_base->cnt);
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/* Set slave address */
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writew(chip, &i2c_base->sa);
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if (alen) {
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/* Must write reg offset first */
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#ifdef CONFIG_I2C_REPEATED_START
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/* No stop bit, use Repeated Start (Sr) */
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writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT |
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I2C_CON_TRX, &i2c_base->con);
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#else
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/* Stop - Start (P-S) */
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writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP |
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I2C_CON_TRX, &i2c_base->con);
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#endif
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/* Send register offset */
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while (1) {
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status = wait_for_event();
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/* Try to identify bus that is not padconf'd for I2C */
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if (status == I2C_STAT_XRDY) {
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i2c_error = 2;
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printf("i2c_read (addr phase): pads on bus %d probably not configured (status=0x%x)\n",
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current_bus, status);
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goto rd_exit;
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}
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if (status == 0 || status & I2C_STAT_NACK) {
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i2c_error = 1;
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printf("i2c_read: error waiting for addr ACK (status=0x%x)\n",
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status);
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goto rd_exit;
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}
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if (alen) {
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if (status & I2C_STAT_XRDY) {
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alen--;
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/* Do we have to use byte access? */
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writeb((addr >> (8 * alen)) & 0xff,
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&i2c_base->data);
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writew(I2C_STAT_XRDY, &i2c_base->stat);
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}
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}
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if (status & I2C_STAT_ARDY) {
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writew(I2C_STAT_ARDY, &i2c_base->stat);
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break;
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}
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}
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}
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/* Set slave address */
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writew(chip, &i2c_base->sa);
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/* Read len bytes from slave */
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writew(len, &i2c_base->cnt);
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/* Need stop bit here */
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writew(I2C_CON_EN | I2C_CON_MST |
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I2C_CON_STT | I2C_CON_STP,
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&i2c_base->con);
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/* Receive data */
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while (1) {
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status = wait_for_event();
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/*
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* Try to identify bus that is not padconf'd for I2C. This
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* state could be left over from previous transactions if
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* the address phase is skipped due to alen=0.
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*/
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if (status == I2C_STAT_XRDY) {
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i2c_error = 2;
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printf("i2c_read (data phase): pads on bus %d probably not configured (status=0x%x)\n",
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current_bus, status);
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goto rd_exit;
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}
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if (status == 0 || status & I2C_STAT_NACK) {
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i2c_error = 1;
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goto rd_exit;
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}
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if (status & I2C_STAT_RRDY) {
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*buffer++ = readb(&i2c_base->data);
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writew(I2C_STAT_RRDY, &i2c_base->stat);
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}
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if (status & I2C_STAT_ARDY) {
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writew(I2C_STAT_ARDY, &i2c_base->stat);
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break;
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}
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}
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return 0;
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rd_exit:
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flush_fifo();
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writew(0xFFFF, &i2c_base->stat);
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writew(0, &i2c_base->cnt);
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return i2c_error;
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}
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/* i2c_write: Address (reg offset) may be 0, 1 or 2 bytes long. */
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int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
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{
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int i;
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u16 status;
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int i2c_error = 0;
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u16 w;
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u8 tmpbuf[2] = {addr >> 8, addr & 0xff};
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if (alen < 0) {
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puts("I2C write: addr len < 0\n");
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return 1;
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}
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if (len < 0) {
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puts("I2C write: data len < 0\n");
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return 1;
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}
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if (buffer == NULL) {
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puts("I2C write: NULL pointer passed\n");
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return 1;
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}
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if (alen > 2) {
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printf("I2C write: addr len %d not supported\n", alen);
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@ -355,92 +410,137 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
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if (addr + len > (1 << 16)) {
|
||||
printf("I2C write: address 0x%x + 0x%x out of range\n",
|
||||
addr, len);
|
||||
addr, len);
|
||||
return 1;
|
||||
}
|
||||
|
||||
/* wait until bus not busy */
|
||||
/* Wait until bus not busy */
|
||||
if (wait_for_bb())
|
||||
return 1;
|
||||
|
||||
/* start address phase - will write regoffset + len bytes data */
|
||||
/* TODO consider case when !CONFIG_OMAP243X/34XX/44XX */
|
||||
/* Start address phase - will write regoffset + len bytes data */
|
||||
writew(alen + len, &i2c_base->cnt);
|
||||
/* set slave address */
|
||||
/* Set slave address */
|
||||
writew(chip, &i2c_base->sa);
|
||||
/* stop bit needed here */
|
||||
/* Stop bit needed here */
|
||||
writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX |
|
||||
I2C_CON_STP, &i2c_base->con);
|
||||
|
||||
/* Send address and data */
|
||||
for (i = -alen; i < len; i++) {
|
||||
status = wait_for_pin();
|
||||
I2C_CON_STP, &i2c_base->con);
|
||||
|
||||
while (alen) {
|
||||
/* Must write reg offset (one or two bytes) */
|
||||
status = wait_for_event();
|
||||
/* Try to identify bus that is not padconf'd for I2C */
|
||||
if (status == I2C_STAT_XRDY) {
|
||||
i2c_error = 2;
|
||||
printf("i2c_write: pads on bus %d probably not configured (status=0x%x)\n",
|
||||
current_bus, status);
|
||||
goto wr_exit;
|
||||
}
|
||||
if (status == 0 || status & I2C_STAT_NACK) {
|
||||
i2c_error = 1;
|
||||
printf("i2c error waiting for data ACK (status=0x%x)\n",
|
||||
status);
|
||||
goto write_exit;
|
||||
printf("i2c_write: error waiting for addr ACK (status=0x%x)\n",
|
||||
status);
|
||||
goto wr_exit;
|
||||
}
|
||||
|
||||
if (status & I2C_STAT_XRDY) {
|
||||
w = (i < 0) ? tmpbuf[2+i] : buffer[i];
|
||||
#if !(defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \
|
||||
defined(CONFIG_OMAP44XX) || defined(CONFIG_AM33XX) || \
|
||||
defined(CONFIG_OMAP54XX))
|
||||
w |= ((++i < 0) ? tmpbuf[2+i] : buffer[i]) << 8;
|
||||
#endif
|
||||
writew(w, &i2c_base->data);
|
||||
alen--;
|
||||
writeb((addr >> (8 * alen)) & 0xff, &i2c_base->data);
|
||||
writew(I2C_STAT_XRDY, &i2c_base->stat);
|
||||
} else {
|
||||
i2c_error = 1;
|
||||
printf("i2c bus not ready for Tx (i=%d)\n", i);
|
||||
goto write_exit;
|
||||
printf("i2c_write: bus not ready for addr Tx (status=0x%x)\n",
|
||||
status);
|
||||
goto wr_exit;
|
||||
}
|
||||
}
|
||||
/* Address phase is over, now write data */
|
||||
for (i = 0; i < len; i++) {
|
||||
status = wait_for_event();
|
||||
if (status == 0 || status & I2C_STAT_NACK) {
|
||||
i2c_error = 1;
|
||||
printf("i2c_write: error waiting for data ACK (status=0x%x)\n",
|
||||
status);
|
||||
goto wr_exit;
|
||||
}
|
||||
if (status & I2C_STAT_XRDY) {
|
||||
writeb(buffer[i], &i2c_base->data);
|
||||
writew(I2C_STAT_XRDY, &i2c_base->stat);
|
||||
} else {
|
||||
i2c_error = 1;
|
||||
printf("i2c_write: bus not ready for data Tx (i=%d)\n",
|
||||
i);
|
||||
goto wr_exit;
|
||||
}
|
||||
}
|
||||
|
||||
write_exit:
|
||||
wr_exit:
|
||||
flush_fifo();
|
||||
writew(0xFFFF, &i2c_base->stat);
|
||||
writew(0, &i2c_base->cnt);
|
||||
return i2c_error;
|
||||
}
|
||||
|
||||
/*
|
||||
* Wait for the bus to be free by checking the Bus Busy (BB)
|
||||
* bit to become clear
|
||||
*/
|
||||
static int wait_for_bb(void)
|
||||
{
|
||||
int timeout = I2C_TIMEOUT;
|
||||
u16 stat;
|
||||
|
||||
writew(0xFFFF, &i2c_base->stat); /* clear current interrupts...*/
|
||||
#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX)
|
||||
while ((stat = readw(&i2c_base->stat) & I2C_STAT_BB) && timeout--) {
|
||||
#else
|
||||
/* Read RAW status */
|
||||
while ((stat = readw(&i2c_base->irqstatus_raw) &
|
||||
I2C_STAT_BB) && timeout--) {
|
||||
#endif
|
||||
writew(stat, &i2c_base->stat);
|
||||
udelay(1000);
|
||||
udelay(I2C_WAIT);
|
||||
}
|
||||
|
||||
if (timeout <= 0) {
|
||||
printf("timed out in wait_for_bb: I2C_STAT=%x\n",
|
||||
readw(&i2c_base->stat));
|
||||
printf("Timed out in wait_for_bb: status=%04x\n",
|
||||
stat);
|
||||
return 1;
|
||||
}
|
||||
writew(0xFFFF, &i2c_base->stat); /* clear delayed stuff*/
|
||||
return 0;
|
||||
}
|
||||
|
||||
static u16 wait_for_pin(void)
|
||||
/*
|
||||
* Wait for the I2C controller to complete current action
|
||||
* and update status
|
||||
*/
|
||||
static u16 wait_for_event(void)
|
||||
{
|
||||
u16 status;
|
||||
int timeout = I2C_TIMEOUT;
|
||||
|
||||
do {
|
||||
udelay(1000);
|
||||
udelay(I2C_WAIT);
|
||||
#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX)
|
||||
status = readw(&i2c_base->stat);
|
||||
#else
|
||||
/* Read RAW status */
|
||||
status = readw(&i2c_base->irqstatus_raw);
|
||||
#endif
|
||||
} while (!(status &
|
||||
(I2C_STAT_ROVR | I2C_STAT_XUDF | I2C_STAT_XRDY |
|
||||
I2C_STAT_RRDY | I2C_STAT_ARDY | I2C_STAT_NACK |
|
||||
I2C_STAT_AL)) && timeout--);
|
||||
|
||||
if (timeout <= 0) {
|
||||
printf("timed out in wait_for_pin: I2C_STAT=%x\n",
|
||||
readw(&i2c_base->stat));
|
||||
printf("Timed out in wait_for_event: status=%04x\n",
|
||||
status);
|
||||
/*
|
||||
* If status is still 0 here, probably the bus pads have
|
||||
* not been configured for I2C, and/or pull-ups are missing.
|
||||
*/
|
||||
printf("Check if pads/pull-ups of bus %d are properly configured\n",
|
||||
current_bus);
|
||||
writew(0xFFFF, &i2c_base->stat);
|
||||
status = 0;
|
||||
}
|
||||
@ -450,28 +550,36 @@ static u16 wait_for_pin(void)
|
||||
|
||||
int i2c_set_bus_num(unsigned int bus)
|
||||
{
|
||||
if ((bus < 0) || (bus >= I2C_BUS_MAX)) {
|
||||
printf("Bad bus: %d\n", bus);
|
||||
if (bus >= I2C_BUS_MAX) {
|
||||
printf("Bad bus: %x\n", bus);
|
||||
return -1;
|
||||
}
|
||||
|
||||
#if I2C_BUS_MAX == 4
|
||||
if (bus == 3)
|
||||
i2c_base = (struct i2c *)I2C_BASE4;
|
||||
else
|
||||
if (bus == 2)
|
||||
i2c_base = (struct i2c *)I2C_BASE3;
|
||||
else
|
||||
#endif
|
||||
#if I2C_BUS_MAX == 3
|
||||
if (bus == 2)
|
||||
i2c_base = (struct i2c *)I2C_BASE3;
|
||||
else
|
||||
#endif
|
||||
if (bus == 1)
|
||||
i2c_base = (struct i2c *)I2C_BASE2;
|
||||
else
|
||||
switch (bus) {
|
||||
default:
|
||||
bus = 0; /* Fall through */
|
||||
case 0:
|
||||
i2c_base = (struct i2c *)I2C_BASE1;
|
||||
break;
|
||||
case 1:
|
||||
i2c_base = (struct i2c *)I2C_BASE2;
|
||||
break;
|
||||
#if (I2C_BUS_MAX > 2)
|
||||
case 2:
|
||||
i2c_base = (struct i2c *)I2C_BASE3;
|
||||
break;
|
||||
#if (I2C_BUS_MAX > 3)
|
||||
case 3:
|
||||
i2c_base = (struct i2c *)I2C_BASE4;
|
||||
break;
|
||||
#if (I2C_BUS_MAX > 4)
|
||||
case 4:
|
||||
i2c_base = (struct i2c *)I2C_BASE5;
|
||||
break;
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
}
|
||||
|
||||
current_bus = bus;
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user