ARM: AM33xx: Cleanup dplls data
Locking sequence for all the dplls is same. In the current code same sequence is done repeatedly for each dpll. Instead have a generic function for locking dplls and pass dpll data to that function. This is derived from OMAP4 boards. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Tested-by: Heiko Schocher <hs@denx.de> Acked-by: Heiko Schocher <hs@denx.de>
This commit is contained in:
parent
fdce7b633a
commit
94d77fb656
arch/arm
cpu/armv7/am33xx
include/asm/arch-am33xx
board
@ -10,6 +10,7 @@ LIB = $(obj)lib$(SOC).o
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COBJS-$(CONFIG_AM33XX) += clock_am33xx.o
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COBJS-$(CONFIG_TI814X) += clock_ti814x.o
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COBJS-$(CONFIG_AM33XX) += clock.o
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COBJS += sys_info.o
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COBJS += mem.o
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COBJS += ddr.o
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111
arch/arm/cpu/armv7/am33xx/clock.c
Normal file
111
arch/arm/cpu/armv7/am33xx/clock.c
Normal file
@ -0,0 +1,111 @@
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/*
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* clock.c
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*
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* Clock initialization for AM33XX boards.
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* Derived from OMAP4 boards
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*
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* Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/io.h>
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static void setup_post_dividers(const struct dpll_regs *dpll_regs,
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const struct dpll_params *params)
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{
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/* Setup post-dividers */
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if (params->m2 >= 0)
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writel(params->m2, dpll_regs->cm_div_m2_dpll);
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if (params->m3 >= 0)
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writel(params->m3, dpll_regs->cm_div_m3_dpll);
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if (params->m4 >= 0)
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writel(params->m4, dpll_regs->cm_div_m4_dpll);
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if (params->m5 >= 0)
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writel(params->m5, dpll_regs->cm_div_m5_dpll);
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if (params->m6 >= 0)
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writel(params->m6, dpll_regs->cm_div_m6_dpll);
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}
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static inline void do_lock_dpll(const struct dpll_regs *dpll_regs)
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{
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clrsetbits_le32(dpll_regs->cm_clkmode_dpll,
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CM_CLKMODE_DPLL_DPLL_EN_MASK,
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DPLL_EN_LOCK << CM_CLKMODE_DPLL_EN_SHIFT);
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}
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static inline void wait_for_lock(const struct dpll_regs *dpll_regs)
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{
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if (!wait_on_value(ST_DPLL_CLK_MASK, ST_DPLL_CLK_MASK,
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(void *)dpll_regs->cm_idlest_dpll, LDELAY)) {
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printf("DPLL locking failed for 0x%x\n",
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dpll_regs->cm_clkmode_dpll);
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hang();
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}
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}
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static inline void do_bypass_dpll(const struct dpll_regs *dpll_regs)
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{
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clrsetbits_le32(dpll_regs->cm_clkmode_dpll,
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CM_CLKMODE_DPLL_DPLL_EN_MASK,
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DPLL_EN_MN_BYPASS << CM_CLKMODE_DPLL_EN_SHIFT);
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}
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static inline void wait_for_bypass(const struct dpll_regs *dpll_regs)
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{
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if (!wait_on_value(ST_DPLL_CLK_MASK, 0,
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(void *)dpll_regs->cm_idlest_dpll, LDELAY)) {
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printf("Bypassing DPLL failed 0x%x\n",
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dpll_regs->cm_clkmode_dpll);
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}
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}
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static void bypass_dpll(const struct dpll_regs *dpll_regs)
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{
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do_bypass_dpll(dpll_regs);
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wait_for_bypass(dpll_regs);
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}
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void do_setup_dpll(const struct dpll_regs *dpll_regs,
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const struct dpll_params *params)
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{
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u32 temp;
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if (!params)
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return;
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temp = readl(dpll_regs->cm_clksel_dpll);
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bypass_dpll(dpll_regs);
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/* Set M & N */
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temp &= ~CM_CLKSEL_DPLL_M_MASK;
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temp |= (params->m << CM_CLKSEL_DPLL_M_SHIFT) & CM_CLKSEL_DPLL_M_MASK;
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temp &= ~CM_CLKSEL_DPLL_N_MASK;
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temp |= (params->n << CM_CLKSEL_DPLL_N_SHIFT) & CM_CLKSEL_DPLL_N_MASK;
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writel(temp, dpll_regs->cm_clksel_dpll);
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setup_post_dividers(dpll_regs, params);
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/* Wait till the DPLL locks */
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do_lock_dpll(dpll_regs);
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wait_for_lock(dpll_regs);
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}
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void setup_dplls(void)
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{
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const struct dpll_params *params;
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do_setup_dpll(&dpll_core_regs, &dpll_core);
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do_setup_dpll(&dpll_mpu_regs, &dpll_mpu);
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do_setup_dpll(&dpll_per_regs, &dpll_per);
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writel(0x300, &cmwkup->clkdcoldodpllper);
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params = get_dpll_ddr_params();
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do_setup_dpll(&dpll_ddr_regs, params);
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}
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@ -18,56 +18,51 @@
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#define PRCM_FORCE_WAKEUP 0x2
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#define PRCM_FUNCTL 0x0
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#define PRCM_EMIF_CLK_ACTIVITY BIT(2)
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#define PRCM_L3_GCLK_ACTIVITY BIT(4)
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#define PLL_BYPASS_MODE 0x4
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#define ST_MN_BYPASS 0x00000100
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#define ST_DPLL_CLK 0x00000001
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#define CLK_SEL_MASK 0x7ffff
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#define CLK_DIV_MASK 0x1f
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#define CLK_DIV2_MASK 0x7f
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#define CLK_SEL_SHIFT 0x8
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#define CLK_MODE_SEL 0x7
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#define CLK_MODE_MASK 0xfffffff8
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#define CLK_DIV_SEL 0xFFFFFFE0
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#define CPGMAC0_IDLE 0x30000
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#define DPLL_CLKDCOLDO_GATE_CTRL 0x300
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#define OSC (V_OSCK/1000000)
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#define MPUPLL_M CONFIG_SYS_MPUCLK
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#define MPUPLL_N (OSC-1)
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#define MPUPLL_M2 1
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/* Core PLL Fdll = 1 GHZ, */
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#define COREPLL_M 1000
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#define COREPLL_N (OSC-1)
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#define COREPLL_M4 10 /* CORE_CLKOUTM4 = 200 MHZ */
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#define COREPLL_M5 8 /* CORE_CLKOUTM5 = 250 MHZ */
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#define COREPLL_M6 4 /* CORE_CLKOUTM6 = 500 MHZ */
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/*
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* USB PHY clock is 960 MHZ. Since, this comes directly from Fdll, Fdll
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* frequency needs to be set to 960 MHZ. Hence,
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* For clkout = 192 MHZ, Fdll = 960 MHZ, divider values are given below
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*/
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#define PERPLL_M 960
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#define PERPLL_N (OSC-1)
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#define PERPLL_M2 5
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/* DDR Freq is 266 MHZ for now */
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/* Set Fdll = 400 MHZ , Fdll = M * 2 * CLKINP/ N + 1; clkout = Fdll /(2 * M2) */
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#define DDRPLL_M 266
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#define DDRPLL_N (OSC-1)
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#define DDRPLL_M2 1
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const struct cm_perpll *cmper = (struct cm_perpll *)CM_PER;
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const struct cm_wkuppll *cmwkup = (struct cm_wkuppll *)CM_WKUP;
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const struct cm_dpll *cmdpll = (struct cm_dpll *)CM_DPLL;
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const struct cm_rtc *cmrtc = (struct cm_rtc *)CM_RTC;
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const struct dpll_regs dpll_mpu_regs = {
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.cm_clkmode_dpll = CM_WKUP + 0x88,
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.cm_idlest_dpll = CM_WKUP + 0x20,
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.cm_clksel_dpll = CM_WKUP + 0x2C,
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.cm_div_m2_dpll = CM_WKUP + 0xA8,
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};
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const struct dpll_regs dpll_core_regs = {
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.cm_clkmode_dpll = CM_WKUP + 0x90,
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.cm_idlest_dpll = CM_WKUP + 0x5C,
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.cm_clksel_dpll = CM_WKUP + 0x68,
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.cm_div_m4_dpll = CM_WKUP + 0x80,
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.cm_div_m5_dpll = CM_WKUP + 0x84,
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.cm_div_m6_dpll = CM_WKUP + 0xD8,
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};
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const struct dpll_regs dpll_per_regs = {
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.cm_clkmode_dpll = CM_WKUP + 0x8C,
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.cm_idlest_dpll = CM_WKUP + 0x70,
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.cm_clksel_dpll = CM_WKUP + 0x9C,
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.cm_div_m2_dpll = CM_WKUP + 0xAC,
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};
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const struct dpll_regs dpll_ddr_regs = {
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.cm_clkmode_dpll = CM_WKUP + 0x94,
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.cm_idlest_dpll = CM_WKUP + 0x34,
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.cm_clksel_dpll = CM_WKUP + 0x40,
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.cm_div_m2_dpll = CM_WKUP + 0xA0,
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};
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const struct dpll_params dpll_mpu = {
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CONFIG_SYS_MPUCLK, OSC-1, 1, -1, -1, -1, -1};
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const struct dpll_params dpll_core = {
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1000, OSC-1, -1, -1, 10, 8, 4};
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const struct dpll_params dpll_per = {
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960, OSC-1, 5, -1, -1, -1, -1};
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static void enable_interface_clocks(void)
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{
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/* Enable all the Interconnect Modules */
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@ -238,142 +233,6 @@ static void enable_per_clocks(void)
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;
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}
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void mpu_pll_config_val(int mpull_m)
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{
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u32 clkmode, clksel, div_m2;
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clkmode = readl(&cmwkup->clkmoddpllmpu);
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clksel = readl(&cmwkup->clkseldpllmpu);
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div_m2 = readl(&cmwkup->divm2dpllmpu);
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/* Set the PLL to bypass Mode */
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writel(PLL_BYPASS_MODE, &cmwkup->clkmoddpllmpu);
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while (readl(&cmwkup->idlestdpllmpu) != ST_MN_BYPASS)
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;
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clksel = clksel & (~CLK_SEL_MASK);
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clksel = clksel | ((mpull_m << CLK_SEL_SHIFT) | MPUPLL_N);
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writel(clksel, &cmwkup->clkseldpllmpu);
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div_m2 = div_m2 & ~CLK_DIV_MASK;
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div_m2 = div_m2 | MPUPLL_M2;
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writel(div_m2, &cmwkup->divm2dpllmpu);
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clkmode = clkmode | CLK_MODE_SEL;
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writel(clkmode, &cmwkup->clkmoddpllmpu);
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while (readl(&cmwkup->idlestdpllmpu) != ST_DPLL_CLK)
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;
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}
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static void mpu_pll_config(void)
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{
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mpu_pll_config_val(CONFIG_SYS_MPUCLK);
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}
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static void core_pll_config(void)
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{
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u32 clkmode, clksel, div_m4, div_m5, div_m6;
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clkmode = readl(&cmwkup->clkmoddpllcore);
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clksel = readl(&cmwkup->clkseldpllcore);
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div_m4 = readl(&cmwkup->divm4dpllcore);
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div_m5 = readl(&cmwkup->divm5dpllcore);
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div_m6 = readl(&cmwkup->divm6dpllcore);
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/* Set the PLL to bypass Mode */
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writel(PLL_BYPASS_MODE, &cmwkup->clkmoddpllcore);
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while (readl(&cmwkup->idlestdpllcore) != ST_MN_BYPASS)
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;
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clksel = clksel & (~CLK_SEL_MASK);
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clksel = clksel | ((COREPLL_M << CLK_SEL_SHIFT) | COREPLL_N);
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writel(clksel, &cmwkup->clkseldpllcore);
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div_m4 = div_m4 & ~CLK_DIV_MASK;
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div_m4 = div_m4 | COREPLL_M4;
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writel(div_m4, &cmwkup->divm4dpllcore);
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div_m5 = div_m5 & ~CLK_DIV_MASK;
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div_m5 = div_m5 | COREPLL_M5;
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writel(div_m5, &cmwkup->divm5dpllcore);
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div_m6 = div_m6 & ~CLK_DIV_MASK;
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div_m6 = div_m6 | COREPLL_M6;
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writel(div_m6, &cmwkup->divm6dpllcore);
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clkmode = clkmode | CLK_MODE_SEL;
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writel(clkmode, &cmwkup->clkmoddpllcore);
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while (readl(&cmwkup->idlestdpllcore) != ST_DPLL_CLK)
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;
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}
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static void per_pll_config(void)
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{
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u32 clkmode, clksel, div_m2;
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clkmode = readl(&cmwkup->clkmoddpllper);
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clksel = readl(&cmwkup->clkseldpllper);
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div_m2 = readl(&cmwkup->divm2dpllper);
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/* Set the PLL to bypass Mode */
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writel(PLL_BYPASS_MODE, &cmwkup->clkmoddpllper);
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while (readl(&cmwkup->idlestdpllper) != ST_MN_BYPASS)
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;
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clksel = clksel & (~CLK_SEL_MASK);
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clksel = clksel | ((PERPLL_M << CLK_SEL_SHIFT) | PERPLL_N);
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writel(clksel, &cmwkup->clkseldpllper);
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div_m2 = div_m2 & ~CLK_DIV2_MASK;
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div_m2 = div_m2 | PERPLL_M2;
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writel(div_m2, &cmwkup->divm2dpllper);
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clkmode = clkmode | CLK_MODE_SEL;
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writel(clkmode, &cmwkup->clkmoddpllper);
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while (readl(&cmwkup->idlestdpllper) != ST_DPLL_CLK)
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;
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writel(DPLL_CLKDCOLDO_GATE_CTRL, &cmwkup->clkdcoldodpllper);
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}
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void ddr_pll_config(unsigned int ddrpll_m)
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{
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u32 clkmode, clksel, div_m2;
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clkmode = readl(&cmwkup->clkmoddpllddr);
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clksel = readl(&cmwkup->clkseldpllddr);
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div_m2 = readl(&cmwkup->divm2dpllddr);
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/* Set the PLL to bypass Mode */
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clkmode = (clkmode & CLK_MODE_MASK) | PLL_BYPASS_MODE;
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writel(clkmode, &cmwkup->clkmoddpllddr);
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/* Wait till bypass mode is enabled */
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while ((readl(&cmwkup->idlestdpllddr) & ST_MN_BYPASS)
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!= ST_MN_BYPASS)
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;
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clksel = clksel & (~CLK_SEL_MASK);
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clksel = clksel | ((ddrpll_m << CLK_SEL_SHIFT) | DDRPLL_N);
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writel(clksel, &cmwkup->clkseldpllddr);
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div_m2 = div_m2 & CLK_DIV_SEL;
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div_m2 = div_m2 | DDRPLL_M2;
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writel(div_m2, &cmwkup->divm2dpllddr);
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clkmode = (clkmode & CLK_MODE_MASK) | CLK_MODE_SEL;
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writel(clkmode, &cmwkup->clkmoddpllddr);
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/* Wait till dpll is locked */
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while ((readl(&cmwkup->idlestdpllddr) & ST_DPLL_CLK) != ST_DPLL_CLK)
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;
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}
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void enable_emif_clocks(void)
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{
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/* Enable the EMIF_FW Functional clock */
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@ -390,10 +249,7 @@ void enable_emif_clocks(void)
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*/
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void pll_init()
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{
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mpu_pll_config();
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core_pll_config();
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per_pll_config();
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setup_dplls();
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/* Enable the required interconnect clocks */
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enable_interface_clocks();
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@ -79,6 +79,10 @@ static void config_vtp(int nr)
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;
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}
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void __weak ddr_pll_config(unsigned int ddrpll_m)
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{
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}
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void config_ddr(unsigned int pll, unsigned int ioctrl,
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const struct ddr_data *data, const struct cmd_control *ctrl,
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const struct emif_regs *regs, int nr)
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@ -13,4 +13,74 @@
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#include <asm/arch/clocks_am33xx.h>
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#define LDELAY 1000000
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/* CM_CLKMODE_DPLL */
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#define CM_CLKMODE_DPLL_REGM4XEN_SHIFT 11
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#define CM_CLKMODE_DPLL_REGM4XEN_MASK (1 << 11)
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#define CM_CLKMODE_DPLL_LPMODE_EN_SHIFT 10
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#define CM_CLKMODE_DPLL_LPMODE_EN_MASK (1 << 10)
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#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_SHIFT 9
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#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK (1 << 9)
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#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_SHIFT 8
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#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK (1 << 8)
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#define CM_CLKMODE_DPLL_RAMP_RATE_SHIFT 5
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#define CM_CLKMODE_DPLL_RAMP_RATE_MASK (0x7 << 5)
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#define CM_CLKMODE_DPLL_EN_SHIFT 0
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#define CM_CLKMODE_DPLL_EN_MASK (0x7 << 0)
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#define CM_CLKMODE_DPLL_DPLL_EN_SHIFT 0
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#define CM_CLKMODE_DPLL_DPLL_EN_MASK 7
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#define DPLL_EN_STOP 1
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#define DPLL_EN_MN_BYPASS 4
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#define DPLL_EN_LOW_POWER_BYPASS 5
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#define DPLL_EN_LOCK 7
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/* CM_IDLEST_DPLL fields */
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||||
#define ST_DPLL_CLK_MASK 1
|
||||
|
||||
/* CM_CLKSEL_DPLL */
|
||||
#define CM_CLKSEL_DPLL_M_SHIFT 8
|
||||
#define CM_CLKSEL_DPLL_M_MASK (0x7FF << 8)
|
||||
#define CM_CLKSEL_DPLL_N_SHIFT 0
|
||||
#define CM_CLKSEL_DPLL_N_MASK 0x7F
|
||||
|
||||
struct dpll_params {
|
||||
u32 m;
|
||||
u32 n;
|
||||
s8 m2;
|
||||
s8 m3;
|
||||
s8 m4;
|
||||
s8 m5;
|
||||
s8 m6;
|
||||
};
|
||||
|
||||
struct dpll_regs {
|
||||
u32 cm_clkmode_dpll;
|
||||
u32 cm_idlest_dpll;
|
||||
u32 cm_autoidle_dpll;
|
||||
u32 cm_clksel_dpll;
|
||||
u32 cm_div_m2_dpll;
|
||||
u32 cm_div_m3_dpll;
|
||||
u32 cm_div_m4_dpll;
|
||||
u32 cm_div_m5_dpll;
|
||||
u32 cm_div_m6_dpll;
|
||||
};
|
||||
|
||||
extern const struct dpll_regs dpll_mpu_regs;
|
||||
extern const struct dpll_regs dpll_core_regs;
|
||||
extern const struct dpll_regs dpll_per_regs;
|
||||
extern const struct dpll_regs dpll_ddr_regs;
|
||||
extern const struct dpll_params dpll_mpu;
|
||||
extern const struct dpll_params dpll_core;
|
||||
extern const struct dpll_params dpll_per;
|
||||
extern const struct dpll_params dpll_ddr;
|
||||
|
||||
extern const struct cm_wkuppll *cmwkup;
|
||||
|
||||
void setup_dplls(void);
|
||||
const struct dpll_params *get_dpll_ddr_params(void);
|
||||
void do_setup_dpll(const struct dpll_regs *, const struct dpll_params *);
|
||||
|
||||
#endif
|
||||
|
@ -146,6 +146,8 @@ void set_sdram_timings(const struct emif_regs *regs, int nr);
|
||||
*/
|
||||
void config_ddr_phy(const struct emif_regs *regs, int nr);
|
||||
|
||||
void ddr_pll_config(unsigned int ddrpll_m);
|
||||
|
||||
struct ddr_cmd_regs {
|
||||
unsigned int resv0[7];
|
||||
unsigned int cm0csratio; /* offset 0x01C */
|
||||
|
@ -37,4 +37,5 @@ void omap_nand_switch_ecc(uint32_t, uint32_t);
|
||||
|
||||
void rtc32k_enable(void);
|
||||
void uart_soft_reset(void);
|
||||
u32 wait_on_value(u32, u32, void *, u32);
|
||||
#endif
|
||||
|
@ -66,6 +66,16 @@ static struct emif_regs ddr3_emif_reg_data = {
|
||||
.zq_config = K4B2G1646EBIH9_ZQ_CFG,
|
||||
.emif_ddr_phy_ctlr_1 = K4B2G1646EBIH9_EMIF_READ_LATENCY,
|
||||
};
|
||||
|
||||
#define OSC (V_OSCK/1000000)
|
||||
const struct dpll_params dpll_ddr = {
|
||||
303, OSC-1, 1, -1, -1, -1, -1};
|
||||
|
||||
const struct dpll_params *get_dpll_ddr_params(void)
|
||||
{
|
||||
return &dpll_ddr;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
/*
|
||||
|
@ -44,6 +44,15 @@ static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
|
||||
/* DDR RAM defines */
|
||||
#define DDR_CLK_MHZ 303 /* DDR_DPLL_MULT value */
|
||||
|
||||
#define OSC (V_OSCK/1000000)
|
||||
const struct dpll_params dpll_ddr = {
|
||||
DDR_CLK_MHZ, OSC-1, 1, -1, -1, -1, -1};
|
||||
|
||||
const struct dpll_params *get_dpll_ddr_params(void)
|
||||
{
|
||||
return &dpll_ddr;
|
||||
}
|
||||
|
||||
static const struct ddr_data ddr3_data = {
|
||||
.datardsratio0 = MT41J256M8HX15E_RD_DQS,
|
||||
.datawdsratio0 = MT41J256M8HX15E_WR_DQS,
|
||||
|
@ -242,6 +242,33 @@ int spl_start_uboot(void)
|
||||
}
|
||||
#endif
|
||||
|
||||
#define OSC (V_OSCK/1000000)
|
||||
const struct dpll_params dpll_ddr = {
|
||||
266, OSC-1, 1, -1, -1, -1, -1};
|
||||
const struct dpll_params dpll_ddr_evm_sk = {
|
||||
303, OSC-1, 1, -1, -1, -1, -1};
|
||||
const struct dpll_params dpll_ddr_bone_black = {
|
||||
400, OSC-1, 1, -1, -1, -1, -1};
|
||||
|
||||
const struct dpll_params *get_dpll_ddr_params(void)
|
||||
{
|
||||
struct am335x_baseboard_id header;
|
||||
|
||||
enable_i2c0_pin_mux();
|
||||
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
|
||||
if (read_eeprom(&header) < 0)
|
||||
puts("Could not get board ID.\n");
|
||||
|
||||
if (board_is_evm_sk(&header))
|
||||
return &dpll_ddr_evm_sk;
|
||||
else if (board_is_bone_lt(&header))
|
||||
return &dpll_ddr_bone_black;
|
||||
else if (board_is_evm_15_or_later(&header))
|
||||
return &dpll_ddr_evm_sk;
|
||||
else
|
||||
return &dpll_ddr;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
/*
|
||||
|
Loading…
Reference in New Issue
Block a user