ARM: IGEP0033: Update timing to run DDR at 400MHz.
We can run the DDR at 400MHz, so update the timings for that purpose. Signed-off-by: Enric Balletbo i Serra <eballetbo@iseebcn.com> Reviewed-by: Javier Martinez Canillas <javier@dowhile0.org>
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@ -110,20 +110,20 @@
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#define MT41J512M8RH125_IOCTRL_VALUE 0x18B
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/* Samsung K4B2G1646E-BIH9 */
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#define K4B2G1646EBIH9_EMIF_READ_LATENCY 0x06
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#define K4B2G1646EBIH9_EMIF_TIM1 0x0888A39B
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#define K4B2G1646EBIH9_EMIF_TIM2 0x2A04011A
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#define K4B2G1646EBIH9_EMIF_TIM3 0x501F820F
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#define K4B2G1646EBIH9_EMIF_SDCFG 0x61C24AB2
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#define K4B2G1646EBIH9_EMIF_SDREF 0x0000093B
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#define K4B2G1646EBIH9_EMIF_READ_LATENCY 0x07
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#define K4B2G1646EBIH9_EMIF_TIM1 0x0AAAE51B
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#define K4B2G1646EBIH9_EMIF_TIM2 0x2A1D7FDA
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#define K4B2G1646EBIH9_EMIF_TIM3 0x501F83FF
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#define K4B2G1646EBIH9_EMIF_SDCFG 0x61C052B2
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#define K4B2G1646EBIH9_EMIF_SDREF 0x00000C30
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#define K4B2G1646EBIH9_ZQ_CFG 0x50074BE4
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#define K4B2G1646EBIH9_DLL_LOCK_DIFF 0x1
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#define K4B2G1646EBIH9_RATIO 0x40
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#define K4B2G1646EBIH9_INVERT_CLKOUT 0x1
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#define K4B2G1646EBIH9_RD_DQS 0x3B
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#define K4B2G1646EBIH9_WR_DQS 0x85
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#define K4B2G1646EBIH9_PHY_FIFO_WE 0x100
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#define K4B2G1646EBIH9_PHY_WR_DATA 0xC1
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#define K4B2G1646EBIH9_RATIO 0x80
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#define K4B2G1646EBIH9_INVERT_CLKOUT 0x0
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#define K4B2G1646EBIH9_RD_DQS 0x35
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#define K4B2G1646EBIH9_WR_DQS 0x3A
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#define K4B2G1646EBIH9_PHY_FIFO_WE 0x97
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#define K4B2G1646EBIH9_PHY_WR_DATA 0x76
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#define K4B2G1646EBIH9_IOCTRL_VALUE 0x18B
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/**
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@ -64,7 +64,7 @@ static struct emif_regs ddr3_emif_reg_data = {
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#define OSC (V_OSCK/1000000)
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const struct dpll_params dpll_ddr = {
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303, OSC-1, 1, -1, -1, -1, -1};
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400, OSC-1, 1, -1, -1, -1, -1};
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const struct dpll_params *get_dpll_ddr_params(void)
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{
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@ -83,7 +83,7 @@ void set_mux_conf_regs(void)
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void sdram_init(void)
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{
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config_ddr(303, K4B2G1646EBIH9_IOCTRL_VALUE, &ddr3_data,
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config_ddr(400, K4B2G1646EBIH9_IOCTRL_VALUE, &ddr3_data,
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&ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
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}
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#endif
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