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Coding Style cleanup: replace leading SPACEs by TABs

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Signed-off-by: Wolfgang Denk <wd@denx.de>
[trini: Drop changes for PEP 4 following python tools]
Signed-off-by: Tom Rini <trini@ti.com>
This commit is contained in:
Wolfgang Denk 2013-10-04 17:43:24 +02:00 committed by Tom Rini
parent 3765b3e7bd
commit 93e1459641
116 changed files with 506 additions and 506 deletions
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4
MAKEALL
View File

@ -38,8 +38,8 @@ usage()
BUILD_NCPUS number of parallel make jobs (default: auto)
CROSS_COMPILE cross-compiler toolchain prefix (default: "")
CROSS_COMPILE_<ARCH> cross-compiler toolchain prefix for
architecture "ARCH". Substitute "ARCH" for any
supported architecture (default: "")
architecture "ARCH". Substitute "ARCH" for any
supported architecture (default: "")
MAKEALL_LOGDIR output all logs to here (default: ./LOG/)
BUILD_DIR output build directory (default: ./)
BUILD_NBUILDS number of parallel targets (default: 1)

20
README
View File

@ -944,10 +944,10 @@ The following options need to be configured:
- Regular expression support:
CONFIG_REGEX
If this variable is defined, U-Boot is linked against
the SLRE (Super Light Regular Expression) library,
which adds regex support to some commands, as for
example "env grep" and "setexpr".
If this variable is defined, U-Boot is linked against
the SLRE (Super Light Regular Expression) library,
which adds regex support to some commands, as for
example "env grep" and "setexpr".
- Device tree:
CONFIG_OF_CONTROL
@ -1096,8 +1096,8 @@ The following options need to be configured:
devices.
CONFIG_SYS_SCSI_SYM53C8XX_CCF to fix clock timing (80Mhz)
The environment variable 'scsidevs' is set to the number of
SCSI devices found during the last scan.
The environment variable 'scsidevs' is set to the number of
SCSI devices found during the last scan.
- NETWORK Support (PCI):
CONFIG_E1000
@ -1987,7 +1987,7 @@ CBFS (Coreboot Filesystem) support
offset CONFIG_SYS_FSL_I2C_SPEED for the i2c speed and
CONFIG_SYS_FSL_I2C_SLAVE for the slave addr of the first
bus.
- If your board supports a second fsl i2c bus, define
- If your board supports a second fsl i2c bus, define
CONFIG_SYS_FSL_I2C2_OFFSET for the register offset
CONFIG_SYS_FSL_I2C2_SPEED for the speed and
CONFIG_SYS_FSL_I2C2_SLAVE for the slave address of the
@ -3191,9 +3191,9 @@ FIT uImage format:
CONFIG_TPL_PAD_TO
Image offset to which the TPL should be padded before appending
the TPL payload. By default, this is defined as
CONFIG_SPL_MAX_SIZE, or 0 if CONFIG_SPL_MAX_SIZE is undefined.
CONFIG_SPL_PAD_TO must be either 0, meaning to append the SPL
payload without any padding, or >= CONFIG_SPL_MAX_SIZE.
CONFIG_SPL_MAX_SIZE, or 0 if CONFIG_SPL_MAX_SIZE is undefined.
CONFIG_SPL_PAD_TO must be either 0, meaning to append the SPL
payload without any padding, or >= CONFIG_SPL_MAX_SIZE.
Modem Support:
--------------

2
arch/arm/config.mk
View File

@ -17,7 +17,7 @@ endif
LDFLAGS_FINAL += --gc-sections
PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections \
-fno-common -ffixed-r9 -msoft-float
-fno-common -ffixed-r9 -msoft-float
# Support generic board on ARM
__HAVE_ARCH_GENERIC_BOARD := y

44
arch/arm/cpu/armv7/mx5/lowlevel_init.S
View File

@ -31,10 +31,10 @@
/* reconfigure L2 cache aux control reg */
ldr r0, =0xC0 | /* tag RAM */ \
0x4 | /* data RAM */ \
1 << 24 | /* disable write allocate delay */ \
1 << 23 | /* disable write allocate combine */ \
1 << 22 /* disable write allocate */
0x4 | /* data RAM */ \
1 << 24 | /* disable write allocate delay */ \
1 << 23 | /* disable write allocate combine */ \
1 << 22 /* disable write allocate */
#if defined(CONFIG_MX51)
ldr r3, [r4, #ROM_SI_REV]
@ -290,20 +290,20 @@ setup_pll_func:
setup_pll PLL1_BASE_ADDR, 800
setup_pll PLL3_BASE_ADDR, 400
setup_pll PLL3_BASE_ADDR, 400
/* Switch peripheral to PLL3 */
ldr r0, =CCM_BASE_ADDR
ldr r1, =0x00015154
str r1, [r0, #CLKCTL_CBCMR]
ldr r1, =0x02898945
str r1, [r0, #CLKCTL_CBCDR]
/* make sure change is effective */
/* Switch peripheral to PLL3 */
ldr r0, =CCM_BASE_ADDR
ldr r1, =0x00015154
str r1, [r0, #CLKCTL_CBCMR]
ldr r1, =0x02898945
str r1, [r0, #CLKCTL_CBCDR]
/* make sure change is effective */
1: ldr r1, [r0, #CLKCTL_CDHIPR]
cmp r1, #0x0
bne 1b
cmp r1, #0x0
bne 1b
setup_pll PLL2_BASE_ADDR, 400
setup_pll PLL2_BASE_ADDR, 400
/* Switch peripheral to PLL2 */
ldr r0, =CCM_BASE_ADDR
@ -324,7 +324,7 @@ setup_pll_func:
cmp r1, #0x0
bne 1b
setup_pll PLL3_BASE_ADDR, 216
setup_pll PLL3_BASE_ADDR, 216
setup_pll PLL4_BASE_ADDR, 455
@ -358,13 +358,13 @@ setup_pll_func:
str r1, [r0, #CLKCTL_CCGR6]
str r1, [r0, #CLKCTL_CCGR7]
mov r1, #0x00000
str r1, [r0, #CLKCTL_CCDR]
mov r1, #0x00000
str r1, [r0, #CLKCTL_CCDR]
/* for cko - for ARM div by 8 */
mov r1, #0x000A0000
add r1, r1, #0x00000F0
str r1, [r0, #CLKCTL_CCOSR]
/* for cko - for ARM div by 8 */
mov r1, #0x000A0000
add r1, r1, #0x00000F0
str r1, [r0, #CLKCTL_CCOSR]
#endif /* CONFIG_MX53 */
.endm

2
arch/arm/dts/exynos5250.dtsi
View File

@ -140,7 +140,7 @@
reg = <0x12d40000 0x30>;
clock-frequency = <50000000>;
interrupts = <0 70 0>;
};
};
spi@131a0000 {
#address-cells = <1>;

4
arch/arm/lib/relocate.S
View File

@ -66,9 +66,9 @@ relocate_done:
/* ARMv4- don't know bx lr but the assembler fails to see that */
#ifdef __ARM_ARCH_4__
mov pc, lr
mov pc, lr
#else
bx lr
bx lr
#endif
ENDPROC(relocate_code)

2
arch/blackfin/cpu/traps.c
View File

@ -261,7 +261,7 @@ static void decode_address(char *buf, unsigned long address)
if (!address)
sprintf(buf, "<0x%p> /* Maybe null pointer? */", paddr);
else if (address >= CONFIG_SYS_MONITOR_BASE &&
address < CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
address < CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
sprintf(buf, "<0x%p> /* somewhere in u-boot */", paddr);
else
sprintf(buf, "<0x%p> /* unknown address */", paddr);

2
arch/blackfin/include/asm/mach-common/bits/lockbox.h
View File

@ -16,7 +16,7 @@ typedef struct SESR_args {
unsigned long ulMessageSize; /* message length in bytes */
unsigned long ulSFEntryPoint; /* entry point of secure function */
unsigned long ulMessagePtr; /* pointer to the buffer containing
the digital signature and message */
the digital signature and message */
unsigned long ulReserved1; /* reserved */
unsigned long ulReserved2; /* reserved */
} tSESR_args;

2
arch/m68k/lib/traps.c
View File

@ -20,7 +20,7 @@ extern void _int_handler(void);
static void show_frame(struct pt_regs *fp)
{
printf ("Vector Number: %d Format: %02x Fault Status: %01x\n\n", (fp->vector & 0x3fc) >> 2,
fp->format, (fp->vector & 0x3) | ((fp->vector & 0xc00) >> 8));
fp->format, (fp->vector & 0x3) | ((fp->vector & 0xc00) >> 8));
printf ("PC: %08lx SR: %08lx SP: %08lx\n", fp->pc, (long) fp->sr, (long) fp);
printf ("D0: %08lx D1: %08lx D2: %08lx D3: %08lx\n",
fp->d0, fp->d1, fp->d2, fp->d3);

2
arch/nios2/cpu/epcs.c
View File

@ -475,7 +475,7 @@ void do_epcs_info (struct epcs_devinfo_t *dev, int argc, char * const argv[])
printf ("status: 0x%02x (WIP:%d, WEL:%d, PROT:%s)\n",
stat,
(stat & EPCS_STATUS_WIP) ? 1 : 0,
(stat & EPCS_STATUS_WEL) ? 1 : 0,
(stat & EPCS_STATUS_WEL) ? 1 : 0,
(stat & dev->prot_mask) ? "on" : "off" );
/* Configuration */

2
arch/nios2/lib/libgcc.c
View File

@ -548,7 +548,7 @@ __mulsi3 (SItype a, SItype b)
while (cnt)
{
if (cnt & 1)
{
{
res += b;
}
b <<= 1;

4
arch/openrisc/cpu/cpu.c
View File

@ -138,8 +138,8 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
/* Code the jump to __reset here as the compiler is prone to
emitting a bad jump instruction if the function is in flash */
__asm__("l.movhi r1,hi(__reset); \
l.ori r1,r1,lo(__reset); \
l.jr r1");
l.ori r1,r1,lo(__reset); \
l.jr r1");
/* not reached, __reset does not return */
return 0;
}

10
arch/powerpc/cpu/mpc83xx/cpu_init.c
View File

@ -425,15 +425,15 @@ static int print_83xx_arb_event(int force)
};
int etype = (gd->arch.arbiter_event_attributes & AEATR_EVENT)
>> AEATR_EVENT_SHIFT;
>> AEATR_EVENT_SHIFT;
int mstr_id = (gd->arch.arbiter_event_attributes & AEATR_MSTR_ID)
>> AEATR_MSTR_ID_SHIFT;
>> AEATR_MSTR_ID_SHIFT;
int tbst = (gd->arch.arbiter_event_attributes & AEATR_TBST)
>> AEATR_TBST_SHIFT;
>> AEATR_TBST_SHIFT;
int tsize = (gd->arch.arbiter_event_attributes & AEATR_TSIZE)
>> AEATR_TSIZE_SHIFT;
>> AEATR_TSIZE_SHIFT;
int ttype = (gd->arch.arbiter_event_attributes & AEATR_TTYPE)
>> AEATR_TTYPE_SHIFT;
>> AEATR_TTYPE_SHIFT;
if (!force && !gd->arch.arbiter_event_address)
return 0;

4
arch/powerpc/cpu/mpc83xx/pci.c
View File

@ -67,7 +67,7 @@ static void pci_init_bus(int bus, struct pci_region *reg)
pci_ctrl->pibar1 = 0;
pci_ctrl->piebar1 = 0;
pci_ctrl->piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP |
PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size - 1));
PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size - 1));
i = hose->region_count++;
hose->regions[i].bus_start = 0;
@ -79,7 +79,7 @@ static void pci_init_bus(int bus, struct pci_region *reg)
hose->last_busno = 0xff;
pci_setup_indirect(hose, CONFIG_SYS_IMMR + 0x8300 + bus * 0x80,
CONFIG_SYS_IMMR + 0x8304 + bus * 0x80);
CONFIG_SYS_IMMR + 0x8304 + bus * 0x80);
pci_register_hose(hose);

4
arch/powerpc/cpu/ppc4xx/4xx_pci.c
View File

@ -143,14 +143,14 @@ void pci_405gp_init(struct pci_controller *hose)
ptmla_str = getenv("ptm1la");
ptmms_str = getenv("ptm1ms");
if(NULL != ptmla_str && NULL != ptmms_str ) {
ptmla[0] = simple_strtoul (ptmla_str, NULL, 16);
ptmla[0] = simple_strtoul (ptmla_str, NULL, 16);
ptmms[0] = simple_strtoul (ptmms_str, NULL, 16);
}
ptmla_str = getenv("ptm2la");
ptmms_str = getenv("ptm2ms");
if(NULL != ptmla_str && NULL != ptmms_str ) {
ptmla[1] = simple_strtoul (ptmla_str, NULL, 16);
ptmla[1] = simple_strtoul (ptmla_str, NULL, 16);
ptmms[1] = simple_strtoul (ptmms_str, NULL, 16);
}
#endif

2
board/Barix/ipam390/README.ipam390
View File

@ -50,7 +50,7 @@ TFTP from server 192.168.1.1; our IP address is 192.168.20.71
Filename '/tftpboot/ipam390/u-boot.ais'.
Load address: 0xc0000000
Loading: ##################################
1.5 MiB/s
1.5 MiB/s
done
Bytes transferred = 493716 (78894 hex)

4
board/altera/common/sevenseg.c
View File

@ -87,10 +87,10 @@ static inline void __sevenseg_set (unsigned int value)
#if (SEVENSEG_ACTIVE == 0)
sevenseg_portval = (sevenseg_portval & SEVENDEG_MASK_DP)
| ((~value) & (~SEVENDEG_MASK_DP));
| ((~value) & (~SEVENDEG_MASK_DP));
#else
sevenseg_portval = (sevenseg_portval & SEVENDEG_MASK_DP)
| (value);
| (value);
#endif
piop->data = sevenseg_portval;

52
board/boundary/nitrogen6x/6x_upgrade.txt
View File

@ -6,39 +6,39 @@ if ${fs}load ${dtype} ${disk}:1 12000000 u-boot.imx || ${fs}load ${dtype} ${disk
if sf probe || sf probe || \
sf probe 1 27000000 || sf probe 1 27000000 ; then
echo "probed SPI ROM" ;
if sf read 0x12400000 $offset $filesize ; then
if cmp.b 0x12000000 0x12400000 $filesize ; then
echo "------- U-Boot versions match" ;
else
echo "Need U-Boot upgrade" ;
echo "Program in 5 seconds" ;
for n in 5 4 3 2 1 ; do
echo $n ;
sleep 1 ;
done
if sf read 0x12400000 $offset $filesize ; then
if cmp.b 0x12000000 0x12400000 $filesize ; then
echo "------- U-Boot versions match" ;
else
echo "Need U-Boot upgrade" ;
echo "Program in 5 seconds" ;
for n in 5 4 3 2 1 ; do
echo $n ;
sleep 1 ;
done
echo "erasing" ;
sf erase 0 0x50000 ;
sf erase 0 0x50000 ;
# two steps to prevent bricking
echo "programming" ;
sf write 0x12000000 $offset $filesize ;
sf write 0x12000000 $offset $filesize ;
echo "verifying" ;
if sf read 0x12400000 $offset $filesize ; then
if cmp.b 0x12000000 0x12400000 $filesize ; then
while echo "---- U-Boot upgraded. reset" ; do
if sf read 0x12400000 $offset $filesize ; then
if cmp.b 0x12000000 0x12400000 $filesize ; then
while echo "---- U-Boot upgraded. reset" ; do
sleep 120
done
else
echo "Read verification error" ;
fi
else
echo "Error re-reading EEPROM" ;
fi
fi
else
echo "Error reading boot loader from EEPROM" ;
fi
else
echo "Read verification error" ;
fi
else
echo "Error re-reading EEPROM" ;
fi
fi
else
echo "Error reading boot loader from EEPROM" ;
fi
else
echo "Error initializing EEPROM" ;
echo "Error initializing EEPROM" ;
fi ;
else
echo "No U-Boot image found on SD card" ;

10
board/chromebook-x86/dts/alex.dts
View File

@ -3,8 +3,8 @@
/include/ "coreboot.dtsi"
/ {
#address-cells = <1>;
#size-cells = <1>;
#address-cells = <1>;
#size-cells = <1>;
model = "Google Alex";
compatible = "google,alex", "intel,atom-pineview";
@ -12,13 +12,13 @@
silent_console = <0>;
};
gpio: gpio {};
gpio: gpio {};
serial {
reg = <0x3f8 8>;
clock-frequency = <115200>;
};
chosen { };
memory { device_type = "memory"; reg = <0 0>; };
chosen { };
memory { device_type = "memory"; reg = <0 0>; };
};

10
board/chromebook-x86/dts/link.dts
View File

@ -3,8 +3,8 @@
/include/ "coreboot.dtsi"
/ {
#address-cells = <1>;
#size-cells = <1>;
#address-cells = <1>;
#size-cells = <1>;
model = "Google Link";
compatible = "google,link", "intel,celeron-ivybridge";
@ -12,15 +12,15 @@
silent_console = <0>;
};
gpio: gpio {};
gpio: gpio {};
serial {
reg = <0x3f8 8>;
clock-frequency = <115200>;
};
chosen { };
memory { device_type = "memory"; reg = <0 0>; };
chosen { };
memory { device_type = "memory"; reg = <0 0>; };
spi {
#address-cells = <1>;

4
board/cobra5272/bdm/cobra5272_uboot.gdb
View File

@ -1,11 +1,11 @@
#
# GDB Init script for the Coldfire 5272 processor.
#
# The main purpose of this script is to configure the
# The main purpose of this script is to configure the
# DRAM controller so code can be loaded.
#
# This file was changed to suite the senTec COBRA5272 board.
#
#
define addresses

2
board/cogent/flash.c
View File

@ -487,7 +487,7 @@ flash_erase(flash_info_t *info, int s_first, int s_last)
if (haderr > 0) {
printf (" failed\n");
rcode = 1;
rcode = 1;
}
else
printf (" done\n");

6
board/cray/L1/bootscript.hush
View File

@ -47,7 +47,7 @@ else
echo no kernel to boot from $flash_krl, need tftp
fi
# Have a rootfs in flash?
# Have a rootfs in flash?
echo test for SQUASHfs at $flash_rfs
if imi $flash_rfs
@ -69,7 +69,7 @@ fi
# TFTP down a kernel
if printenv bootfile
then
then
tftp $tftp_addr $bootfile
setenv kernel $tftp_addr
echo I will boot the TFTP kernel
@ -90,7 +90,7 @@ if printenv rootpath
then
echo rootpath is $rootpath
if printenv initrd
then
then
echo initrd is also specified, so use $initrd
tftp $tftp2_addr $initrd
setenv bootargs root=/dev/ram0 rw cwsroot=$serverip:$rootpath $bootargs

2
board/esd/common/lcd.h
View File

@ -9,7 +9,7 @@
* Neutralize little endians.
*/
#define SWAP_LONG(data) ((unsigned long) \
(((unsigned long)(data) >> 24) | \
(((unsigned long)(data) >> 24) | \
((unsigned long)(data) << 24) | \
(((unsigned long)(data) >> 8) & 0x0000ff00 ) | \
(((unsigned long)(data) << 8) & 0x00ff0000 )))

2
board/esd/cpci750/ide.c
View File

@ -43,7 +43,7 @@ int ide_preinit (void)
if (devbusfn != -1) {
cpci_hd_type = 1;
} else {
devbusfn = pci_find_device (0x1095, 0x3114, 0);
devbusfn = pci_find_device (0x1095, 0x3114, 0);
if (devbusfn != -1) {
cpci_hd_type = 2;
}

2
board/esd/cpci750/pci.c
View File

@ -746,7 +746,7 @@ static int gt_read_config_dword (struct pci_controller *hose,
int bus = PCI_BUS (dev);
if ((bus == local_buses[0]) || (bus == local_buses[1])) {
*value = pciReadConfigReg ((PCI_HOST) hose->cfg_addr,
*value = pciReadConfigReg ((PCI_HOST) hose->cfg_addr,
offset | (PCI_FUNC(dev) << 8),
PCI_DEV (dev));
} else {

12
board/etin/debris/flash.c
View File

@ -323,7 +323,7 @@ int flash_erase (flash_info_t *flash, int s_first, int s_last)
if (prot)
printf ("- Warning: %d protected sectors will not be erased!\n",
prot);
prot);
else
printf ("\n");
@ -365,7 +365,7 @@ static const struct jedec_flash_info jedec_table[] = {
DevSize: SIZE_1MiB,
NumEraseRegions: 4,
regions: {ERASEINFO(0x10000,15),
ERASEINFO(0x08000,1),
ERASEINFO(0x08000,1),
ERASEINFO(0x02000,2),
ERASEINFO(0x04000,1)
}
@ -376,7 +376,7 @@ static const struct jedec_flash_info jedec_table[] = {
DevSize: SIZE_2MiB,
NumEraseRegions: 4,
regions: {ERASEINFO(0x10000,31),
ERASEINFO(0x08000,1),
ERASEINFO(0x08000,1),
ERASEINFO(0x02000,2),
ERASEINFO(0x04000,1)
}
@ -387,7 +387,7 @@ static const struct jedec_flash_info jedec_table[] = {
DevSize: SIZE_2MiB,
NumEraseRegions: 4,
regions: {ERASEINFO(0x04000,1),
ERASEINFO(0x02000,2),
ERASEINFO(0x02000,2),
ERASEINFO(0x08000,1),
ERASEINFO(0x10000,31)
}
@ -398,7 +398,7 @@ static const struct jedec_flash_info jedec_table[] = {
DevSize: SIZE_4MiB,
NumEraseRegions: 2,
regions: {ERASEINFO(0x10000,63),
ERASEINFO(0x02000,8)
ERASEINFO(0x02000,8)
}
}, {
@ -408,7 +408,7 @@ static const struct jedec_flash_info jedec_table[] = {
DevSize: SIZE_4MiB,
NumEraseRegions: 2,
regions: {ERASEINFO(0x02000,8),
ERASEINFO(0x10000,63)
ERASEINFO(0x10000,63)
}
}
};

14
board/evb64260/flash.c
View File

@ -60,7 +60,7 @@ flash_init (void)
#define CONFIG_SYS_BOOT_FLASH_WIDTH 1
#endif
size_b0 = flash_get_size(CONFIG_SYS_BOOT_FLASH_WIDTH, (vu_long *)base,
&flash_info[0]);
&flash_info[0]);
#ifndef CONFIG_P3G4
printf("[");
@ -97,17 +97,17 @@ flash_init (void)
#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
/* monitor protection ON by default */
flash_protect(FLAG_PROTECT_SET,
CONFIG_SYS_MONITOR_BASE,
CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
flash_get_info(CONFIG_SYS_MONITOR_BASE));
CONFIG_SYS_MONITOR_BASE,
CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
flash_get_info(CONFIG_SYS_MONITOR_BASE));
#endif
#ifdef CONFIG_ENV_IS_IN_FLASH
/* ENV protection ON by default */
flash_protect(FLAG_PROTECT_SET,
CONFIG_ENV_ADDR,
CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1,
flash_get_info(CONFIG_ENV_ADDR));
CONFIG_ENV_ADDR,
CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1,
flash_get_info(CONFIG_ENV_ADDR));
#endif
flash_size = size_b0 + size_b1;

4
board/evb64260/mpsc.c
View File

@ -785,7 +785,7 @@ galmpsc_shutdown(int mpsc)
GT_REG_WRITE(GALSDMA_0_COM_REG + CHANNEL * GALSDMA_REG_DIFF, 0);
GT_REG_WRITE(GALSDMA_0_COM_REG + CHANNEL * GALSDMA_REG_DIFF,
SDMA_TX_ABORT | SDMA_RX_ABORT);
SDMA_TX_ABORT | SDMA_RX_ABORT);
/* shut down the MPSC */
GT_REG_WRITE(GALMPSC_MCONF_LOW, 0);
@ -797,7 +797,7 @@ galmpsc_shutdown(int mpsc)
/* shut down the sdma engines. */
/* reset config to default */
GT_REG_WRITE(GALSDMA_0_CONF_REG + CHANNEL * GALSDMA_REG_DIFF,
0x000000fc);
0x000000fc);
udelay(100);

4
board/fads/fads.c
View File

@ -434,7 +434,7 @@ static int _initsdram(uint base, uint noMbytes)
*/
memctl->memc_mcr = 0x80808111; /* run umpb cs4 1 count 1, addr 0x11 ??? (50MHz) */
/* run umpb cs4 1 count 1, addr 0x11 precharge+MRS (100MHz) */
/* run umpb cs4 1 count 1, addr 0x11 precharge+MRS (100MHz) */
udelay(200);
/* Run 8 refresh cycles */
@ -567,7 +567,7 @@ static int initsdram(uint base, uint *noMbytes)
if(!_initsdram(base, m))
{
*noMbytes += m;
*noMbytes += m;
return 0;
}
else

2
board/freescale/b4860qds/tlb.c
View File

@ -68,7 +68,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
0, 3, BOOKE_PAGESZ_256M, 1),
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x10000000,
CONFIG_SYS_PCIE1_MEM_PHYS + 0x10000000,
CONFIG_SYS_PCIE1_MEM_PHYS + 0x10000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 4, BOOKE_PAGESZ_256M, 1),

10
board/freescale/bsc9132qds/README
View File

@ -23,14 +23,14 @@ Overview
ECC), up to 1333 MHz data rate
- Dedicated security engine featuring trusted boot
- Two DMA controllers
- OCNDMA with four bidirectional channels
- SysDMA with sixteen bidirectional channels
- OCNDMA with four bidirectional channels
- SysDMA with sixteen bidirectional channels
- Interfaces
- Four-lane SerDes PHY
- Four-lane SerDes PHY
- PCI Express controller complies with the PEX Specification-Rev 2.0
- Two Common Public Radio Interface (CPRI) controller lanes
- Two Common Public Radio Interface (CPRI) controller lanes
- High-speed USB 2.0 host and device controller with ULPI interface
- Enhanced secure digital (SD/MMC) host controller (eSDHC)
- Enhanced secure digital (SD/MMC) host controller (eSDHC)
- Antenna interface controller (AIC), supporting four industry
standard JESD207/four custom ADI RF interfaces
- ADI lanes support both full duplex FDD support & half duplex TDD

4
board/freescale/mpc8313erdb/mpc8313erdb.c
View File

@ -129,12 +129,12 @@ void board_init_f(ulong bootflag)
{
board_early_init_f();
NS16550_init((NS16550_t)(CONFIG_SYS_IMMR + 0x4500),
CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
puts("NAND boot... ");
init_timebase();
initdram(0);
relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, (gd_t *)gd,
CONFIG_SYS_NAND_U_BOOT_RELOC);
CONFIG_SYS_NAND_U_BOOT_RELOC);
}
void board_init_r(gd_t *gd, ulong dest_addr)

4
board/freescale/mpc8360emds/mpc8360emds.c
View File

@ -427,7 +427,7 @@ void ft_board_setup(void *blob, bd_t *bd)
if (prop) {
path = fdt_path_offset(blob, prop);
prop = fdt_getprop(blob, path,
"phy-connection-type", 0);
"phy-connection-type", 0);
if (prop && (strcmp(prop, "rgmii-id") == 0))
fdt_fixup_phy_connection(blob, path,
PHY_INTERFACE_MODE_RGMII_RXID);
@ -439,7 +439,7 @@ void ft_board_setup(void *blob, bd_t *bd)
if (prop) {
path = fdt_path_offset(blob, prop);
prop = fdt_getprop(blob, path,
"phy-connection-type", 0);
"phy-connection-type", 0);
if (prop && (strcmp(prop, "rgmii-id") == 0))
fdt_fixup_phy_connection(blob, path,
PHY_INTERFACE_MODE_RGMII_RXID);

6
board/funkwerk/vovpn-gw/vovpn-gw.c
View File

@ -270,9 +270,9 @@ int misc_init_r (void)
for (i = 0; i < 64; i++) {
c = *dummy;
printf( "UPMA[%02d]: 0x%08lx,0x%08lx: 0x%08lx\n",i,
memctl->memc_mamr,
memctl->memc_mar,
memctl->memc_mdr );
memctl->memc_mamr,
memctl->memc_mar,
memctl->memc_mdr );
}
memctl->memc_mamr = 0x00044440;
#endif

2
board/gen860t/flash.c
View File

@ -182,7 +182,7 @@ flash_get_offsets (ulong base, flash_info_t *info)
default:
printf ("Don't know sector offsets for FLASH"
" type 0x%lx\n", info->flash_id);
" type 0x%lx\n", info->flash_id);
return;
}
}

4
board/incaip/incaip.c
View File

@ -58,9 +58,9 @@ phys_size_t initdram(int board_type)
for (rows = 0xB; rows <= 0xD; rows++)
{
*INCA_IP_SDRAM_MC_CFGPB0 = (0x14 << 8) |
(rows << 4) | cols;
(rows << 4) | cols;
size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
max_sdram_size());
max_sdram_size());
if (size > max_size)
{

2
board/matrix_vision/mvbc_p/Makefile
View File

@ -19,7 +19,7 @@ OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
$(call cmd_link_o_target, $(OBJS))
$(call cmd_link_o_target, $(OBJS))
#########################################################################

2
board/matrix_vision/mvsmr/Makefile
View File

@ -19,7 +19,7 @@ OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
$(call cmd_link_o_target, $(OBJS))
$(call cmd_link_o_target, $(OBJS))
@mkimage -T script -C none -n mvSMR_Script -d bootscript $(obj)bootscript.img
#########################################################################

122
board/openrisc/openrisc-generic/or1ksim.cfg
View File

@ -20,8 +20,8 @@ the simulator.
not found too, it reverts to the built-in default configuration.
NOTE: Users should not rely on the built-in configuration, since the
default configuration may differ between version.
Rather create a configuration file that sets all critical values.
default configuration may differ between version.
Rather create a configuration file that sets all critical values.
This file may contain (standard C) comments only - no // support.
@ -306,7 +306,7 @@ end
debug = 0-9
0 : no debug messages
1-9: debug message level.
higher numbers produce more messages
higher numbers produce more messages
profile = 0/1
'0': don't generate profiling file 'sim.profile'
@ -375,11 +375,11 @@ end
Core Verification.
enabled = 0/1
'0': disbable VAPI server
'1': enable/start VAPI server
'0': disbable VAPI server
'1': enable/start VAPI server
server_port = <value>
TCP/IP port to start VAPI server on
TCP/IP port to start VAPI server on
log_enabled = 0/1
'0': disable VAPI requests logging
@ -565,56 +565,56 @@ end
This section configures the UARTs
enabled = <0|1>
Enable/disable the peripheral. By default if it is enabled.
Enable/disable the peripheral. By default if it is enabled.
baseaddr = <hex_value>
address of first UART register for this device
address of first UART register for this device
channel = <channeltype>:<args>
The channel parameter indicates the source of received UART characters
and the sink for transmitted UART characters.
The channel parameter indicates the source of received UART characters
and the sink for transmitted UART characters.
The <channeltype> can be either "file", "xterm", "tcp", "fd", or "tty"
(without quotes).
The <channeltype> can be either "file", "xterm", "tcp", "fd", or "tty"
(without quotes).
A) To send/receive characters from a pair of files, use a file
channel:
A) To send/receive characters from a pair of files, use a file
channel:
channel=file:<rxfile>,<txfile>
channel=file:<rxfile>,<txfile>
B) To create an interactive terminal window, use an xterm channel:
channel=xterm:[<xterm_arg>]*
channel=xterm:[<xterm_arg>]*
C) To create a bidirectional tcp socket which one could, for example,
access via telnet, use a tcp channel:
access via telnet, use a tcp channel:
channel=tcp:<port number>
channel=tcp:<port number>
D) To cause the UART to read/write from existing numeric file
descriptors, use an fd channel:
descriptors, use an fd channel:
channel=fd:<rx file descriptor num>,<tx file descriptor num>
channel=fd:<rx file descriptor num>,<tx file descriptor num>
E) To connect the UART to a physical serial port, create a tty
channel:
E) To connect the UART to a physical serial port, create a tty
channel:
channel=tty:device=/dev/ttyS0,baud=9600
irq = <value>
irq number for this device
irq number for this device
16550 = 0/1
'0': this device is a UART16450
'1': this device is a UART16550
'0': this device is a UART16450
'1': this device is a UART16550
jitter = <value>
in msecs... time to block, -1 to disable it
in msecs... time to block, -1 to disable it
vapi_id = <hex_value>
VAPI id of this instance
VAPI id of this instance
*/
section uart
@ -634,16 +634,16 @@ end
This section configures the DMAs
enabled = <0|1>
Enable/disable the peripheral. By default if it is enabled.
Enable/disable the peripheral. By default if it is enabled.
baseaddr = <hex_value>
address of first DMA register for this device
address of first DMA register for this device
irq = <value>
irq number for this device
irq number for this device
vapi_id = <hex_value>
VAPI id of this instance
VAPI id of this instance
*/
section dma
@ -658,37 +658,37 @@ end
This section configures the ETHERNETs
enabled = <0|1>
Enable/disable the peripheral. By default if it is enabled.
Enable/disable the peripheral. By default if it is enabled.
baseaddr = <hex_value>
address of first ethernet register for this device
address of first ethernet register for this device
dma = <value>
which controller is this ethernet "connected" to
which controller is this ethernet "connected" to
irq = <value>
ethernet mac IRQ level
ethernet mac IRQ level
rtx_type = <value>
use 0 - file interface, 1 - socket interface
use 0 - file interface, 1 - socket interface
rx_channel = <value>
DMA channel used for RX
DMA channel used for RX
tx_channel = <value>
DMA channel used for TX
DMA channel used for TX
rxfile = "<filename>"
filename, where to read data from
filename, where to read data from
txfile = "<filename>"
filename, where to write data to
filename, where to write data to
sockif = "<ifacename>"
interface name of ethernet socket
interface name of ethernet socket
vapi_id = <hex_value>
VAPI id of this instance
VAPI id of this instance
*/
section ethernet
@ -711,16 +711,16 @@ end
This section configures the GPIOs
enabled = <0|1>
Enable/disable the peripheral. By default if it is enabled.
Enable/disable the peripheral. By default if it is enabled.
baseaddr = <hex_value>
address of first GPIO register for this device
address of first GPIO register for this device
irq = <value>
irq number for this device
irq number for this device
base_vapi_id = <hex_value>
first VAPI id of this instance
first VAPI id of this instance
GPIO uses 8 consecutive VAPI IDs
*/
@ -736,19 +736,19 @@ end
This section configures the VGA/LCD controller
enabled = <0|1>
Enable/disable the peripheral. By default if it is enabled.
Enable/disable the peripheral. By default if it is enabled.
baseaddr = <hex_value>
address of first VGA register
address of first VGA register
irq = <value>
irq number for this device
irq number for this device
refresh_rate = <value>
number of cycles between screen dumps
number of cycles between screen dumps
filename = "<filename>"
template name for generated names (e.g. "primary" produces "primary0023.bmp")
template name for generated names (e.g. "primary" produces "primary0023.bmp")
*/
section vga
@ -825,39 +825,39 @@ end
This section configures the ATA/ATAPI host controller
baseaddr = <hex_value>
address of first ATA register
address of first ATA register
enabled = <0|1>
Enable/disable the peripheral. By default if it is enabled.
Enable/disable the peripheral. By default if it is enabled.
irq = <value>
irq number for this device
irq number for this device
debug = <value>
debug level for ata models.
debug level for ata models.
0: no debug messages
1: verbose messages
3: normal messages (more messages than verbose)
5: debug messages (normal debug messages)
5: debug messages (normal debug messages)
7: flow control messages (debug statemachine flows)
9: low priority message (display everything the code does)
dev_type0/1 = <value>
ata device 0 type
0: NO_CONNeCT: none (not connected)
ata device 0 type
0: NO_CONNeCT: none (not connected)
1: FILE : simulated harddisk
2: LOCAL : local system harddisk
dev_file0/1 = "<filename>"
filename for simulated ATA device
filename for simulated ATA device
valid only if dev_type0 == 1
dev_size0/1 = <value>
size of simulated hard-disk (in MBytes)
size of simulated hard-disk (in MBytes)
valid only if dev_type0 == 1
dev_packet0/1 = <value>
0: simulated ATA device does NOT implement PACKET command feature set
0: simulated ATA device does NOT implement PACKET command feature set
1: simulated ATA device does implement PACKET command feature set
FIXME: irq number

2
board/ppmc8260/strataflash.c
View File

@ -407,7 +407,7 @@ static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout
printf("Command Sequence Error.\n");
} else if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS)){
printf("Block Erase Error.\n");
retcode = ERR_NOT_ERASED;
retcode = ERR_NOT_ERASED;
} else if (flash_isset(info, sector, 0, FLASH_STATUS_PSLBS)) {
printf("Locking Error\n");
}

6
board/pxa255_idp/pxa_reg_calcs.py
View File

@ -21,7 +21,7 @@ class gpio:
self.clr = clr
self.alt = alt
self.desc = desc
# the following is a dictionary of all GPIOs in the system
# the key is the GPIO number
@ -280,8 +280,8 @@ for reg in registers:
# print define to past right into U-Boot source code
print
print
print
print
for reg in registers:
print '#define %s 0x%x' % (uboot_reg_names[reg], pxa_regs[reg])

2
board/rbc823/rbc823.c
View File

@ -78,7 +78,7 @@ const uint static_table[] =
0x0FFFFC04, 0x0FF3FC04, 0x0FF3CC04, 0x0FF3CC04,
0x0FF3EC04, 0x0FF3CC00, 0x0FF7FC04, 0x3FFFFC04,
0xFFFFFC04, 0xFFFFFC05, /* last */
_NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,

6
board/samsung/dts/exynos5250-snow.dts
View File

@ -71,9 +71,9 @@
codec-enable-gpio = <&gpio 0xb7 0>;
};
sound@12d60000 {
status = "disabled";
};
sound@12d60000 {
status = "disabled";
};
i2c@12cd0000 {
soundcodec@22 {

2
board/svm_sc8xx/svm_sc8xx.c
View File

@ -139,6 +139,6 @@ phys_size_t initdram (int board_type)
#if defined(CONFIG_CMD_DOC)
void doc_init (void)
{
doc_probe (CONFIG_SYS_DOC_BASE);
doc_probe (CONFIG_SYS_DOC_BASE);
}
#endif

2
boards.cfg
View File

@ -196,7 +196,7 @@ Active arm arm926ejs mb86r0x syteco jadecpu
Active arm arm926ejs mx25 freescale mx25pdk mx25pdk mx25pdk:IMX_CONFIG=board/freescale/mx25pdk/imximage.cfg Fabio Estevam <fabio.estevam@freescale.com>
Active arm arm926ejs mx25 karo tx25 tx25 - John Rigby <jcrigby@gmail.com>
Active arm arm926ejs mx25 syteco zmx25 zmx25 - Matthias Weisser <weisserm@arcor.de>
Active arm arm926ejs mx27 armadeus apf27 apf27 - Philippe Reynes <tremyfr@yahoo.fr>:Eric Jarrige <eric.jarrige@armadeus.org>
Active arm arm926ejs mx27 armadeus apf27 apf27 - Philippe Reynes <tremyfr@yahoo.fr>:Eric Jarrige <eric.jarrige@armadeus.org>
Active arm arm926ejs mx27 logicpd imx27lite imx27lite - Wolfgang Denk <wd@denx.de>
Active arm arm926ejs mx27 logicpd imx27lite magnesium - Heiko Schocher <hs@denx.de>
Active arm arm926ejs mxs bluegiga apx4devkit apx4devkit apx4devkit Lauri Hintsala <lauri.hintsala@bluegiga.com>

6
common/cmd_bmp.c
View File

@ -121,9 +121,9 @@ static int do_bmp_display(cmd_tbl_t * cmdtp, int flag, int argc, char * const ar
break;
case 4:
addr = simple_strtoul(argv[1], NULL, 16);
x = simple_strtoul(argv[2], NULL, 10);
y = simple_strtoul(argv[3], NULL, 10);
break;
x = simple_strtoul(argv[2], NULL, 10);
y = simple_strtoul(argv[3], NULL, 10);
break;
default:
return CMD_RET_USAGE;
}

2
common/main.c
View File

@ -365,7 +365,7 @@ static void process_boot_delay(void)
#ifdef CONFIG_BOOTCOUNT_LIMIT
if (bootlimit && (bootcount > bootlimit)) {
printf ("Warning: Bootlimit (%u) exceeded. Using altbootcmd.\n",
(unsigned)bootlimit);
(unsigned)bootlimit);
s = getenv ("altbootcmd");
}
else

2
config.mk
View File

@ -320,7 +320,7 @@ endif
# Linus' kernel sanity checking tool
CHECKFLAGS := -D__linux__ -Dlinux -D__STDC__ -Dunix -D__unix__ \
-Wbitwise -Wno-return-void -D__CHECK_ENDIAN__ $(CF)
-Wbitwise -Wno-return-void -D__CHECK_ENDIAN__ $(CF)
# Location of a usable BFD library, where we define "usable" as
# "built for ${HOST}, supports ${TARGET}". Sensible values are

4
doc/DocBook/Makefile
View File

@ -134,7 +134,7 @@ build_main_index = rm -rf $(main_idx); \
quiet_cmd_db2html = HTML $@
cmd_db2html = xmlto html $(XMLTOFLAGS) -o $(patsubst %.html,%,$@) $< && \
echo '<a HREF="$(patsubst %.html,%,$(notdir $@))/index.html"> \
$(patsubst %.html,%,$(notdir $@))</a><p>' > $@
$(patsubst %.html,%,$(notdir $@))</a><p>' > $@
%.html: %.xml
@(which xmlto > /dev/null 2>&1) || \
@ -143,7 +143,7 @@ quiet_cmd_db2html = HTML $@
@rm -rf $@ $(patsubst %.html,%,$@)
$(call cmd_db2html)
@if [ ! -z "$(PNG-$(basename $(notdir $@)))" ]; then \
cp $(PNG-$(basename $(notdir $@))) $(patsubst %.html,%,$@); fi
cp $(PNG-$(basename $(notdir $@))) $(patsubst %.html,%,$@); fi
quiet_cmd_db2man = MAN $@
cmd_db2man = if grep -q refentry $<; then xmlto man $(XMLTOFLAGS) -o $(obj)/man $< ; gzip -f $(obj)/man/*.9; fi

34
doc/README.ext4
View File

@ -28,30 +28,30 @@ Steps to test:
1. After applying the patch, ext4 specific commands can be seen
in the boot loader prompt using
UBOOT #help
UBOOT #help
ext4load- load binary file from a Ext4 file system
ext4ls - list files in a directory (default /)
ext4write- create a file in ext4 formatted partition
ext4load- load binary file from a Ext4 file system
ext4ls - list files in a directory (default /)
ext4write- create a file in ext4 formatted partition
2. To list the files in ext4 formatted partition, execute
ext4ls <interface> <dev[:part]> [directory]
For example:
UBOOT #ext4ls mmc 0:5 /usr/lib
ext4ls <interface> <dev[:part]> [directory]
For example:
UBOOT #ext4ls mmc 0:5 /usr/lib
3. To read and load a file from an ext4 formatted partition to RAM, execute
ext4load <interface> <dev[:part]> [addr] [filename] [bytes]
For example:
UBOOT #ext4load mmc 2:2 0x30007fc0 uImage
ext4load <interface> <dev[:part]> [addr] [filename] [bytes]
For example:
UBOOT #ext4load mmc 2:2 0x30007fc0 uImage
4. To write a file to a ext4 formatted partition.
a) First load a file to RAM at a particular address for example 0x30007fc0.
Now execute ext4write command
ext4write <interface> <dev[:part]> [filename] [Address] [sizebytes]
For example:
UBOOT #ext4write mmc 2:2 /boot/uImage 0x30007fc0 6183120
(here 6183120 is the size of the file to be written)
Note: Absolute path is required for the file to be written
a) First load a file to RAM at a particular address for example 0x30007fc0.
Now execute ext4write command
ext4write <interface> <dev[:part]> [filename] [Address] [sizebytes]
For example:
UBOOT #ext4write mmc 2:2 /boot/uImage 0x30007fc0 6183120
(here 6183120 is the size of the file to be written)
Note: Absolute path is required for the file to be written
References :
-- ext4 implementation in Linux Kernel

6
doc/README.kwbimage
View File

@ -40,9 +40,9 @@ Board specific configuration file specifications:
------------------------------------------------
1. This file must present in the $(BOARDDIR). The default name is
kwbimage.cfg. The name can be set as part of the full path
to the file using CONFIG_SYS_KWD_CONFIG (probably in
include/configs/<yourboard>.h). The path should look like:
$(SRCTREE)/$(CONFIG_BOARDDIR)/<yourkwbimagename>.cfg
to the file using CONFIG_SYS_KWD_CONFIG (probably in
include/configs/<yourboard>.h). The path should look like:
$(SRCTREE)/$(CONFIG_BOARDDIR)/<yourkwbimagename>.cfg
2. This file can have empty lines and lines starting with "#" as first
character to put comments
3. This file can have configuration command lines as mentioned below,

2
doc/README.mxc_hab
View File

@ -20,7 +20,7 @@ Data Size: 327680 Bytes = 320.00 kB = 0.31 MB
Load Address: 177ff420
Entry Point: 17800000
HAB Blocks: 177ff400 00000000 0004dc00
^^^^^^^^ ^^^^^^^^ ^^^^^^^^
^^^^^^^^ ^^^^^^^^ ^^^^^^^^
| | |
| | -------- (1)
| |

24
doc/README.mxsimage
View File

@ -10,7 +10,7 @@ The mxsimage tool is targeted to be a simple replacement for the elftosb2 .
To generate an image, write an image configuration file and run:
mkimage -A arm -O u-boot -T mxsimage -n <path to configuration file> \
<output bootstream file>
<output bootstream file>
The output bootstream file is usually using the .sb file extension. Note
that the example configuration files for producing bootable BootStream with
@ -54,33 +54,33 @@ These semantics and rules will be outlined now.
LOAD u32_address string_filename
- Instructs the BootROM to load file pointed by "string_filename" onto
address "u32_address".
address "u32_address".
LOAD IVT u32_address u32_IVT_entry_point
- Crafts and loads IVT onto address "u32_address" with the entry point
of u32_IVT_entry_point.
of u32_IVT_entry_point.
- i.MX28-specific instruction!
LOAD DCD u32_address u32_DCD_block_ID
- Loads the DCD block with ID "u32_DCD_block_ID" onto address
"u32_address" and executes the contents of this DCD block
"u32_address" and executes the contents of this DCD block
- i.MX28-specific instruction!
FILL u32_address u32_pattern u32_length
- Starts to write memory from addres "u32_address" with a pattern
specified by "u32_pattern". Writes exactly "u32_length" bytes of the
specified by "u32_pattern". Writes exactly "u32_length" bytes of the
pattern.
JUMP [HAB] u32_address [u32_r0_arg]
- Jumps onto memory address specified by "u32_address" by setting this
address in PT. The BootROM will pass the "u32_r0_arg" value in ARM
address in PT. The BootROM will pass the "u32_r0_arg" value in ARM
register "r0" to the executed code if this option is specified.
Otherwise, ARM register "r0" will default to value 0x00000000. The
optional "HAB" flag is i.MX28-specific flag turning on the HAB boot.
CALL [HAB] u32_address [u32_r0_arg]
- See JUMP instruction above, as the operation is exactly the same with
one difference. The CALL instruction does allow returning into the
one difference. The CALL instruction does allow returning into the
BootROM from the executed code. U-Boot makes use of this in it's SPL
code.
@ -88,10 +88,10 @@ These semantics and rules will be outlined now.
- Restart the CPU and start booting from device specified by the
"string_mode" argument. The "string_mode" differs for each CPU
and can be:
i.MX23, string_mode = USB/I2C/SPI1_FLASH/SPI2_FLASH/NAND_BCH
JTAG/SPI3_EEPROM/SD_SSP0/SD_SSP1
i.MX28, string_mode = USB/I2C/SPI2_FLASH/SPI3_FLASH/NAND_BCH
JTAG/SPI2_EEPROM/SD_SSP0/SD_SSP1
i.MX23, string_mode = USB/I2C/SPI1_FLASH/SPI2_FLASH/NAND_BCH
JTAG/SPI3_EEPROM/SD_SSP0/SD_SSP1
i.MX28, string_mode = USB/I2C/SPI2_FLASH/SPI3_FLASH/NAND_BCH
JTAG/SPI2_EEPROM/SD_SSP0/SD_SSP1
- An optional "DCD" blocks can be added at the begining of the configuration
file. Note that the DCD is only supported on i.MX28.
@ -99,7 +99,7 @@ These semantics and rules will be outlined now.
configuration file.
- The DCD block has the following semantics:
DCD u32_DCD_block_ID
DCD u32_DCD_block_ID
- u32_DCD_block_ID :: The ID number of the DCD block, must match
the ID number used by "LOAD DCD" instruction.

2
doc/README.nokia_rx51
View File

@ -62,7 +62,7 @@ Available additional commands/variables:
* run trymmcscriptboot - Try to load and boot script ${mmcscriptfile}
* run trymmckernboot - Try to load and boot kernel image ${mmckernfile}
* run trymmckerninitrdboot - Try to load and boot kernel image ${mmckernfile}
with initrd image ${mmcinitrdfile}
with initrd image ${mmcinitrdfile}
Additional variables for loading files from mmc:

10
doc/README.ramboot-ppc85xx
View File

@ -23,11 +23,11 @@ methods could be handy.
the board.And then execute the bootloader from DDR.
Some usecases where this may be used:
- While developing some new feature of u-boot, for example USB driver or
SPI driver.
Suppose the board already has a working bootloader on it. And you would
prefer to keep it intact, at the same time want to test your bootloader.
In this case you can get your test bootloader binary into DDR via tftp
for example. Then execute the test bootloader.
SPI driver.
Suppose the board already has a working bootloader on it. And you would
prefer to keep it intact, at the same time want to test your bootloader.
In this case you can get your test bootloader binary into DDR via tftp
for example. Then execute the test bootloader.
- Suppose a platform already has a propreitery bootloader which does not
support for example AMP boot. In this case also RAM boot loader can be
utilized.

24
doc/README.trace
View File

@ -63,20 +63,20 @@ In: serial
Out: serial
Err: serial
=>trace stats
671,406 function sites
69,712 function calls
0 untracked function calls
73,373 traced function calls
16 maximum observed call depth
15 call depth limit
66,491 calls not traced due to depth
671,406 function sites
69,712 function calls
0 untracked function calls
73,373 traced function calls
16 maximum observed call depth
15 call depth limit
66,491 calls not traced due to depth
=>trace stats
671,406 function sites
671,406 function sites
1,279,450 function calls
0 untracked function calls
950,490 traced function calls (333217 dropped due to overflow)
16 maximum observed call depth
15 call depth limit
0 untracked function calls
950,490 traced function calls (333217 dropped due to overflow)
16 maximum observed call depth
15 call depth limit
1,275,767 calls not traced due to depth
=>trace calls 0 e00000
Call list dumped to 00000000, size 0xae0a40

4
doc/README.ubi
View File

@ -188,8 +188,8 @@ ubifsls [directory]
For example:
=> ubifsls
17442 Thu Jan 01 02:57:38 1970 imx28-evk.dtb
2998146 Thu Jan 01 02:57:43 1970 zImage
17442 Thu Jan 01 02:57:38 1970 imx28-evk.dtb
2998146 Thu Jan 01 02:57:43 1970 zImage
And the ubifsload command allows you to load a file from a UBI

18
doc/README.zfs
View File

@ -7,20 +7,20 @@ Steps to test:
1. After applying the patch, zfs specific commands can be seen
in the boot loader prompt using
UBOOT #help
UBOOT #help
zfsload- load binary file from a ZFS file system
zfsls - list files in a directory (default /)
zfsload- load binary file from a ZFS file system
zfsls - list files in a directory (default /)
2. To list the files in zfs pool, device or partition, execute
zfsls <interface> <dev[:part]> [POOL/@/dir/file]
For example:
UBOOT #zfsls mmc 0:5 /rpool/@/usr/bin/
zfsls <interface> <dev[:part]> [POOL/@/dir/file]
For example:
UBOOT #zfsls mmc 0:5 /rpool/@/usr/bin/
3. To read and load a file from an ZFS formatted partition to RAM, execute
zfsload <interface> <dev[:part]> [addr] [filename] [bytes]
For example:
UBOOT #zfsload mmc 2:2 0x30007fc0 /rpool/@/boot/uImage
zfsload <interface> <dev[:part]> [addr] [filename] [bytes]
For example:
UBOOT #zfsload mmc 2:2 0x30007fc0 /rpool/@/boot/uImage
References :
-- ZFS GRUB sources from Solaris GRUB-0.97

24
doc/driver-model/UDM-cores.txt
View File

@ -94,12 +94,12 @@ Pavel Herrmann <morpheus.ibis@gmail.com>
driver_activate(instance *inst);
This call will recursively activate all devices necessary for using the
specified device. the code could be simplified as:
{
if (is_activated(inst))
return;
driver_activate(inst->bus);
get_driver(inst)->probe(inst);
}
{
if (is_activated(inst))
return;
driver_activate(inst->bus);
get_driver(inst)->probe(inst);
}
The case with multiple parents will need to be handled here as well.
get_driver is an accessor to available drivers, which will get struct
@ -107,12 +107,12 @@ Pavel Herrmann <morpheus.ibis@gmail.com>
i2c_write(instance *inst, ...);
An actual call to some method of the driver. This code will look like:
{
driver_activate(inst);
struct instance *core = get_core_instance(CORE_I2C);
device_ops = get_ops(inst);
device_ops->write(...);
}
{
driver_activate(inst);
struct instance *core = get_core_instance(CORE_I2C);
device_ops = get_ops(inst);
device_ops->write(...);
}
get_ops will not be an exported function, it will be internal and specific
to the core, as it needs to know how are the ops stored, and what type

12
doc/driver-model/UDM-design.txt
View File

@ -87,7 +87,7 @@ III) The drivers
of the cores.
FIXME: Should *cores[] be really struct driver, pointing to drivers that
represent the cores? Shouldn't it be core instance pointer?
represent the cores? Shouldn't it be core instance pointer?
2) Instantiation of a driver
----------------------------
@ -101,7 +101,7 @@ III) The drivers
functions.
FIXME: We need some functions that will return list of busses of certain type
registered with the system so the user can find proper instance even if
registered with the system so the user can find proper instance even if
he has no bus pointer (this will come handy if the user isn't
registering the driver from board init function, but somewhere else).
@ -183,12 +183,12 @@ III) The drivers
int driver_bind(struct instance *in)
{
...
core_bind(&core_i2c_static_instance, in, i2c_bus_funcs);
...
core_bind(&core_i2c_static_instance, in, i2c_bus_funcs);
...
}
FIXME: What if we need to run-time determine, depending on some hardware
register, what kind of i2c_bus_funcs to pass?
register, what kind of i2c_bus_funcs to pass?
This makes the i2c core aware of a new bus. The i2c_bus_funcs is a constant
structure of functions any i2c bus driver must provide to work. This will
@ -196,7 +196,7 @@ III) The drivers
the pointer to the instance of a core this driver provides function to.
FIXME: Maybe replace "core-i2c" with CORE_I2C global pointer to an instance of
the core?
the core?
4) The instantiation of a core driver
-------------------------------------

4
doc/driver-model/UDM-gpio.txt
View File

@ -56,11 +56,11 @@ II) Approach
struct gpio_driver_ops {
int (*gpio_request)(struct instance *i, unsigned gpio,
const char *label);
const char *label);
int (*gpio_free)(struct instance *i, unsigned gpio);
int (*gpio_direction_input)(struct instance *i, unsigned gpio);
int (*gpio_direction_output)(struct instance *i, unsigned gpio,
int value);
int value);
int (*gpio_get_value)(struct instance *i, unsigned gpio);
void (*gpio_set_value)(struct instance *i, unsigned gpio, int value);
}

10
doc/driver-model/UDM-hwmon.txt
View File

@ -36,15 +36,15 @@ II) Approach
In the UDM each hwmon driver would register itself by a function
int hwmon_device_register(struct instance *i,
struct hwmon_device_ops *o);
struct hwmon_device_ops *o);
The structure being defined as follows:
struct hwmon_device_ops {
int (*read)(struct instance *i, int sensor, int reg);
int (*write)(struct instance *i, int sensor, int reg,
int val);
int (*get_temp)(struct instance *i, int sensor);
int (*read)(struct instance *i, int sensor, int reg);
int (*write)(struct instance *i, int sensor, int reg,
int val);
int (*get_temp)(struct instance *i, int sensor);
};

6
doc/driver-model/UDM-mmc.txt
View File

@ -107,7 +107,7 @@ struct mmc {
/* DRIVER: Function used to submit command to the card */
int (*send_cmd)(struct mmc *mmc,
struct mmc_cmd *cmd, struct mmc_data *data);
struct mmc_cmd *cmd, struct mmc_data *data);
/* DRIVER: Function used to configure the host */
void (*set_ios)(struct mmc *mmc);
@ -139,7 +139,7 @@ provided by the MMC driver:
struct mmc_driver_ops {
/* Function used to submit command to the card */
int (*send_cmd)(struct mmc *mmc,
struct mmc_cmd *cmd, struct mmc_data *data);
struct mmc_cmd *cmd, struct mmc_data *data);
/* DRIVER: Function used to configure the host */
void (*set_ios)(struct mmc *mmc);
/* Function used to initialize the host */
@ -206,7 +206,7 @@ struct mmc_card_props {
The probe() function will then register the MMC driver by calling:
mmc_device_register(struct instance *i, struct mmc_driver_ops *o,
struct mmc_driver_params *p);
struct mmc_driver_params *p);
The struct mmc_driver_params will have to be dynamic in some cases, but the
driver shouldn't modify it's contents elsewhere than in probe() call.

12
doc/driver-model/UDM-power.txt
View File

@ -57,20 +57,20 @@ III) Analysis of in-tree drivers
All methods of this file are moved to another location.
void ftpmu010_32768osc_enable(void): Move to boards hacks
void ftpmu010_mfpsr_select_dev(unsigned int dev): Move to board file
arch/nds32/lib/board.c
arch/nds32/lib/board.c
void ftpmu010_mfpsr_diselect_dev(unsigned int dev): Dead code
void ftpmu010_dlldis_disable(void): Dead code
void ftpmu010_sdram_clk_disable(unsigned int cr0): Move to board file
arch/nds32/lib/board.c
arch/nds32/lib/board.c
void ftpmu010_sdramhtc_set(unsigned int val): Move to board file
arch/nds32/lib/board.c
arch/nds32/lib/board.c
2) twl4030.c
------------
All methods of this file are moved to another location.
void twl4030_power_reset_init(void): Move to board hacks
void twl4030_pmrecv_vsel_cfg(u8 vsel_reg, u8 vsel_val, u8 dev_grp,
u8 dev_grp_sel): Move to board hacks
u8 dev_grp_sel): Move to board hacks
void twl4030_power_init(void): Move to board hacks
void twl4030_power_mmc_init(void): Move to board hacks
@ -83,6 +83,6 @@ III) Analysis of in-tree drivers
int twl6030_get_battery_voltage(void): Convert to new API
void twl6030_init_battery_charging(void): Convert to new API
void twl6030_power_mmc_init(): Move to board file
drivers/mmc/omap_hsmmc.c
drivers/mmc/omap_hsmmc.c
void twl6030_usb_device_settings(): Move to board file
drivers/usb/musb/omap3.c
drivers/usb/musb/omap3.c

26
doc/driver-model/UDM-rtc.txt
View File

@ -12,15 +12,15 @@ U-Boot currently implements one common API for RTC devices. The interface
is defined in include/rtc.h and comprises of functions and structures:
struct rtc_time {
int tm_sec;
int tm_min;
int tm_hour;
int tm_mday;
int tm_mon;
int tm_year;
int tm_wday;
int tm_yday;
int tm_isdst;
int tm_sec;
int tm_min;
int tm_hour;
int tm_mday;
int tm_mon;
int tm_year;
int tm_wday;
int tm_yday;
int tm_isdst;
};
int rtc_get (struct rtc_time *);
@ -42,14 +42,14 @@ II) Approach
In the UDM each rtc driver would register itself by a function
int rtc_device_register(struct instance *i,
struct rtc_device_ops *o);
struct rtc_device_ops *o);
The structure being defined as follows:
struct rtc_device_ops {
int (*get_time)(struct instance *i, struct rtc_time *t);
int (*set_time)(struct instance *i, struct rtc_time *t);
int (*reset)(struct instance *i);
int (*get_time)(struct instance *i, struct rtc_time *t);
int (*set_time)(struct instance *i, struct rtc_time *t);
int (*reset)(struct instance *i);
};

12
doc/driver-model/UDM-spi.txt
View File

@ -15,12 +15,12 @@ I) Overview
void spi_init(void);
struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
unsigned int max_hz, unsigned int mode);
unsigned int max_hz, unsigned int mode);
void spi_free_slave(struct spi_slave *slave);
int spi_claim_bus(struct spi_slave *slave);
void spi_release_bus(struct spi_slave *slave);
int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
const void *dout, void *din, unsigned long flags);
const void *dout, void *din, unsigned long flags);
int spi_cs_is_valid(unsigned int bus, unsigned int cs);
void spi_cs_activate(struct spi_slave *slave);
void spi_cs_deactivate(struct spi_slave *slave);
@ -69,13 +69,13 @@ II) Approach
struct ops {
int (*spi_request_bus)(struct instance *i, unsigned int bus,
unsigned int cs, unsigned int max_hz,
unsigned int mode);
unsigned int cs, unsigned int max_hz,
unsigned int mode);
void (*spi_release_bus)(struct instance *i);
int (*spi_xfer) (struct instance *i, unsigned int bitlen,
const void *dout, void *din, unsigned long flags);
const void *dout, void *din, unsigned long flags);
int (*spi_cs_is_valid)(struct instance *i, unsigned int bus,
unsigned int cs);
unsigned int cs);
void (*spi_cs_activate)(struct instance *i);
void (*spi_cs_deactivate)(struct instance *i);
void (*spi_set_speed)(struct instance *i, uint hz);

28
doc/driver-model/UDM-stdio.txt
View File

@ -17,29 +17,29 @@ Each device that wants to register with STDIO subsystem has to define struct
stdio_dev, defined in include/stdio_dev.h and containing the following fields:
struct stdio_dev {
int flags; /* Device flags: input/output/system */
int ext; /* Supported extensions */
char name[16]; /* Device name */
int flags; /* Device flags: input/output/system */
int ext; /* Supported extensions */
char name[16]; /* Device name */
/* GENERAL functions */
int (*start) (void); /* To start the device */
int (*stop) (void); /* To stop the device */
int (*start) (void); /* To start the device */
int (*stop) (void); /* To stop the device */
/* OUTPUT functions */
void (*putc) (const char c); /* To put a char */
void (*puts) (const char *s); /* To put a string (accelerator) */
void (*putc) (const char c); /* To put a char */
void (*puts) (const char *s); /* To put a string (accelerator) */
/* INPUT functions */
int (*tstc) (void); /* To test if a char is ready... */
int (*getc) (void); /* To get that char */
int (*tstc) (void); /* To test if a char is ready... */
int (*getc) (void); /* To get that char */
/* Other functions */
void *priv; /* Private extensions */
struct list_head list;
void *priv; /* Private extensions */
struct list_head list;
};
Currently used flags are DEV_FLAGS_INPUT, DEV_FLAGS_OUTPUT and DEV_FLAGS_SYSTEM,
@ -139,13 +139,13 @@ II) Approach
purpose. The following flags will be defined:
STDIO_FLG_STDIN ..... This device will be used as an input device. All input
from all devices with this flag set will be received
from all devices with this flag set will be received
and passed to the upper layers.
STDIO_FLG_STDOUT .... This device will be used as an output device. All
output sent to stdout will be routed to all devices
output sent to stdout will be routed to all devices
with this flag set.
STDIO_FLG_STDERR .... This device will be used as an standard error output
device. All output sent to stderr will be routed to
device. All output sent to stderr will be routed to
all devices with this flag set.
The "list" member of this structure allows to have a linked list of all

2
doc/driver-model/UDM-tpm.txt
View File

@ -14,7 +14,7 @@ controlling it is very much based on this. The API is very simple:
int tis_open(void);
int tis_close(void);
int tis_sendrecv(const u8 *sendbuf, size_t send_size,
u8 *recvbuf, size_t *recv_len);
u8 *recvbuf, size_t *recv_len);
The command operating the TPM chip only provides operations to send and receive
bytes from the chip.

6
doc/driver-model/UDM-watchdog.txt
View File

@ -41,13 +41,13 @@ II) Approach
In the UDM each watchdog driver would register itself by a function
int watchdog_device_register(struct instance *i,
const struct watchdog_device_ops *o);
const struct watchdog_device_ops *o);
The structure being defined as follows:
struct watchdog_device_ops {
int (*disable)(struct instance *i);
void (*reset)(struct instance *i);
int (*disable)(struct instance *i);
void (*reset)(struct instance *i);
};
The watchdog_init() function will be dissolved into probe() function.

20
drivers/mtd/nand/fsl_elbc_spl.c
View File

@ -59,20 +59,20 @@ static int nand_load_image(uint32_t offs, unsigned int uboot_size, void *vdst)
if (large) {
fmr |= FMR_ECCM;
out_be32(&regs->fcr, (NAND_CMD_READ0 << FCR_CMD0_SHIFT) |
(NAND_CMD_READSTART << FCR_CMD1_SHIFT));
(NAND_CMD_READSTART << FCR_CMD1_SHIFT));
out_be32(&regs->fir,
(FIR_OP_CW0 << FIR_OP0_SHIFT) |
(FIR_OP_CA << FIR_OP1_SHIFT) |
(FIR_OP_PA << FIR_OP2_SHIFT) |
(FIR_OP_CW1 << FIR_OP3_SHIFT) |
(FIR_OP_RBW << FIR_OP4_SHIFT));
(FIR_OP_CW0 << FIR_OP0_SHIFT) |
(FIR_OP_CA << FIR_OP1_SHIFT) |
(FIR_OP_PA << FIR_OP2_SHIFT) |
(FIR_OP_CW1 << FIR_OP3_SHIFT) |
(FIR_OP_RBW << FIR_OP4_SHIFT));
} else {
out_be32(&regs->fcr, NAND_CMD_READ0 << FCR_CMD0_SHIFT);
out_be32(&regs->fir,
(FIR_OP_CW0 << FIR_OP0_SHIFT) |
(FIR_OP_CA << FIR_OP1_SHIFT) |
(FIR_OP_PA << FIR_OP2_SHIFT) |
(FIR_OP_RBW << FIR_OP3_SHIFT));
(FIR_OP_CW0 << FIR_OP0_SHIFT) |
(FIR_OP_CA << FIR_OP1_SHIFT) |
(FIR_OP_PA << FIR_OP2_SHIFT) |
(FIR_OP_RBW << FIR_OP3_SHIFT));
}
out_be32(&regs->fbcr, 0);

8
drivers/mtd/nand/fsl_upm.c
View File

@ -112,10 +112,10 @@ static void fun_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
fsl_upm_run_pattern(&fun->upm, fun->width, io_addr, mar);
/*
* Some boards/chips needs this. At least the MPC8360E-RDK
* needs it. Probably weird chip, because I don't see any
* need for this on MPC8555E + Samsung K9F1G08U0A. Usually
* here are 0-2 unexpected busy states per block read.
* Some boards/chips needs this. At least the MPC8360E-RDK
* needs it. Probably weird chip, because I don't see any
* need for this on MPC8555E + Samsung K9F1G08U0A. Usually
* here are 0-2 unexpected busy states per block read.
*/
if (fun->wait_flags & FSL_UPM_WAIT_RUN_PATTERN)
fun_wait(fun);

2
drivers/mtd/nand/nand_base.c
View File

@ -3282,7 +3282,7 @@ int nand_scan_tail(struct mtd_info *mtd)
case NAND_ECC_NONE:
pr_warn("NAND_ECC_NONE selected by board driver. "
"This is not recommended !!\n");
"This is not recommended !!\n");
chip->ecc.read_page = nand_read_page_raw;
chip->ecc.write_page = nand_write_page_raw;
chip->ecc.read_oob = nand_read_oob_std;

4
drivers/mtd/nand/nand_util.c
View File

@ -142,8 +142,8 @@ int nand_erase_opts(nand_info_t *meminfo, const nand_erase_options_t *opts)
ops.mode = MTD_OPS_AUTO_OOB;
result = mtd_write_oob(meminfo,
erase.addr,
&ops);
erase.addr,
&ops);
if (result != 0) {
printf("\n%s: MTD writeoob failure: %d\n",
mtd_device, result);

4
drivers/mtd/ubi/crc32.c
View File

@ -102,7 +102,7 @@ u32 crc32_le(u32 crc, unsigned char const *p, size_t len)
if((len >= 4)){
/* load data 32 bits wide, xor data 32 bits wide. */
size_t save_len = len & 3;
len = len >> 2;
len = len >> 2;
--b; /* use pre increment below(*++b) for speed */
do {
crc ^= *++b;
@ -200,7 +200,7 @@ u32 __attribute_pure__ crc32_be(u32 crc, unsigned char const *p, size_t len)
if(likely(len >= 4)){
/* load data 32 bits wide, xor data 32 bits wide. */
size_t save_len = len & 3;
len = len >> 2;
len = len >> 2;
--b; /* use pre increment below(*++b) for speed */
do {
crc ^= *++b;

2
drivers/net/dm9000x.c
View File

@ -17,7 +17,7 @@ V0.11 06/20/2001 REG_0A bit3=1, default enable BP with DA match
R17 = (R17 & 0xfff0) | NF
v1.00 modify by simon 2001.9.5
change for kernel 2.4.x
change for kernel 2.4.x
v1.1 11/09/2001 fix force mode bug

2
drivers/net/plb2800_eth.c
View File

@ -260,7 +260,7 @@ static int plb2800_eth_recv(struct eth_device *dev)
printf("Received %d bytes\n", length);
#endif
NetReceive((void*)(NetRxPackets[rx_new]),
length - 4);
length - 4);
}
else
{

2
drivers/rtc/bfin_rtc.c
View File

@ -68,7 +68,7 @@ int rtc_set(struct rtc_time *tmp)
/* Calculate number of seconds this incoming time represents */
remain = mktime(tmp->tm_year, tmp->tm_mon, tmp->tm_mday,
tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
/* Figure out how many days since epoch */
days = remain / NUM_SECS_IN_DAY;

2
drivers/rtc/pl031.c
View File

@ -73,7 +73,7 @@ int rtc_set(struct rtc_time *tmp)
/* Calculate number of seconds this incoming time represents */
tim = mktime(tmp->tm_year, tmp->tm_mon, tmp->tm_mday,
tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
RTC_WRITE_REG(RTC_LR, tim);

4
drivers/spi/mpc8xxx_spi.c
View File

@ -110,10 +110,10 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
if (bitlen <= 16) {
if (bitlen <= 4)
spi->mode = (spi->mode & 0xff0fffff) |
(3 << 20);
(3 << 20);
else
spi->mode = (spi->mode & 0xff0fffff) |
((bitlen - 1) << 20);
((bitlen - 1) << 20);
} else {
spi->mode = (spi->mode & 0xff0fffff);
/* Set up the next iteration if sending > 32 bits */

10
drivers/spi/omap3_spi.c
View File

@ -50,7 +50,7 @@ static void omap3_spi_write_chconf(struct omap3_spi_slave *ds, int val)
static void omap3_spi_set_enable(struct omap3_spi_slave *ds, int enable)
{
writel(enable, &ds->regs->channel[ds->slave.cs].chctrl);
/* Flash post writes to make immediate effect */
/* Flash post writes to make immediate effect */
readl(&ds->regs->channel[ds->slave.cs].chctrl);
}
@ -253,9 +253,9 @@ int omap3_spi_write(struct spi_slave *slave, unsigned int len, const u8 *txp,
writel(txp[i], &ds->regs->channel[ds->slave.cs].tx);
}
/* wait to finish of transfer */
while (!(readl(&ds->regs->channel[ds->slave.cs].chstat) &
OMAP3_MCSPI_CHSTAT_EOT));
/* wait to finish of transfer */
while (!(readl(&ds->regs->channel[ds->slave.cs].chstat) &
OMAP3_MCSPI_CHSTAT_EOT));
/* Disable the channel otherwise the next immediate RX will get affected */
omap3_spi_set_enable(ds,OMAP3_MCSPI_CHCTRL_DIS);
@ -359,7 +359,7 @@ int omap3_spi_txrx(struct spi_slave *slave,
rxp[i] = readl(&ds->regs->channel[ds->slave.cs].rx);
}
/* Disable the channel */
omap3_spi_set_enable(ds,OMAP3_MCSPI_CHCTRL_DIS);
omap3_spi_set_enable(ds,OMAP3_MCSPI_CHCTRL_DIS);
/*if transfer must be terminated disable the channel*/
if (flags & SPI_XFER_END) {

2
drivers/video/ati_radeon_fb.h
View File

@ -92,7 +92,7 @@ static inline void radeon_engine_flush (struct radeonfb_info *rinfo)
/* initiate flush */
OUTREGP(RB2D_DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL,
~RB2D_DC_FLUSH_ALL);
~RB2D_DC_FLUSH_ALL);
for (i=0; i < 2000000; i++) {
if (!(INREG(RB2D_DSTCACHE_CTLSTAT) & RB2D_DC_BUSY))

2
fs/ubifs/super.c
View File

@ -771,7 +771,7 @@ static int mount_ubifs(struct ubifs_info *c)
dbg_msg("node sizes: ref %zu, cmt. start %zu, orph %zu",
UBIFS_REF_NODE_SZ, UBIFS_CS_NODE_SZ, UBIFS_ORPH_NODE_SZ);
dbg_msg("max. node sizes: data %zu, inode %zu dentry %zu",
UBIFS_MAX_DATA_NODE_SZ, UBIFS_MAX_INO_NODE_SZ,
UBIFS_MAX_DATA_NODE_SZ, UBIFS_MAX_INO_NODE_SZ,
UBIFS_MAX_DENT_NODE_SZ);
dbg_msg("dead watermark: %d", c->dead_wm);
dbg_msg("dark watermark: %d", c->dark_wm);

2
include/configs/DU440.h
View File

@ -223,7 +223,7 @@
"flash_self=run ramargs addip addtty optargs;" \
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
"net_nfs=tftp 200000 ${img};run nfsargs addip addtty optargs;" \
"bootm\0" \
"bootm\0" \
"rootpath=/tftpboot/du440/target_root_du440\0" \
"img=/tftpboot/du440/uImage\0" \
"kernel_addr=FFC00000\0" \

2
include/configs/P3G4.h
View File

@ -85,7 +85,7 @@
"flash_self=run ramargs addip addtty;" \
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
"bootm\0" \
"bootm\0" \
"rootpath=/opt/eldk/ppc_74xx\0" \
"bootfile=/tftpboot/p3g4/uImage\0" \
"kernel_addr=ff000000\0" \

6
include/configs/RBC823.h
View File

@ -262,8 +262,8 @@
*/
#define SCCR_MASK SCCR_EBDF11
#define CONFIG_SYS_SCCR (SCCR_RTDIV | SCCR_RTSEL | SCCR_CRQEN | \
SCCR_PRQEN | SCCR_EBDF00 | \
SCCR_COM01 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
SCCR_PRQEN | SCCR_EBDF00 | \
SCCR_COM01 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD001 | \
SCCR_DFALCD00)
@ -344,7 +344,7 @@
#define CONFIG_SYS_OR1_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_MSYS)
#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMB | \
BR_PS_8 | BR_V)
BR_PS_8 | BR_V)
/*
* BR4 and OR4 (SDRAM)

2
include/configs/alpr.h
View File

@ -148,7 +148,7 @@
"flash_self=run ramargs addip addtty;" \
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
"bootm\0" \
"bootm\0" \
"net_nfs_fdt=tftp 200000 ${bootfile};" \
"tftp ${fdt_addr} ${fdt_file};" \
"run nfsargs addip addtty;" \

4
include/configs/devkit8000.h
View File

@ -278,8 +278,8 @@
#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
#define CONFIG_SYS_INIT_RAM_SIZE 0x800
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - \
GENERATED_GBL_DATA_SIZE)
CONFIG_SYS_INIT_RAM_SIZE - \
GENERATED_GBL_DATA_SIZE)
/* SRAM config */
#define CONFIG_SYS_SRAM_START 0x40200000

2
include/configs/p3mx.h
View File

@ -194,7 +194,7 @@
"flash_self=run ramargs addip addtty;" \
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
"bootm\0" \
"bootm\0" \
"rootpath=/opt/eldk/ppc_6xx\0" \
"u-boot=p3mx/u-boot/u-boot.bin\0" \
"load=tftp 100000 ${u-boot}\0" \

2
include/configs/p3p440.h
View File

@ -129,7 +129,7 @@
"flash_self=run ramargs addip addtty;" \
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
"bootm\0" \
"bootm\0" \
"rootpath=/opt/eldk/ppc_4xx\0" \
"bootfile=/tftpboot/p3p440/uImage\0" \
"kernel_addr=ff800000\0" \

2
include/configs/pcs440ep.h
View File

@ -157,7 +157,7 @@
"flash_self=run ramargs addip addtty;" \
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
"bootm\0" \
"bootm\0" \
"rootpath=/opt/eldk/ppc_4xx\0" \
"bootfile=/tftpboot/pcs440ep/uImage\0" \
"kernel_addr=FFF00000\0" \

4
include/configs/pdnb3.h
View File

@ -131,7 +131,7 @@
"flash_self=run ramargs addip addtty;" \
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
"bootm\0" \
"bootm\0" \
"rootpath=/opt/buildroot\0" \
"bootfile=/tftpboot/netbox/uImage\0" \
"kernel_addr=50080000\0" \
@ -280,7 +280,7 @@
#define I2C_TRISTATE GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_I2C_SDA)
#define I2C_READ ((*IXP425_GPIO_GPINR & PB_SDA) != 0)
#define I2C_SDA(bit) if (bit) GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_I2C_SDA); \
else GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_I2C_SDA)
else GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_I2C_SDA)
#define I2C_SCL(bit) if (bit) GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_I2C_SCL); \
else GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_I2C_SCL)
#define I2C_DELAY udelay(3) /* 1/4 I2C clock duration */

2
include/configs/uc100.h
View File

@ -65,7 +65,7 @@
"flash_self=run ramargs addip addtty;" \
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
"bootm\0" \
"bootm\0" \
"rootpath=/opt/eldk/ppc_8xx\0" \
"bootfile=/tftpboot/uc100/uImage\0" \
"kernel_addr=40000000\0" \

4
include/configs/zeus.h
View File

@ -322,7 +322,7 @@
" ramdisk_size=${ramdisk_size}\0" \
"addip=setenv bootargs ${bootargs} " \
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
":${hostname}:${netdev}:off panic=1\0" \
":${hostname}:${netdev}:off panic=1\0" \
"addtty=setenv bootargs ${bootargs} console=ttyS0," \
"${baudrate}\0" \
"net_nfs=tftp ${kernel_mem_addr} ${file_kernel};" \
@ -352,7 +352,7 @@
"file_fs=/zeus/rootfs_ba.img\0" \
"tftp_fs=tftp 100000 ${file_fs}\0" \
"update_fs=protect off ff300000 ff87ffff;era ff300000 ff87ffff;"\
"cp.b 100000 ff300000 580000\0" \
"cp.b 100000 ff300000 580000\0" \
"upd_fs=run tftp_fs;run update_fs\0" \
"bootcmd=chkreset;run ramargs addip addtty addmisc;" \
"bootm ${kernel_fl_addr} ${ramdisk_fl_addr}\0" \

34
include/ddr_spd.h
View File

@ -39,7 +39,7 @@ typedef struct ddr1_spd_eeprom_s {
unsigned char dev_attr; /* 22 SDRAM Device Attributes */
unsigned char clk_cycle2; /* 23 Min SDRAM Cycle time @ CL=X-0.5 */
unsigned char clk_access2; /* 24 SDRAM Access from
Clk @ CL=X-0.5 (tAC) */
Clk @ CL=X-0.5 (tAC) */
unsigned char clk_cycle3; /* 25 Min SDRAM Cycle time @ CL=X-1 */
unsigned char clk_access3; /* 26 Max Access from Clk @ CL=X-1 (tAC) */
unsigned char trp; /* 27 Min Row Precharge Time (tRP)*/
@ -112,9 +112,9 @@ typedef struct ddr2_spd_eeprom_s {
unsigned char ca_setup; /* 32 Addr+Cmd Setup Time Before Clk (tIS) */
unsigned char ca_hold; /* 33 Addr+Cmd Hold Time After Clk (tIH) */
unsigned char data_setup; /* 34 Data Input Setup Time
Before Strobe (tDS) */
Before Strobe (tDS) */
unsigned char data_hold; /* 35 Data Input Hold Time
After Strobe (tDH) */
After Strobe (tDH) */
unsigned char twr; /* 36 Write Recovery time tWR */
unsigned char twtr; /* 37 Int write to read delay tWTR */
unsigned char trtp; /* 38 Int read to precharge delay tRTP */
@ -128,40 +128,40 @@ typedef struct ddr2_spd_eeprom_s {
unsigned char pll_relock; /* 46 PLL Relock time */
unsigned char Tcasemax; /* 47 Tcasemax */
unsigned char psiTAdram; /* 48 Thermal Resistance of DRAM Package from
Top (Case) to Ambient (Psi T-A DRAM) */
Top (Case) to Ambient (Psi T-A DRAM) */
unsigned char dt0_mode; /* 49 DRAM Case Temperature Rise from Ambient
due to Activate-Precharge/Mode Bits
due to Activate-Precharge/Mode Bits
(DT0/Mode Bits) */
unsigned char dt2n_dt2q; /* 50 DRAM Case Temperature Rise from Ambient
due to Precharge/Quiet Standby
due to Precharge/Quiet Standby
(DT2N/DT2Q) */
unsigned char dt2p; /* 51 DRAM Case Temperature Rise from Ambient
due to Precharge Power-Down (DT2P) */
due to Precharge Power-Down (DT2P) */
unsigned char dt3n; /* 52 DRAM Case Temperature Rise from Ambient
due to Active Standby (DT3N) */
due to Active Standby (DT3N) */
unsigned char dt3pfast; /* 53 DRAM Case Temperature Rise from Ambient
due to Active Power-Down with
due to Active Power-Down with
Fast PDN Exit (DT3Pfast) */
unsigned char dt3pslow; /* 54 DRAM Case Temperature Rise from Ambient
due to Active Power-Down with Slow
due to Active Power-Down with Slow
PDN Exit (DT3Pslow) */
unsigned char dt4r_dt4r4w; /* 55 DRAM Case Temperature Rise from Ambient
due to Page Open Burst Read/DT4R4W
due to Page Open Burst Read/DT4R4W
Mode Bit (DT4R/DT4R4W Mode Bit) */
unsigned char dt5b; /* 56 DRAM Case Temperature Rise from Ambient
due to Burst Refresh (DT5B) */
due to Burst Refresh (DT5B) */
unsigned char dt7; /* 57 DRAM Case Temperature Rise from Ambient
due to Bank Interleave Reads with
due to Bank Interleave Reads with
Auto-Precharge (DT7) */
unsigned char psiTApll; /* 58 Thermal Resistance of PLL Package form
Top (Case) to Ambient (Psi T-A PLL) */
Top (Case) to Ambient (Psi T-A PLL) */
unsigned char psiTAreg; /* 59 Thermal Reisitance of Register Package
from Top (Case) to Ambient
from Top (Case) to Ambient
(Psi T-A Register) */
unsigned char dtpllactive; /* 60 PLL Case Temperature Rise from Ambient
due to PLL Active (DT PLL Active) */
due to PLL Active (DT PLL Active) */
unsigned char dtregact; /* 61 Register Case Temperature Rise from
Ambient due to Register Active/Mode Bit
Ambient due to Register Active/Mode Bit
(DT Register Active/Mode Bit) */
unsigned char spd_rev; /* 62 SPD Data Revision Code */
unsigned char cksum; /* 63 Checksum for bytes 0-62 */

2
nand_spl/nand_boot_fsl_elbc.c
View File

@ -126,7 +126,7 @@ void nand_boot(void)
* Load U-Boot image from NAND into RAM
*/
nand_load(CONFIG_SYS_NAND_U_BOOT_OFFS, CONFIG_SYS_NAND_U_BOOT_SIZE,
(uchar *)CONFIG_SYS_NAND_U_BOOT_DST);
(uchar *)CONFIG_SYS_NAND_U_BOOT_DST);
/*
* Jump to U-Boot image

2
post/lib_powerpc/andi.c
View File

@ -89,7 +89,7 @@ int cpu_post_test_andi (void)
if (ret != 0)
{
post_log ("Error at andi test %d !\n", i);
post_log ("Error at andi test %d !\n", i);
}
}
}

32
post/lib_powerpc/cpu_asm.h
View File

@ -112,64 +112,64 @@
#define ASM_0(opcode) (opcode)
#define ASM_1(opcode, rd) ((opcode) + \
((rd) << 21))
((rd) << 21))
#define ASM_1C(opcode, cr) ((opcode) + \
((cr) << 23))
((cr) << 23))
#define ASM_11(opcode, rd, rs) ((opcode) + \
((rd) << 21) + \
((rd) << 21) + \
((rs) << 16))
#define ASM_11C(opcode, cd, cs) ((opcode) + \
((cd) << 23) + \
((cd) << 23) + \
((cs) << 18))
#define ASM_11X(opcode, rd, rs) ((opcode) + \
((rs) << 21) + \
((rs) << 21) + \
((rd) << 16))
#define ASM_11I(opcode, rd, rs, simm) ((opcode) + \
((rd) << 21) + \
((rd) << 21) + \
((rs) << 16) + \
((simm) & 0xffff))
#define ASM_11IF(opcode, rd, rs, simm) ((opcode) + \
((rd) << 21) + \
((rd) << 21) + \
((rs) << 16) + \
((simm) << 11))
#define ASM_11S(opcode, rd, rs, sh) ((opcode) + \
((rs) << 21) + \
((rs) << 21) + \
((rd) << 16) + \
((sh) << 11))
#define ASM_11IX(opcode, rd, rs, imm) ((opcode) + \
((rs) << 21) + \
((rs) << 21) + \
((rd) << 16) + \
((imm) & 0xffff))
#define ASM_12(opcode, rd, rs1, rs2) ((opcode) + \
((rd) << 21) + \
((rd) << 21) + \
((rs1) << 16) + \
((rs2) << 11))
#define ASM_12F(opcode, fd, fs1, fs2) ((opcode) + \
((fd) << 21) + \
((fd) << 21) + \
((fs1) << 16) + \
((fs2) << 11))
#define ASM_12X(opcode, rd, rs1, rs2) ((opcode) + \
((rs1) << 21) + \
((rs1) << 21) + \
((rd) << 16) + \
((rs2) << 11))
#define ASM_2C(opcode, cr, rs1, rs2) ((opcode) + \
((cr) << 23) + \
((cr) << 23) + \
((rs1) << 16) + \
((rs2) << 11))
#define ASM_1IC(opcode, cr, rs, imm) ((opcode) + \
((cr) << 23) + \
((cr) << 23) + \
((rs) << 16) + \
((imm) & 0xffff))
#define ASM_122(opcode, rd, rs1, rs2, imm1, imm2) \
((opcode) + \
((rs1) << 21) + \
((rs1) << 21) + \
((rd) << 16) + \
((rs2) << 11) + \
((imm1) << 6) + \
((imm2) << 1))
#define ASM_113(opcode, rd, rs, imm1, imm2, imm3) \
((opcode) + \
((rs) << 21) + \
((rs) << 21) + \
((rd) << 16) + \
((imm1) << 11) + \
((imm2) << 6) + \

6
post/lib_powerpc/rlwimi.c
View File

@ -114,7 +114,7 @@ int cpu_post_test_rlwimi (void)
if (ret != 0)
{
post_log ("Error at rlwimi test %d !\n", i);
post_log ("Error at rlwimi test %d !\n", i);
}
}
@ -127,8 +127,8 @@ int cpu_post_test_rlwimi (void)
if (ret != 0)
{
post_log ("Error at rlwimi test %d !\n", i);
}
post_log ("Error at rlwimi test %d !\n", i);
}
}
}
}

6
post/lib_powerpc/rlwinm.c
View File

@ -107,7 +107,7 @@ int cpu_post_test_rlwinm (void)
if (ret != 0)
{
post_log ("Error at rlwinm test %d !\n", i);
post_log ("Error at rlwinm test %d !\n", i);
}
}
@ -120,8 +120,8 @@ int cpu_post_test_rlwinm (void)
if (ret != 0)
{
post_log ("Error at rlwinm test %d !\n", i);
}
post_log ("Error at rlwinm test %d !\n", i);
}
}
}
}

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