vf610: add support for Phytec PCM052
Devices supported are: - NFC (NAND FLASH) - MMC - QSPI (SPI NOR FLASH) - I2C (only bus 2) - I2C RTC - I2C EEPROM - FEC Patch-series: 2 - remove useless CONFIG_SYS_SPD_BUS_NUM from config - remove include of config_cmd_default.h - remove duplicate CONFIG_CMD_NET Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
This commit is contained in:
Albert ARIBAUD \(3ADEV\)
Stefano Babic
parent
03544c6640
commit
931a1d2a14
@ -538,6 +538,10 @@ config TARGET_COLIBRI_VF
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bool "Support Colibri VF50/61"
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select CPU_V7
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config TARGET_PCM052
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bool "Support pcm-052"
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select CPU_V7
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config ARCH_ZYNQ
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bool "Xilinx Zynq Platform"
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select CPU_V7
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@ -753,6 +757,7 @@ source "board/maxbcm/Kconfig"
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source "board/mpl/vcma9/Kconfig"
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source "board/olimex/mx23_olinuxino/Kconfig"
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source "board/phytec/pcm051/Kconfig"
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source "board/phytec/pcm052/Kconfig"
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source "board/ppcag/bg0900/Kconfig"
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source "board/samsung/smdk2410/Kconfig"
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source "board/sandisk/sansa_fuze_plus/Kconfig"
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15
board/phytec/pcm052/Kconfig
Normal file
15
board/phytec/pcm052/Kconfig
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@ -0,0 +1,15 @@
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if TARGET_PCM052
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config SYS_BOARD
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default "pcm052"
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config SYS_VENDOR
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default "phytec"
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config SYS_SOC
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default "vf610"
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config SYS_CONFIG_NAME
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default "pcm052"
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endif
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6
board/phytec/pcm052/MAINTAINERS
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6
board/phytec/pcm052/MAINTAINERS
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@ -0,0 +1,6 @@
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PCM052 BOARD
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M: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
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S: Maintained
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F: board/phytec/pcm052/
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F: include/configs/pcm052.h
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F: configs/pcm052_defconfig
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7
board/phytec/pcm052/Makefile
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7
board/phytec/pcm052/Makefile
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@ -0,0 +1,7 @@
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#
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# Copyright 2013 Freescale Semiconductor, Inc.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y := pcm052.o
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17
board/phytec/pcm052/imximage.cfg
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17
board/phytec/pcm052/imximage.cfg
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@ -0,0 +1,17 @@
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/*
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* Copyright 2015 3ADEV <http://www.3adev.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*
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* Refer docs/README.imxmage for more details about how-to configure
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* and create imximage boot image
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*
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* The syntax is taken as close as possible with the kwbimage
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*/
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#include <asm/imx-common/imximage.cfg>
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/* image version */
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IMAGE_VERSION 2
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/* Boot Offset 0x400, valid for both SD and NAND boot */
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BOOT_OFFSET FLASH_OFFSET_STANDARD
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515
board/phytec/pcm052/pcm052.c
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515
board/phytec/pcm052/pcm052.c
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@ -0,0 +1,515 @@
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/*
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* Copyright 2013 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/iomux-vf610.h>
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#include <asm/arch/ddrmc-vf610.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/arch/clock.h>
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#include <mmc.h>
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#include <fsl_esdhc.h>
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#include <miiphy.h>
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#include <netdev.h>
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#include <i2c.h>
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* Default DDR pad settings in arch/arm/include/asm/arch-vf610/iomux-vf610.h
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* do not match our settings. Let us (re)define our own settings here.
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*/
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#define PCM052_VF610_DDR_PAD_CTRL PAD_CTL_DSE_20ohm
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#define PCM052_VF610_DDR_PAD_CTRL_1 (PAD_CTL_DSE_20ohm | \
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PAD_CTL_INPUT_DIFFERENTIAL)
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#define PCM052_VF610_DDR_RESET_PAD_CTL (PAD_CTL_DSE_150ohm | \
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PAD_CTL_PUS_100K_UP | \
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PAD_CTL_INPUT_DIFFERENTIAL)
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enum {
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PCM052_VF610_PAD_DDR_RESETB = IOMUX_PAD(0x021c, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_RESET_PAD_CTL),
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PCM052_VF610_PAD_DDR_A15__DDR_A_15 = IOMUX_PAD(0x0220, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
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PCM052_VF610_PAD_DDR_A14__DDR_A_14 = IOMUX_PAD(0x0224, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
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PCM052_VF610_PAD_DDR_A13__DDR_A_13 = IOMUX_PAD(0x0228, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
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PCM052_VF610_PAD_DDR_A12__DDR_A_12 = IOMUX_PAD(0x022c, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
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PCM052_VF610_PAD_DDR_A11__DDR_A_11 = IOMUX_PAD(0x0230, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
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PCM052_VF610_PAD_DDR_A10__DDR_A_10 = IOMUX_PAD(0x0234, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
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PCM052_VF610_PAD_DDR_A9__DDR_A_9 = IOMUX_PAD(0x0238, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
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PCM052_VF610_PAD_DDR_A8__DDR_A_8 = IOMUX_PAD(0x023c, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
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PCM052_VF610_PAD_DDR_A7__DDR_A_7 = IOMUX_PAD(0x0240, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
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PCM052_VF610_PAD_DDR_A6__DDR_A_6 = IOMUX_PAD(0x0244, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
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PCM052_VF610_PAD_DDR_A5__DDR_A_5 = IOMUX_PAD(0x0248, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
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PCM052_VF610_PAD_DDR_A4__DDR_A_4 = IOMUX_PAD(0x024c, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
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PCM052_VF610_PAD_DDR_A3__DDR_A_3 = IOMUX_PAD(0x0250, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
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PCM052_VF610_PAD_DDR_A2__DDR_A_2 = IOMUX_PAD(0x0254, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
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PCM052_VF610_PAD_DDR_A1__DDR_A_1 = IOMUX_PAD(0x0258, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
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PCM052_VF610_PAD_DDR_A0__DDR_A_0 = IOMUX_PAD(0x025c, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
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PCM052_VF610_PAD_DDR_BA2__DDR_BA_2 = IOMUX_PAD(0x0260, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
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PCM052_VF610_PAD_DDR_BA1__DDR_BA_1 = IOMUX_PAD(0x0264, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
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PCM052_VF610_PAD_DDR_BA0__DDR_BA_0 = IOMUX_PAD(0x0268, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
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PCM052_VF610_PAD_DDR_CAS__DDR_CAS_B = IOMUX_PAD(0x026c, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
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PCM052_VF610_PAD_DDR_CKE__DDR_CKE_0 = IOMUX_PAD(0x0270, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
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PCM052_VF610_PAD_DDR_CLK__DDR_CLK_0 = IOMUX_PAD(0x0274, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL_1),
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PCM052_VF610_PAD_DDR_CS__DDR_CS_B_0 = IOMUX_PAD(0x0278, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
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PCM052_VF610_PAD_DDR_D15__DDR_D_15 = IOMUX_PAD(0x027c, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
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PCM052_VF610_PAD_DDR_D14__DDR_D_14 = IOMUX_PAD(0x0280, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
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PCM052_VF610_PAD_DDR_D13__DDR_D_13 = IOMUX_PAD(0x0284, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
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PCM052_VF610_PAD_DDR_D12__DDR_D_12 = IOMUX_PAD(0x0288, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
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PCM052_VF610_PAD_DDR_D11__DDR_D_11 = IOMUX_PAD(0x028c, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
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PCM052_VF610_PAD_DDR_D10__DDR_D_10 = IOMUX_PAD(0x0290, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
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PCM052_VF610_PAD_DDR_D9__DDR_D_9 = IOMUX_PAD(0x0294, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
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PCM052_VF610_PAD_DDR_D8__DDR_D_8 = IOMUX_PAD(0x0298, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
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PCM052_VF610_PAD_DDR_D7__DDR_D_7 = IOMUX_PAD(0x029c, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
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PCM052_VF610_PAD_DDR_D6__DDR_D_6 = IOMUX_PAD(0x02a0, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
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PCM052_VF610_PAD_DDR_D5__DDR_D_5 = IOMUX_PAD(0x02a4, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
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PCM052_VF610_PAD_DDR_D4__DDR_D_4 = IOMUX_PAD(0x02a8, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
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PCM052_VF610_PAD_DDR_D3__DDR_D_3 = IOMUX_PAD(0x02ac, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
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PCM052_VF610_PAD_DDR_D2__DDR_D_2 = IOMUX_PAD(0x02b0, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
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PCM052_VF610_PAD_DDR_D1__DDR_D_1 = IOMUX_PAD(0x02b4, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
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PCM052_VF610_PAD_DDR_D0__DDR_D_0 = IOMUX_PAD(0x02b8, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
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PCM052_VF610_PAD_DDR_DQM1__DDR_DQM_1 = IOMUX_PAD(0x02bc, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
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PCM052_VF610_PAD_DDR_DQM0__DDR_DQM_0 = IOMUX_PAD(0x02c0, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
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PCM052_VF610_PAD_DDR_DQS1__DDR_DQS_1 = IOMUX_PAD(0x02c4, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL_1),
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PCM052_VF610_PAD_DDR_DQS0__DDR_DQS_0 = IOMUX_PAD(0x02c8, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL_1),
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PCM052_VF610_PAD_DDR_RAS__DDR_RAS_B = IOMUX_PAD(0x02cc, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
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PCM052_VF610_PAD_DDR_WE__DDR_WE_B = IOMUX_PAD(0x02d0, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
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PCM052_VF610_PAD_DDR_ODT1__DDR_ODT_0 = IOMUX_PAD(0x02d4, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
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PCM052_VF610_PAD_DDR_ODT0__DDR_ODT_1 = IOMUX_PAD(0x02d8, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
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PCM052_VF610_PAD_DDR_DDRBYTE1__DDR_DDRBYTE1 = IOMUX_PAD(0x02dc, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
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PCM052_VF610_PAD_DDR_DDRBYTE0__DDR_DDRBYTE0 = IOMUX_PAD(0x02e0, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL),
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};
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static struct ddrmc_cr_setting pcm052_cr_settings[] = {
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/* not in the datasheets, but in the original code */
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{ 0x00002000, 105 },
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{ 0x00000020, 110 },
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/* AXI */
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{ DDRMC_CR117_AXI0_W_PRI(1) | DDRMC_CR117_AXI0_R_PRI(1), 117 },
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{ DDRMC_CR118_AXI1_W_PRI(1) | DDRMC_CR118_AXI1_R_PRI(1), 118 },
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{ DDRMC_CR120_AXI0_PRI1_RPRI(2) |
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DDRMC_CR120_AXI0_PRI0_RPRI(2), 120 },
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{ DDRMC_CR121_AXI0_PRI3_RPRI(2) |
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DDRMC_CR121_AXI0_PRI2_RPRI(2), 121 },
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{ DDRMC_CR122_AXI1_PRI1_RPRI(1) | DDRMC_CR122_AXI1_PRI0_RPRI(1) |
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DDRMC_CR122_AXI0_PRIRLX(100), 122 },
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{ DDRMC_CR123_AXI1_P_ODR_EN | DDRMC_CR123_AXI1_PRI3_RPRI(1) |
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DDRMC_CR123_AXI1_PRI2_RPRI(1), 123 },
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{ DDRMC_CR124_AXI1_PRIRLX(100), 124 },
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{ DDRMC_CR126_PHY_RDLAT(11), 126 },
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{ DDRMC_CR132_WRLAT_ADJ(5) | DDRMC_CR132_RDLAT_ADJ(6), 132 },
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{ DDRMC_CR137_PHYCTL_DL(2), 137 },
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{ DDRMC_CR139_PHY_WRLV_RESPLAT(4) | DDRMC_CR139_PHY_WRLV_LOAD(7) |
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DDRMC_CR139_PHY_WRLV_DLL(3) |
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DDRMC_CR139_PHY_WRLV_EN(3), 139 },
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{ DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(13) |
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DDRMC_CR154_PAD_ZQ_MODE(1) |
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DDRMC_CR154_DDR_SEL_PAD_CONTR(3) |
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DDRMC_CR154_PAD_ZQ_HW_FOR(0), 154 },
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{ DDRMC_CR155_PAD_ODT_BYTE1(5) | DDRMC_CR155_PAD_ODT_BYTE0(5), 155 },
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{ DDRMC_CR158_TWR(6), 158 },
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{ DDRMC_CR161_ODT_EN(0) | DDRMC_CR161_TODTH_RD(0) |
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DDRMC_CR161_TODTH_WR(6), 161 },
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/* end marker */
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{ 0, -1 }
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};
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/* PHY settings -- most of them differ from default in imx-regs.h */
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#define PCM052_DDRMC_PHY_DQ_TIMING 0x00002213
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#define PCM052_DDRMC_PHY_CTRL 0x00290000
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#define PCM052_DDRMC_PHY_SLAVE_CTRL 0x00002c00
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#define PCM052_DDRMC_PHY_PROC_PAD_ODT 0x00010020
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static struct ddrmc_phy_setting pcm052_phy_settings[] = {
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{ PCM052_DDRMC_PHY_DQ_TIMING, 0 },
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{ PCM052_DDRMC_PHY_DQ_TIMING, 16 },
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{ PCM052_DDRMC_PHY_DQ_TIMING, 32 },
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{ PCM052_DDRMC_PHY_DQ_TIMING, 48 },
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{ DDRMC_PHY_DQS_TIMING, 1 },
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{ DDRMC_PHY_DQS_TIMING, 17 },
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{ DDRMC_PHY_DQS_TIMING, 33 },
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{ DDRMC_PHY_DQS_TIMING, 49 },
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{ PCM052_DDRMC_PHY_CTRL, 2 },
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{ PCM052_DDRMC_PHY_CTRL, 18 },
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{ PCM052_DDRMC_PHY_CTRL, 34 },
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{ DDRMC_PHY_MASTER_CTRL, 3 },
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{ DDRMC_PHY_MASTER_CTRL, 19 },
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{ DDRMC_PHY_MASTER_CTRL, 35 },
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{ PCM052_DDRMC_PHY_SLAVE_CTRL, 4 },
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{ PCM052_DDRMC_PHY_SLAVE_CTRL, 20 },
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{ PCM052_DDRMC_PHY_SLAVE_CTRL, 36 },
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{ DDRMC_PHY50_DDR3_MODE | DDRMC_PHY50_EN_SW_HALF_CYCLE, 50 },
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{ PCM052_DDRMC_PHY_PROC_PAD_ODT, 52 },
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/* end marker */
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{ 0, -1 }
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};
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int dram_init(void)
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{
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static const struct ddr3_jedec_timings pcm052_ddr_timings = {
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.tinit = 5,
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.trst_pwron = 80000,
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.cke_inactive = 200000,
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.wrlat = 5,
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.caslat_lin = 12,
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.trc = 6,
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.trrd = 4,
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.tccd = 4,
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.tbst_int_interval = 4,
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.tfaw = 18,
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.trp = 6,
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.twtr = 4,
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.tras_min = 15,
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.tmrd = 4,
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.trtp = 4,
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.tras_max = 14040,
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.tmod = 12,
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.tckesr = 4,
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.tcke = 3,
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.trcd_int = 6,
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.tras_lockout = 1,
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.tdal = 10,
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.bstlen = 3,
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.tdll = 512,
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.trp_ab = 6,
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.tref = 1542,
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.trfc = 64,
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.tref_int = 5,
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.tpdex = 3,
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.txpdll = 10,
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.txsnr = 68,
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.txsr = 506,
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.cksrx = 5,
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.cksre = 5,
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.freq_chg_en = 1,
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.zqcl = 256,
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.zqinit = 512,
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.zqcs = 64,
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.ref_per_zq = 64,
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.zqcs_rotate = 1,
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.aprebit = 10,
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.cmd_age_cnt = 255,
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.age_cnt = 255,
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.q_fullness = 0,
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.odt_rd_mapcs0 = 1,
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.odt_wr_mapcs0 = 1,
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.wlmrd = 40,
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.wldqsen = 25,
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};
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static const iomux_v3_cfg_t pcm052_pads[] = {
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PCM052_VF610_PAD_DDR_A15__DDR_A_15,
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PCM052_VF610_PAD_DDR_A14__DDR_A_14,
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PCM052_VF610_PAD_DDR_A13__DDR_A_13,
|
||||
PCM052_VF610_PAD_DDR_A12__DDR_A_12,
|
||||
PCM052_VF610_PAD_DDR_A11__DDR_A_11,
|
||||
PCM052_VF610_PAD_DDR_A10__DDR_A_10,
|
||||
PCM052_VF610_PAD_DDR_A9__DDR_A_9,
|
||||
PCM052_VF610_PAD_DDR_A8__DDR_A_8,
|
||||
PCM052_VF610_PAD_DDR_A7__DDR_A_7,
|
||||
PCM052_VF610_PAD_DDR_A6__DDR_A_6,
|
||||
PCM052_VF610_PAD_DDR_A5__DDR_A_5,
|
||||
PCM052_VF610_PAD_DDR_A4__DDR_A_4,
|
||||
PCM052_VF610_PAD_DDR_A3__DDR_A_3,
|
||||
PCM052_VF610_PAD_DDR_A2__DDR_A_2,
|
||||
PCM052_VF610_PAD_DDR_A1__DDR_A_1,
|
||||
PCM052_VF610_PAD_DDR_A0__DDR_A_0,
|
||||
PCM052_VF610_PAD_DDR_BA2__DDR_BA_2,
|
||||
PCM052_VF610_PAD_DDR_BA1__DDR_BA_1,
|
||||
PCM052_VF610_PAD_DDR_BA0__DDR_BA_0,
|
||||
PCM052_VF610_PAD_DDR_CAS__DDR_CAS_B,
|
||||
PCM052_VF610_PAD_DDR_CKE__DDR_CKE_0,
|
||||
PCM052_VF610_PAD_DDR_CLK__DDR_CLK_0,
|
||||
PCM052_VF610_PAD_DDR_CS__DDR_CS_B_0,
|
||||
PCM052_VF610_PAD_DDR_D15__DDR_D_15,
|
||||
PCM052_VF610_PAD_DDR_D14__DDR_D_14,
|
||||
PCM052_VF610_PAD_DDR_D13__DDR_D_13,
|
||||
PCM052_VF610_PAD_DDR_D12__DDR_D_12,
|
||||
PCM052_VF610_PAD_DDR_D11__DDR_D_11,
|
||||
PCM052_VF610_PAD_DDR_D10__DDR_D_10,
|
||||
PCM052_VF610_PAD_DDR_D9__DDR_D_9,
|
||||
PCM052_VF610_PAD_DDR_D8__DDR_D_8,
|
||||
PCM052_VF610_PAD_DDR_D7__DDR_D_7,
|
||||
PCM052_VF610_PAD_DDR_D6__DDR_D_6,
|
||||
PCM052_VF610_PAD_DDR_D5__DDR_D_5,
|
||||
PCM052_VF610_PAD_DDR_D4__DDR_D_4,
|
||||
PCM052_VF610_PAD_DDR_D3__DDR_D_3,
|
||||
PCM052_VF610_PAD_DDR_D2__DDR_D_2,
|
||||
PCM052_VF610_PAD_DDR_D1__DDR_D_1,
|
||||
PCM052_VF610_PAD_DDR_D0__DDR_D_0,
|
||||
PCM052_VF610_PAD_DDR_DQM1__DDR_DQM_1,
|
||||
PCM052_VF610_PAD_DDR_DQM0__DDR_DQM_0,
|
||||
PCM052_VF610_PAD_DDR_DQS1__DDR_DQS_1,
|
||||
PCM052_VF610_PAD_DDR_DQS0__DDR_DQS_0,
|
||||
PCM052_VF610_PAD_DDR_RAS__DDR_RAS_B,
|
||||
PCM052_VF610_PAD_DDR_WE__DDR_WE_B,
|
||||
PCM052_VF610_PAD_DDR_ODT1__DDR_ODT_0,
|
||||
PCM052_VF610_PAD_DDR_ODT0__DDR_ODT_1,
|
||||
PCM052_VF610_PAD_DDR_DDRBYTE1__DDR_DDRBYTE1,
|
||||
PCM052_VF610_PAD_DDR_DDRBYTE0__DDR_DDRBYTE0,
|
||||
PCM052_VF610_PAD_DDR_RESETB,
|
||||
};
|
||||
|
||||
imx_iomux_v3_setup_multiple_pads(pcm052_pads, ARRAY_SIZE(pcm052_pads));
|
||||
|
||||
ddrmc_ctrl_init_ddr3(&pcm052_ddr_timings, pcm052_cr_settings,
|
||||
pcm052_phy_settings, 1, 2);
|
||||
|
||||
gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void setup_iomux_uart(void)
|
||||
{
|
||||
static const iomux_v3_cfg_t uart1_pads[] = {
|
||||
NEW_PAD_CTRL(VF610_PAD_PTB4__UART1_TX, VF610_UART_PAD_CTRL),
|
||||
NEW_PAD_CTRL(VF610_PAD_PTB5__UART1_RX, VF610_UART_PAD_CTRL),
|
||||
};
|
||||
|
||||
imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
|
||||
}
|
||||
|
||||
#define ENET_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH | \
|
||||
PAD_CTL_DSE_50ohm | PAD_CTL_OBE_IBE_ENABLE)
|
||||
|
||||
static void setup_iomux_enet(void)
|
||||
{
|
||||
static const iomux_v3_cfg_t enet0_pads[] = {
|
||||
NEW_PAD_CTRL(VF610_PAD_PTA6__RMII0_CLKIN, ENET_PAD_CTRL),
|
||||
NEW_PAD_CTRL(VF610_PAD_PTC1__RMII0_MDIO, ENET_PAD_CTRL),
|
||||
NEW_PAD_CTRL(VF610_PAD_PTC0__RMII0_MDC, ENET_PAD_CTRL),
|
||||
NEW_PAD_CTRL(VF610_PAD_PTC2__RMII0_CRS_DV, ENET_PAD_CTRL),
|
||||
NEW_PAD_CTRL(VF610_PAD_PTC3__RMII0_RD1, ENET_PAD_CTRL),
|
||||
NEW_PAD_CTRL(VF610_PAD_PTC4__RMII0_RD0, ENET_PAD_CTRL),
|
||||
NEW_PAD_CTRL(VF610_PAD_PTC5__RMII0_RXER, ENET_PAD_CTRL),
|
||||
NEW_PAD_CTRL(VF610_PAD_PTC6__RMII0_TD1, ENET_PAD_CTRL),
|
||||
NEW_PAD_CTRL(VF610_PAD_PTC7__RMII0_TD0, ENET_PAD_CTRL),
|
||||
NEW_PAD_CTRL(VF610_PAD_PTC8__RMII0_TXEN, ENET_PAD_CTRL),
|
||||
};
|
||||
|
||||
imx_iomux_v3_setup_multiple_pads(enet0_pads, ARRAY_SIZE(enet0_pads));
|
||||
}
|
||||
|
||||
/*
|
||||
* I2C2 is the only I2C used, on pads PTA22/PTA23.
|
||||
*/
|
||||
|
||||
static void setup_iomux_i2c(void)
|
||||
{
|
||||
static const iomux_v3_cfg_t i2c_pads[] = {
|
||||
VF610_PAD_PTA22__I2C2_SCL,
|
||||
VF610_PAD_PTA23__I2C2_SDA,
|
||||
};
|
||||
|
||||
imx_iomux_v3_setup_multiple_pads(i2c_pads, ARRAY_SIZE(i2c_pads));
|
||||
}
|
||||
|
||||
#ifdef CONFIG_NAND_VF610_NFC
|
||||
static void setup_iomux_nfc(void)
|
||||
{
|
||||
static const iomux_v3_cfg_t nfc_pads[] = {
|
||||
VF610_PAD_PTD31__NF_IO15,
|
||||
VF610_PAD_PTD30__NF_IO14,
|
||||
VF610_PAD_PTD29__NF_IO13,
|
||||
VF610_PAD_PTD28__NF_IO12,
|
||||
VF610_PAD_PTD27__NF_IO11,
|
||||
VF610_PAD_PTD26__NF_IO10,
|
||||
VF610_PAD_PTD25__NF_IO9,
|
||||
VF610_PAD_PTD24__NF_IO8,
|
||||
VF610_PAD_PTD23__NF_IO7,
|
||||
VF610_PAD_PTD22__NF_IO6,
|
||||
VF610_PAD_PTD21__NF_IO5,
|
||||
VF610_PAD_PTD20__NF_IO4,
|
||||
VF610_PAD_PTD19__NF_IO3,
|
||||
VF610_PAD_PTD18__NF_IO2,
|
||||
VF610_PAD_PTD17__NF_IO1,
|
||||
VF610_PAD_PTD16__NF_IO0,
|
||||
VF610_PAD_PTB24__NF_WE_B,
|
||||
VF610_PAD_PTB25__NF_CE0_B,
|
||||
VF610_PAD_PTB27__NF_RE_B,
|
||||
VF610_PAD_PTC26__NF_RB_B,
|
||||
VF610_PAD_PTC27__NF_ALE,
|
||||
VF610_PAD_PTC28__NF_CLE
|
||||
};
|
||||
|
||||
imx_iomux_v3_setup_multiple_pads(nfc_pads, ARRAY_SIZE(nfc_pads));
|
||||
}
|
||||
#endif
|
||||
|
||||
static void setup_iomux_qspi(void)
|
||||
{
|
||||
static const iomux_v3_cfg_t qspi0_pads[] = {
|
||||
VF610_PAD_PTD0__QSPI0_A_QSCK,
|
||||
VF610_PAD_PTD1__QSPI0_A_CS0,
|
||||
VF610_PAD_PTD2__QSPI0_A_DATA3,
|
||||
VF610_PAD_PTD3__QSPI0_A_DATA2,
|
||||
VF610_PAD_PTD4__QSPI0_A_DATA1,
|
||||
VF610_PAD_PTD5__QSPI0_A_DATA0,
|
||||
VF610_PAD_PTD7__QSPI0_B_QSCK,
|
||||
VF610_PAD_PTD8__QSPI0_B_CS0,
|
||||
VF610_PAD_PTD9__QSPI0_B_DATA3,
|
||||
VF610_PAD_PTD10__QSPI0_B_DATA2,
|
||||
VF610_PAD_PTD11__QSPI0_B_DATA1,
|
||||
VF610_PAD_PTD12__QSPI0_B_DATA0,
|
||||
};
|
||||
|
||||
imx_iomux_v3_setup_multiple_pads(qspi0_pads, ARRAY_SIZE(qspi0_pads));
|
||||
}
|
||||
|
||||
#define ESDHC_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH | \
|
||||
PAD_CTL_DSE_20ohm | PAD_CTL_OBE_IBE_ENABLE)
|
||||
|
||||
struct fsl_esdhc_cfg esdhc_cfg[1] = {
|
||||
{ESDHC1_BASE_ADDR},
|
||||
};
|
||||
|
||||
int board_mmc_getcd(struct mmc *mmc)
|
||||
{
|
||||
/* eSDHC1 is always present */
|
||||
return 1;
|
||||
}
|
||||
|
||||
int board_mmc_init(bd_t *bis)
|
||||
{
|
||||
static const iomux_v3_cfg_t esdhc1_pads[] = {
|
||||
NEW_PAD_CTRL(VF610_PAD_PTA24__ESDHC1_CLK, ESDHC_PAD_CTRL),
|
||||
NEW_PAD_CTRL(VF610_PAD_PTA25__ESDHC1_CMD, ESDHC_PAD_CTRL),
|
||||
NEW_PAD_CTRL(VF610_PAD_PTA26__ESDHC1_DAT0, ESDHC_PAD_CTRL),
|
||||
NEW_PAD_CTRL(VF610_PAD_PTA27__ESDHC1_DAT1, ESDHC_PAD_CTRL),
|
||||
NEW_PAD_CTRL(VF610_PAD_PTA28__ESDHC1_DAT2, ESDHC_PAD_CTRL),
|
||||
NEW_PAD_CTRL(VF610_PAD_PTA29__ESDHC1_DAT3, ESDHC_PAD_CTRL),
|
||||
};
|
||||
|
||||
esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
|
||||
|
||||
imx_iomux_v3_setup_multiple_pads(
|
||||
esdhc1_pads, ARRAY_SIZE(esdhc1_pads));
|
||||
|
||||
return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
|
||||
}
|
||||
|
||||
static void clock_init(void)
|
||||
{
|
||||
struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
|
||||
struct anadig_reg *anadig = (struct anadig_reg *)ANADIG_BASE_ADDR;
|
||||
|
||||
clrsetbits_le32(&ccm->ccgr0, CCM_REG_CTRL_MASK,
|
||||
CCM_CCGR0_UART1_CTRL_MASK);
|
||||
clrsetbits_le32(&ccm->ccgr1, CCM_REG_CTRL_MASK,
|
||||
CCM_CCGR1_PIT_CTRL_MASK | CCM_CCGR1_WDOGA5_CTRL_MASK);
|
||||
clrsetbits_le32(&ccm->ccgr2, CCM_REG_CTRL_MASK,
|
||||
CCM_CCGR2_IOMUXC_CTRL_MASK | CCM_CCGR2_PORTA_CTRL_MASK |
|
||||
CCM_CCGR2_PORTB_CTRL_MASK | CCM_CCGR2_PORTC_CTRL_MASK |
|
||||
CCM_CCGR2_PORTD_CTRL_MASK | CCM_CCGR2_PORTE_CTRL_MASK |
|
||||
CCM_CCGR2_QSPI0_CTRL_MASK);
|
||||
clrsetbits_le32(&ccm->ccgr3, CCM_REG_CTRL_MASK,
|
||||
CCM_CCGR3_ANADIG_CTRL_MASK | CCM_CCGR3_SCSC_CTRL_MASK);
|
||||
clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK,
|
||||
CCM_CCGR4_WKUP_CTRL_MASK | CCM_CCGR4_CCM_CTRL_MASK |
|
||||
CCM_CCGR4_GPC_CTRL_MASK);
|
||||
clrsetbits_le32(&ccm->ccgr6, CCM_REG_CTRL_MASK,
|
||||
CCM_CCGR6_OCOTP_CTRL_MASK | CCM_CCGR6_DDRMC_CTRL_MASK);
|
||||
clrsetbits_le32(&ccm->ccgr7, CCM_REG_CTRL_MASK,
|
||||
CCM_CCGR7_SDHC1_CTRL_MASK);
|
||||
clrsetbits_le32(&ccm->ccgr9, CCM_REG_CTRL_MASK,
|
||||
CCM_CCGR9_FEC0_CTRL_MASK | CCM_CCGR9_FEC1_CTRL_MASK);
|
||||
clrsetbits_le32(&ccm->ccgr10, CCM_REG_CTRL_MASK,
|
||||
CCM_CCGR10_NFC_CTRL_MASK | CCM_CCGR10_I2C2_CTRL_MASK);
|
||||
|
||||
clrsetbits_le32(&anadig->pll2_ctrl, ANADIG_PLL2_CTRL_POWERDOWN,
|
||||
ANADIG_PLL2_CTRL_ENABLE | ANADIG_PLL2_CTRL_DIV_SELECT);
|
||||
clrsetbits_le32(&anadig->pll1_ctrl, ANADIG_PLL1_CTRL_POWERDOWN,
|
||||
ANADIG_PLL1_CTRL_ENABLE | ANADIG_PLL1_CTRL_DIV_SELECT);
|
||||
|
||||
clrsetbits_le32(&ccm->ccr, CCM_CCR_OSCNT_MASK,
|
||||
CCM_CCR_FIRC_EN | CCM_CCR_OSCNT(5));
|
||||
clrsetbits_le32(&ccm->ccsr, CCM_REG_CTRL_MASK,
|
||||
CCM_CCSR_PLL1_PFD_CLK_SEL(3) | CCM_CCSR_PLL2_PFD4_EN |
|
||||
CCM_CCSR_PLL2_PFD3_EN | CCM_CCSR_PLL2_PFD2_EN |
|
||||
CCM_CCSR_PLL2_PFD1_EN | CCM_CCSR_PLL1_PFD4_EN |
|
||||
CCM_CCSR_PLL1_PFD3_EN | CCM_CCSR_PLL1_PFD2_EN |
|
||||
CCM_CCSR_PLL1_PFD1_EN | CCM_CCSR_DDRC_CLK_SEL(1) |
|
||||
CCM_CCSR_FAST_CLK_SEL(1) | CCM_CCSR_SYS_CLK_SEL(4));
|
||||
clrsetbits_le32(&ccm->cacrr, CCM_REG_CTRL_MASK,
|
||||
CCM_CACRR_IPG_CLK_DIV(1) | CCM_CACRR_BUS_CLK_DIV(2) |
|
||||
CCM_CACRR_ARM_CLK_DIV(0));
|
||||
clrsetbits_le32(&ccm->cscmr1, CCM_REG_CTRL_MASK,
|
||||
CCM_CSCMR1_ESDHC1_CLK_SEL(3) |
|
||||
CCM_CSCMR1_QSPI0_CLK_SEL(3) |
|
||||
CCM_CSCMR1_NFC_CLK_SEL(0));
|
||||
clrsetbits_le32(&ccm->cscdr1, CCM_REG_CTRL_MASK,
|
||||
CCM_CSCDR1_RMII_CLK_EN);
|
||||
clrsetbits_le32(&ccm->cscdr2, CCM_REG_CTRL_MASK,
|
||||
CCM_CSCDR2_ESDHC1_EN | CCM_CSCDR2_ESDHC1_CLK_DIV(0) |
|
||||
CCM_CSCDR2_NFC_EN);
|
||||
clrsetbits_le32(&ccm->cscdr3, CCM_REG_CTRL_MASK,
|
||||
CCM_CSCDR3_QSPI0_EN | CCM_CSCDR3_QSPI0_DIV(1) |
|
||||
CCM_CSCDR3_QSPI0_X2_DIV(1) |
|
||||
CCM_CSCDR3_QSPI0_X4_DIV(3) |
|
||||
CCM_CSCDR3_NFC_PRE_DIV(5));
|
||||
clrsetbits_le32(&ccm->cscmr2, CCM_REG_CTRL_MASK,
|
||||
CCM_CSCMR2_RMII_CLK_SEL(0));
|
||||
}
|
||||
|
||||
static void mscm_init(void)
|
||||
{
|
||||
struct mscm_ir *mscmir = (struct mscm_ir *)MSCM_IR_BASE_ADDR;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < MSCM_IRSPRC_NUM; i++)
|
||||
writew(MSCM_IRSPRC_CP0_EN, &mscmir->irsprc[i]);
|
||||
}
|
||||
|
||||
int board_phy_config(struct phy_device *phydev)
|
||||
{
|
||||
if (phydev->drv->config)
|
||||
phydev->drv->config(phydev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
clock_init();
|
||||
mscm_init();
|
||||
setup_iomux_uart();
|
||||
setup_iomux_enet();
|
||||
setup_iomux_i2c();
|
||||
setup_iomux_qspi();
|
||||
setup_iomux_nfc();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
struct scsc_reg *scsc = (struct scsc_reg *)SCSC_BASE_ADDR;
|
||||
|
||||
/* address of boot parameters */
|
||||
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
|
||||
|
||||
/*
|
||||
* Enable external 32K Oscillator
|
||||
*
|
||||
* The internal clock experiences significant drift
|
||||
* so we must use the external oscillator in order
|
||||
* to maintain correct time in the hwclock
|
||||
*/
|
||||
setbits_le32(&scsc->sosc_ctr, SCSC_SOSC_CTR_SOSC_EN);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int checkboard(void)
|
||||
{
|
||||
puts("Board: PCM-052\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
6
configs/pcm052_defconfig
Normal file
6
configs/pcm052_defconfig
Normal file
@ -0,0 +1,6 @@
|
||||
CONFIG_ARM=y
|
||||
CONFIG_TARGET_PCM052=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/phytec/pcm052/imximage.cfg,ENV_IS_IN_NAND"
|
||||
CONFIG_NAND_VF610_NFC=y
|
||||
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
|
||||
CONFIG_SYS_NAND_VF610_NFC_45_ECC_BYTES=y
|
||||
231
include/configs/pcm052.h
Normal file
231
include/configs/pcm052.h
Normal file
@ -0,0 +1,231 @@
|
||||
/*
|
||||
* Copyright 2013 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* Configuration settings for the phytec PCM-052 SoM.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
#include <asm/arch/imx-regs.h>
|
||||
|
||||
#define CONFIG_VF610
|
||||
|
||||
#define CONFIG_SYS_GENERIC_BOARD
|
||||
#define CONFIG_DISPLAY_CPUINFO
|
||||
#define CONFIG_DISPLAY_BOARDINFO
|
||||
#define CONFIG_SYS_THUMB_BUILD
|
||||
|
||||
#define CONFIG_SKIP_LOWLEVEL_INIT
|
||||
|
||||
/* Enable passing of ATAGs */
|
||||
#define CONFIG_CMDLINE_TAG
|
||||
|
||||
/* Size of malloc() pool */
|
||||
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
|
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F
|
||||
|
||||
#define CONFIG_FSL_LPUART
|
||||
#define LPUART_BASE UART1_BASE
|
||||
|
||||
/* Allow to overwrite serial and ethaddr */
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
#define CONFIG_SYS_UART_PORT (1)
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
|
||||
#undef CONFIG_CMD_IMLS
|
||||
|
||||
/* NAND support */
|
||||
#define CONFIG_CMD_NAND
|
||||
#define CONFIG_CMD_NAND_TRIMFFS
|
||||
#define CONFIG_SYS_NAND_ONFI_DETECTION
|
||||
|
||||
#ifdef CONFIG_CMD_NAND
|
||||
#define CONFIG_USE_ARCH_MEMCPY
|
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1
|
||||
#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR
|
||||
|
||||
#define CONFIG_JFFS2_NAND
|
||||
|
||||
/* UBI */
|
||||
#define CONFIG_CMD_UBI
|
||||
#define CONFIG_CMD_UBIFS
|
||||
#define CONFIG_RBTREE
|
||||
#define CONFIG_LZO
|
||||
|
||||
/* Dynamic MTD partition support */
|
||||
#define CONFIG_CMD_MTDPARTS
|
||||
#define CONFIG_MTD_PARTITIONS
|
||||
#define CONFIG_MTD_DEVICE
|
||||
#define MTDIDS_DEFAULT "nand0=NAND,nor0=qspi0-a,nor1=qspi0-b"
|
||||
#define MTDPARTS_DEFAULT "mtdparts=NAND:256k(spare)"\
|
||||
",384k(bootloader)"\
|
||||
",128k(env1)"\
|
||||
",128k(env2)"\
|
||||
",3840k(kernel)"\
|
||||
",-(rootfs)"\
|
||||
",qspi0-a:-(jffs2),qspio0-b:-(jffs2)"
|
||||
#endif
|
||||
|
||||
#define CONFIG_MMC
|
||||
#define CONFIG_FSL_ESDHC
|
||||
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
|
||||
#define CONFIG_SYS_FSL_ESDHC_NUM 1
|
||||
|
||||
/*#define CONFIG_ESDHC_DETECT_USE_EXTERN_IRQ1*/
|
||||
#define CONFIG_SYS_FSL_ERRATUM_ESDHC135
|
||||
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
|
||||
#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
|
||||
|
||||
#define CONFIG_CMD_MMC
|
||||
#define CONFIG_GENERIC_MMC
|
||||
#define CONFIG_CMD_FAT
|
||||
#define CONFIG_DOS_PARTITION
|
||||
|
||||
#define CONFIG_CMD_PING
|
||||
#define CONFIG_CMD_DHCP
|
||||
#define CONFIG_CMD_MII
|
||||
#define CONFIG_FEC_MXC
|
||||
#define CONFIG_MII
|
||||
#define IMX_FEC_BASE ENET_BASE_ADDR
|
||||
#define CONFIG_FEC_XCV_TYPE RMII
|
||||
#define CONFIG_FEC_MXC_PHYADDR 0
|
||||
#define CONFIG_PHYLIB
|
||||
#define CONFIG_PHY_MICREL
|
||||
|
||||
/* QSPI Configs*/
|
||||
#define CONFIG_FSL_QSPI
|
||||
|
||||
#ifdef CONFIG_FSL_QSPI
|
||||
#define CONFIG_CMD_SF
|
||||
#define CONFIG_SPI_FLASH
|
||||
#define CONFIG_SPI_FLASH_STMICRO
|
||||
#define FSL_QSPI_FLASH_SIZE (1 << 24)
|
||||
#define FSL_QSPI_FLASH_NUM 2
|
||||
#define CONFIG_SYS_FSL_QSPI_LE
|
||||
#endif
|
||||
|
||||
/* I2C Configs */
|
||||
#define CONFIG_CMD_I2C
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_MXC_I2C3
|
||||
#define CONFIG_SYS_I2C_MXC
|
||||
|
||||
/* RTC (actually an RV-4162 but M41T62-compatible) */
|
||||
#define CONFIG_CMD_DATE
|
||||
#define CONFIG_RTC_M41T62
|
||||
#define CONFIG_SYS_I2C_RTC_ADDR 0x68
|
||||
#define CONFIG_SYS_RTC_BUS_NUM 2
|
||||
|
||||
/* EEPROM (24FC256) */
|
||||
#define CONFIG_CMD_EEPROM
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
|
||||
#define CONFIG_SYS_I2C_EEPROM_BUS 2
|
||||
|
||||
#define CONFIG_BOOTDELAY 3
|
||||
|
||||
#define CONFIG_LOADADDR 0x82000000
|
||||
|
||||
/* We boot from the gfxRAM area of the OCRAM. */
|
||||
#define CONFIG_SYS_TEXT_BASE 0x3f408000
|
||||
#define CONFIG_BOARD_SIZE_LIMIT 524288
|
||||
|
||||
#define CONFIG_BOOTCOMMAND "run bootcmd_sd"
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"bootfile=uImage\0" \
|
||||
"bootargs_base=setenv bootargs rw mem=256M " \
|
||||
"console=ttymxc1,115200n8\0" \
|
||||
"bootargs_sd=setenv bootargs ${bootargs} " \
|
||||
"root=/dev/mmcblk0p2 rootwait\0" \
|
||||
"bootargs_net=setenv bootargs ${bootargs} root=/dev/nfs ip=dhcp " \
|
||||
"nfsroot=${serverip}:${nfs_root},v3,tcp\0" \
|
||||
"bootargs_nand=setenv bootargs ${bootargs} " \
|
||||
"root=/dev/mtdblock2 rootfstype=jffs2\0" \
|
||||
"bootargs_mtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
|
||||
"bootcmd_sd=run bootargs_base bootargs_sd bootargs_mtd; mmc rescan; " \
|
||||
"fatload mmc 0:1 ${loadaddr} ${bootfile}; bootm ${loadaddr}\0" \
|
||||
"bootcmd_net=run bootargs_base bootargs_net bootargs_mtd; " \
|
||||
"tftpboot ${loadaddr} ${tftploc}${bootfile}; bootm\0" \
|
||||
"bootcmd_nand='run bootargs_base bootargs_nand bootargs_mtd; " \
|
||||
"nand read ${loadaddr} 0x000E0000 0x3C0000; " \
|
||||
"bootm ${loadaddr}\0" \
|
||||
"tftploc=/path/to/tftp/directory/\0" \
|
||||
"nfs_root=/path/to/nfs/root\0" \
|
||||
"mtdparts=" MTDPARTS_DEFAULT "\0" \
|
||||
"update_kernel_from_sd=mw.b $(loadaddr) 0xff 0x3C0000; " \
|
||||
"mmc rescan; fatload mmc 0:2 ${loadaddr} ${bootfile}; " \
|
||||
"nand erase 0xE0000 0x3C0000; " \
|
||||
"nand write.i ${loadaddr} 0xE0000 0x3C0000\0" \
|
||||
"update_rootfs_from_tftp=mw.b ${loadaddr} 0xff 0x8F20000; " \
|
||||
"tftp ${loadaddr} ${tftp}${filesys}; " \
|
||||
"nand erase 0x4A0000 0x8F20000; " \
|
||||
"nand write.i ${loadaddr} 0x4A0000 0x8F20000\0" \
|
||||
"filesys=rootfs.jffs2\0"
|
||||
|
||||
/* miscellaneous commands */
|
||||
#define CONFIG_CMD_ELF
|
||||
|
||||
/* Miscellaneous configurable options */
|
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */
|
||||
#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
|
||||
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
|
||||
#define CONFIG_AUTO_COMPLETE
|
||||
#define CONFIG_CMDLINE_EDITING
|
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#define CONFIG_SYS_PBSIZE \
|
||||
(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
|
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
|
||||
|
||||
#define CONFIG_CMD_MEMTEST
|
||||
#define CONFIG_SYS_MEMTEST_START 0x80010000
|
||||
#define CONFIG_SYS_MEMTEST_END 0x87C00000
|
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
|
||||
|
||||
/*
|
||||
* Stack sizes
|
||||
* The stack sizes are set up in start.S using the settings below
|
||||
*/
|
||||
#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
|
||||
|
||||
/* Physical memory map */
|
||||
#define CONFIG_NR_DRAM_BANKS 1
|
||||
#define PHYS_SDRAM (0x80000000)
|
||||
#define PHYS_SDRAM_SIZE (256 * 1024 * 1024)
|
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
|
||||
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET \
|
||||
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_ADDR \
|
||||
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
|
||||
|
||||
/* FLASH and environment organization */
|
||||
#define CONFIG_SYS_NO_FLASH
|
||||
|
||||
#ifdef CONFIG_ENV_IS_IN_MMC
|
||||
#define CONFIG_ENV_SIZE (8 * 1024)
|
||||
|
||||
#define CONFIG_ENV_OFFSET (12 * 64 * 1024)
|
||||
#define CONFIG_SYS_MMC_ENV_DEV 0
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ENV_IS_IN_NAND
|
||||
#define CONFIG_ENV_SECT_SIZE (128 * 1024)
|
||||
#define CONFIG_ENV_SIZE (8 * 1024)
|
||||
#define CONFIG_ENV_OFFSET 0x80000
|
||||
#define CONFIG_ENV_SIZE_REDUND (8 * 1024)
|
||||
#define CONFIG_ENV_OFFSET_REDUND 0xA0000
|
||||
#endif
|
||||
|
||||
#define CONFIG_OF_LIBFDT
|
||||
#define CONFIG_CMD_BOOTZ
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user