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ARM: DRA7xx: EMIF: Change settings required for EVM board

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DRA7 EVM board has the below configuration. Adding the
settings for the same here.

   2Gb_1_35V_DDR3L part * 2 on EMIF1
   2Gb_1_35V_DDR3L part * 4 on EMIF2

Signed-off-by: Sricharan R <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
This commit is contained in:
Sricharan R 2013-05-30 03:19:39 +00:00 committed by Tom Rini
parent 97405d843e
commit 92b0482c17
8 changed files with 221 additions and 32 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

26
arch/arm/cpu/armv7/omap-common/emif-common.c
View File

@ -209,7 +209,8 @@ void emif_update_timings(u32 base, const struct emif_regs *regs)
writel(regs->temp_alert_config, &emif->emif_temp_alert_config);
writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw);
if (omap_revision() >= OMAP5430_ES1_0) {
if ((omap_revision() >= OMAP5430_ES1_0) ||
(omap_revision() == DRA752_ES1_0)) {
writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_5_LL_0,
&emif->emif_l3_config);
} else if (omap_revision() >= OMAP4460_ES1_0) {
@ -263,6 +264,18 @@ static void ddr3_leveling(u32 base, const struct emif_regs *regs)
__udelay(130);
}
static void ddr3_sw_leveling(u32 base, const struct emif_regs *regs)
{
struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1);
writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw);
config_data_eye_leveling_samples(base);
writel(regs->emif_rd_wr_lvl_ctl, &emif->emif_rd_wr_lvl_ctl);
writel(regs->sdram_config, &emif->emif_sdram_config);
}
static void ddr3_init(u32 base, const struct emif_regs *regs)
{
struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
@ -273,6 +286,7 @@ static void ddr3_init(u32 base, const struct emif_regs *regs)
* defined, contents of mode Registers must be fully initialized.
* H/W takes care of this initialization
*/
writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config);
writel(regs->sdram_config_init, &emif->emif_sdram_config);
writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1);
@ -290,7 +304,10 @@ static void ddr3_init(u32 base, const struct emif_regs *regs)
/* enable leveling */
writel(regs->emif_rd_wr_lvl_rmp_ctl, &emif->emif_rd_wr_lvl_rmp_ctl);
ddr3_leveling(base, regs);
if (omap_revision() == DRA752_ES1_0)
ddr3_sw_leveling(base, regs);
else
ddr3_leveling(base, regs);
}
#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
@ -1078,7 +1095,10 @@ static void do_sdram_init(u32 base)
if (warm_reset() && (emif_sdram_type() == EMIF_SDRAM_TYPE_DDR3)) {
set_lpmode_selfrefresh(base);
emif_reset_phy(base);
ddr3_leveling(base, regs);
if (omap_revision() == DRA752_ES1_0)
ddr3_sw_leveling(base, regs);
else
ddr3_leveling(base, regs);
}
/* Write to the shadow registers */

21
arch/arm/cpu/armv7/omap5/hw_data.c
View File

@ -602,6 +602,17 @@ const struct ctrl_ioregs ioregs_omap5432_es2 = {
.ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES,
};
const struct ctrl_ioregs ioregs_dra7xx_es1 = {
.ctrl_ddrch = 0x40404040,
.ctrl_lpddr2ch = 0x40404040,
.ctrl_ddr3ch = 0x80808080,
.ctrl_ddrio_0 = 0xbae8c631,
.ctrl_ddrio_1 = 0xb46318d8,
.ctrl_ddrio_2 = 0x84210000,
.ctrl_emif_sdram_config_ext = 0xb2c00000,
.ctrl_ddr_ctrl_ext_0 = 0xA2000000,
};
void hw_data_init(void)
{
u32 omap_rev = omap_revision();
@ -644,14 +655,16 @@ void get_ioregs(const struct ctrl_ioregs **regs)
case OMAP5430_ES1_0:
case OMAP5430_ES2_0:
*regs = &ioregs_omap5430;
break;
break;
case OMAP5432_ES1_0:
*regs = &ioregs_omap5432_es1;
break;
break;
case OMAP5432_ES2_0:
case DRA752_ES1_0:
*regs = &ioregs_omap5432_es2;
break;
break;
case DRA752_ES1_0:
*regs = &ioregs_dra7xx_es1;
break;
default:
printf("\n INVALID OMAP REVISION ");

19
arch/arm/cpu/armv7/omap5/hwinit.c
View File

@ -100,16 +100,21 @@ static void io_settings_ddr3(void)
writel(ioregs->ctrl_emif_sdram_config_ext,
(*ctrl)->control_emif2_sdram_config_ext);
/* Disable DLL select */
io_settings = (readl((*ctrl)->control_port_emif1_sdram_config)
if (is_omap54xx()) {
/* Disable DLL select */
io_settings = (readl((*ctrl)->control_port_emif1_sdram_config)
& 0xFFEFFFFF);
writel(io_settings,
(*ctrl)->control_port_emif1_sdram_config);
writel(io_settings,
(*ctrl)->control_port_emif1_sdram_config);
io_settings = (readl((*ctrl)->control_port_emif2_sdram_config)
io_settings = (readl((*ctrl)->control_port_emif2_sdram_config)
& 0xFFEFFFFF);
writel(io_settings,
(*ctrl)->control_port_emif2_sdram_config);
writel(io_settings,
(*ctrl)->control_port_emif2_sdram_config);
} else {
writel(ioregs->ctrl_ddr_ctrl_ext_0,
(*ctrl)->control_ddr_control_ext_0);
}
}
/*

1
arch/arm/cpu/armv7/omap5/prcm-regs.c
View File

@ -439,6 +439,7 @@ struct omap_sys_ctrl_regs const dra7xx_ctrl = {
.control_srcomp_east_side = 0x4A002E7C,
.control_srcomp_west_side = 0x4A002E80,
.control_srcomp_code_latch = 0x4A002E84,
.control_ddr_control_ext_0 = 0x4A002E88,
.control_padconf_core_base = 0x4A003400,
.control_port_emif1_sdram_config = 0x4AE0C110,
.control_port_emif1_lpddr2_nvm_config = 0x4AE0C114,

172
arch/arm/cpu/armv7/omap5/sdram.c
View File

@ -108,6 +108,7 @@ const struct emif_regs emif_regs_266_mhz_2cs = {
const struct emif_regs emif_regs_ddr3_532_mhz_1cs = {
.sdram_config_init = 0x61851B32,
.sdram_config = 0x61851B32,
.sdram_config2 = 0x0,
.ref_ctrl = 0x00001035,
.sdram_tim1 = 0xCCCF36B3,
.sdram_tim2 = 0x308F7FDA,
@ -131,6 +132,7 @@ const struct emif_regs emif_regs_ddr3_532_mhz_1cs = {
const struct emif_regs emif_regs_ddr3_532_mhz_1cs_es2 = {
.sdram_config_init = 0x61851B32,
.sdram_config = 0x61851B32,
.sdram_config2 = 0x0,
.ref_ctrl = 0x00001035,
.sdram_tim1 = 0xCCCF36B3,
.sdram_tim2 = 0x308F7FDA,
@ -151,6 +153,54 @@ const struct emif_regs emif_regs_ddr3_532_mhz_1cs_es2 = {
.emif_rd_wr_exec_thresh = 0x40000305
};
const struct emif_regs emif_1_regs_ddr3_532_mhz_1cs_dra_es1 = {
.sdram_config_init = 0x61851ab2,
.sdram_config = 0x61851ab2,
.sdram_config2 = 0x08000000,
.ref_ctrl = 0x00001035,
.sdram_tim1 = 0xCCCF36B3,
.sdram_tim2 = 0x308F7FDA,
.sdram_tim3 = 0x027F88A8,
.read_idle_ctrl = 0x00050000,
.zq_config = 0x0007190B,
.temp_alert_config = 0x00000000,
.emif_ddr_phy_ctlr_1_init = 0x0E20400A,
.emif_ddr_phy_ctlr_1 = 0x0E24400A,
.emif_ddr_ext_phy_ctrl_1 = 0x04040100,
.emif_ddr_ext_phy_ctrl_2 = 0x009E009E,
.emif_ddr_ext_phy_ctrl_3 = 0x009E009E,
.emif_ddr_ext_phy_ctrl_4 = 0x009E009E,
.emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
.emif_rd_wr_lvl_rmp_win = 0x00000000,
.emif_rd_wr_lvl_rmp_ctl = 0x80000000,
.emif_rd_wr_lvl_ctl = 0x00000000,
.emif_rd_wr_exec_thresh = 0x00000305
};
const struct emif_regs emif_2_regs_ddr3_532_mhz_1cs_dra_es1 = {
.sdram_config_init = 0x61851B32,
.sdram_config = 0x61851B32,
.sdram_config2 = 0x08000000,
.ref_ctrl = 0x00001035,
.sdram_tim1 = 0xCCCF36B3,
.sdram_tim2 = 0x308F7FDA,
.sdram_tim3 = 0x027F88A8,
.read_idle_ctrl = 0x00050000,
.zq_config = 0x0007190B,
.temp_alert_config = 0x00000000,
.emif_ddr_phy_ctlr_1_init = 0x0020400A,
.emif_ddr_phy_ctlr_1 = 0x0E24400A,
.emif_ddr_ext_phy_ctrl_1 = 0x04040100,
.emif_ddr_ext_phy_ctrl_2 = 0x009D009D,
.emif_ddr_ext_phy_ctrl_3 = 0x009D009D,
.emif_ddr_ext_phy_ctrl_4 = 0x009D009D,
.emif_ddr_ext_phy_ctrl_5 = 0x009D009D,
.emif_rd_wr_lvl_rmp_win = 0x00000000,
.emif_rd_wr_lvl_rmp_ctl = 0x80000000,
.emif_rd_wr_lvl_ctl = 0x00000000,
.emif_rd_wr_exec_thresh = 0x00000305
};
const struct dmm_lisa_map_regs lisa_map_4G_x_2_x_2 = {
.dmm_lisa_map_0 = 0x0,
.dmm_lisa_map_1 = 0x0,
@ -159,11 +209,39 @@ const struct dmm_lisa_map_regs lisa_map_4G_x_2_x_2 = {
.is_ma_present = 0x1
};
const struct dmm_lisa_map_regs lisa_map_512M_x_1 = {
/*
* DRA752 EVM board has 1.5 GB of memory
* EMIF1 --> 2Gb * 2 = 512MB
* EMIF2 --> 2Gb * 4 = 1GB
* so mapping 1GB interleaved and 512MB non-interleaved
*/
const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2_2G_x_1_x_2 = {
.dmm_lisa_map_0 = 0x0,
.dmm_lisa_map_1 = 0x80640300,
.dmm_lisa_map_2 = 0xC0500220,
.dmm_lisa_map_3 = 0xFF020100,
.is_ma_present = 0x1
};
/*
* DRA752 EVM EMIF1 ONLY CONFIGURATION
*/
const struct dmm_lisa_map_regs lisa_map_2G_x_1_x_2 = {
.dmm_lisa_map_0 = 0x0,
.dmm_lisa_map_1 = 0x0,
.dmm_lisa_map_2 = 0x0,
.dmm_lisa_map_3 = 0x80500100,
.dmm_lisa_map_2 = 0x80500100,
.dmm_lisa_map_3 = 0xFF020100,
.is_ma_present = 0x1
};
/*
* DRA752 EVM EMIF2 ONLY CONFIGURATION
*/
const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2 = {
.dmm_lisa_map_0 = 0x0,
.dmm_lisa_map_1 = 0x0,
.dmm_lisa_map_2 = 0x80600200,
.dmm_lisa_map_3 = 0xFF020100,
.is_ma_present = 0x1
};
@ -180,9 +258,20 @@ static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs)
*regs = &emif_regs_532_mhz_2cs_es2;
break;
case OMAP5432_ES2_0:
case DRA752_ES1_0:
default:
*regs = &emif_regs_ddr3_532_mhz_1cs_es2;
break;
case DRA752_ES1_0:
switch (emif_nr) {
case 1:
*regs = &emif_1_regs_ddr3_532_mhz_1cs_dra_es1;
break;
case 2:
*regs = &emif_2_regs_ddr3_532_mhz_1cs_dra_es1;
break;
}
break;
default:
*regs = &emif_1_regs_ddr3_532_mhz_1cs_dra_es1;
}
}
@ -201,7 +290,7 @@ static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs
break;
case DRA752_ES1_0:
default:
*dmm_lisa_regs = &lisa_map_512M_x_1;
*dmm_lisa_regs = &lisa_map_2G_x_2_x_2_2G_x_1_x_2;
}
}
@ -252,7 +341,8 @@ const u32 ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG] = {
0x00000000,
0x00000000,
0x00000000,
0x00000077
0x00000077,
0x0
};
const u32 ddr3_ext_phy_ctrl_const_base_es1[EMIF_EXT_PHY_CTRL_CONST_REG] = {
@ -274,7 +364,8 @@ const u32 ddr3_ext_phy_ctrl_const_base_es1[EMIF_EXT_PHY_CTRL_CONST_REG] = {
0x00000000,
0x00000000,
0x00000000,
0x00000057
0x00000057,
0x0
};
const u32 ddr3_ext_phy_ctrl_const_base_es2[EMIF_EXT_PHY_CTRL_CONST_REG] = {
@ -296,7 +387,56 @@ const u32 ddr3_ext_phy_ctrl_const_base_es2[EMIF_EXT_PHY_CTRL_CONST_REG] = {
0x00000000,
0x00000000,
0x00000000,
0x00000057
0x00000057,
0x0
};
const u32
dra_ddr3_ext_phy_ctrl_const_base_es1_emif1[EMIF_EXT_PHY_CTRL_CONST_REG] = {
0x009E009E,
0x002E002E,
0x002E002E,
0x002E002E,
0x002E002E,
0x002E002E,
0x004D004D,
0x004D004D,
0x004D004D,
0x004D004D,
0x004D004D,
0x004D004D,
0x004D004D,
0x004D004D,
0x004D004D,
0x004D004D,
0x0,
0x600020,
0x40010080,
0x8102040
};
const u32
dra_ddr3_ext_phy_ctrl_const_base_es1_emif2[EMIF_EXT_PHY_CTRL_CONST_REG] = {
0x009D009D,
0x002D002D,
0x002D002D,
0x002D002D,
0x002D002D,
0x002D002D,
0x00570057,
0x00570057,
0x00570057,
0x00570057,
0x00570057,
0x00570057,
0x00570057,
0x00570057,
0x00570057,
0x00570057,
0x0,
0x600020,
0x40010080,
0x8102040
};
const struct lpddr2_mr_regs mr_regs = {
@ -307,7 +447,7 @@ const struct lpddr2_mr_regs mr_regs = {
.mr16 = MR16_REF_FULL_ARRAY
};
static void emif_get_ext_phy_ctrl_const_regs(const u32 **regs)
static void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs)
{
switch (omap_revision()) {
case OMAP5430_ES1_0:
@ -318,7 +458,14 @@ static void emif_get_ext_phy_ctrl_const_regs(const u32 **regs)
*regs = ddr3_ext_phy_ctrl_const_base_es1;
break;
case OMAP5432_ES2_0:
*regs = ddr3_ext_phy_ctrl_const_base_es2;
break;
case DRA752_ES1_0:
if (emif_nr == 1)
*regs = dra_ddr3_ext_phy_ctrl_const_base_es1_emif1;
else
*regs = dra_ddr3_ext_phy_ctrl_const_base_es1_emif2;
break;
default:
*regs = ddr3_ext_phy_ctrl_const_base_es2;
@ -334,9 +481,12 @@ void do_ext_phy_settings(u32 base, const struct emif_regs *regs)
{
u32 *ext_phy_ctrl_base = 0;
u32 *emif_ext_phy_ctrl_base = 0;
u32 emif_nr;
const u32 *ext_phy_ctrl_const_regs;
u32 i = 0;
emif_nr = (base == EMIF1_BASE) ? 1 : 2;
struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
ext_phy_ctrl_base = (u32 *) &(regs->emif_ddr_ext_phy_ctrl_1);
@ -353,7 +503,7 @@ void do_ext_phy_settings(u32 base, const struct emif_regs *regs)
* external phy 6-24 registers do not change with
* ddr frequency
*/
emif_get_ext_phy_ctrl_const_regs(&ext_phy_ctrl_const_regs);
emif_get_ext_phy_ctrl_const_regs(emif_nr, &ext_phy_ctrl_const_regs);
for (i = 0; i < EMIF_EXT_PHY_CTRL_CONST_REG; i++) {
writel(ext_phy_ctrl_const_regs[i],
emif_ext_phy_ctrl_base++);

1
arch/arm/include/asm/arch-omap5/omap.h
View File

@ -221,6 +221,7 @@ struct ctrl_ioregs {
u32 ctrl_ddrio_1;
u32 ctrl_ddrio_2;
u32 ctrl_emif_sdram_config_ext;
u32 ctrl_ddr_ctrl_ext_0;
};
#endif /* __ASSEMBLY__ */
#endif

12
arch/arm/include/asm/emif.h
View File

@ -581,7 +581,7 @@
(0xFF << EMIF_SYS_ADDR_SHIFT))
#define EMIF_EXT_PHY_CTRL_TIMING_REG 0x5
#define EMIF_EXT_PHY_CTRL_CONST_REG 0x13
#define EMIF_EXT_PHY_CTRL_CONST_REG 0x14
/* Reg mapping structure */
struct emif_reg_struct {
@ -855,13 +855,10 @@ struct dmm_lisa_map_regs {
#define DPD_ENABLE 1
/* Maximum delay before Low Power Modes */
#ifndef CONFIG_OMAP54XX
#define REG_CS_TIM 0xF
#else
#define REG_CS_TIM 0x0
#endif
#define REG_SR_TIM 0xF
#define REG_PD_TIM 0xF
#define REG_SR_TIM 0x0
#define REG_PD_TIM 0x0
/* EMIF_PWR_MGMT_CTRL register */
#define EMIF_PWR_MGMT_CTRL (\
@ -1113,6 +1110,7 @@ struct emif_regs {
u32 freq;
u32 sdram_config_init;
u32 sdram_config;
u32 sdram_config2;
u32 ref_ctrl;
u32 sdram_tim1;
u32 sdram_tim2;

1
arch/arm/include/asm/omap_common.h
View File

@ -401,6 +401,7 @@ struct omap_sys_ctrl_regs {
u32 control_ddrio_0;
u32 control_ddrio_1;
u32 control_ddrio_2;
u32 control_ddr_control_ext_0;
u32 control_lpddr2io1_0;
u32 control_lpddr2io1_1;
u32 control_lpddr2io1_2;