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ppc: Move fpga_state to arch_global_data

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Move this field into arch_global_data and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Simon Glass 2012-12-13 20:49:02 +00:00 committed by Tom Rini
parent 7273ccec61
commit 923a662f2f
4 changed files with 19 additions and 17 deletions
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6
arch/powerpc/include/asm/global_data.h
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@ -122,6 +122,9 @@ struct arch_global_data {
#if defined(CONFIG_SYS_GT_6426x) #if defined(CONFIG_SYS_GT_6426x)
unsigned int mirror_hack[16]; unsigned int mirror_hack[16];
#endif #endif
#ifdef CONFIG_SYS_FPGA_COUNT
unsigned fpga_state[CONFIG_SYS_FPGA_COUNT];
#endif
}; };
/* /*
@ -170,9 +173,6 @@ typedef struct global_data {
#if defined(CONFIG_LWMON) || defined(CONFIG_LWMON5) #if defined(CONFIG_LWMON) || defined(CONFIG_LWMON5)
unsigned long kbd_status; unsigned long kbd_status;
#endif #endif
#ifdef CONFIG_SYS_FPGA_COUNT
unsigned fpga_state[CONFIG_SYS_FPGA_COUNT];
#endif
#if defined(CONFIG_WD_MAX_RATE) #if defined(CONFIG_WD_MAX_RATE)
unsigned long long wdt_last; /* trace watch-dog triggering rate */ unsigned long long wdt_last; /* trace watch-dog triggering rate */
#endif #endif

15
board/gdsys/405ep/405ep.c
View File

@ -38,14 +38,14 @@ DECLARE_GLOBAL_DATA_PTR;
int get_fpga_state(unsigned dev) int get_fpga_state(unsigned dev)
{ {
return gd->fpga_state[dev]; return gd->arch.fpga_state[dev];
} }
void print_fpga_state(unsigned dev) void print_fpga_state(unsigned dev)
{ {
if (gd->fpga_state[dev] & FPGA_STATE_DONE_FAILED) if (gd->arch.fpga_state[dev] & FPGA_STATE_DONE_FAILED)
puts(" Waiting for FPGA-DONE timed out.\n"); puts(" Waiting for FPGA-DONE timed out.\n");
if (gd->fpga_state[dev] & FPGA_STATE_REFLECTION_FAILED) if (gd->arch.fpga_state[dev] & FPGA_STATE_REFLECTION_FAILED)
puts(" FPGA reflection test failed.\n"); puts(" FPGA reflection test failed.\n");
} }
@ -54,7 +54,7 @@ int board_early_init_f(void)
unsigned k; unsigned k;
for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
gd->fpga_state[k] = 0; gd->arch.fpga_state[k] = 0;
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0ER, 0x00000000); /* disable all ints */ mtdcr(UIC0ER, 0x00000000); /* disable all ints */
@ -78,7 +78,7 @@ int board_early_init_r(void)
unsigned ctr; unsigned ctr;
for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
gd->fpga_state[k] = 0; gd->arch.fpga_state[k] = 0;
/* /*
* reset FPGA * reset FPGA
@ -94,7 +94,8 @@ int board_early_init_r(void)
while (!gd405ep_get_fpga_done(k)) { while (!gd405ep_get_fpga_done(k)) {
udelay(100000); udelay(100000);
if (ctr++ > 5) { if (ctr++ > 5) {
gd->fpga_state[k] |= FPGA_STATE_DONE_FAILED; gd->arch.fpga_state[k] |=
FPGA_STATE_DONE_FAILED;
break; break;
} }
} }
@ -126,7 +127,7 @@ int board_early_init_r(void)
udelay(100000); udelay(100000);
if (ctr++ > 5) { if (ctr++ > 5) {
gd->fpga_state[k] |= gd->arch.fpga_state[k] |=
FPGA_STATE_REFLECTION_FAILED; FPGA_STATE_REFLECTION_FAILED;
break; break;
} }

13
board/gdsys/405ex/405ex.c
View File

@ -15,14 +15,14 @@ DECLARE_GLOBAL_DATA_PTR;
int get_fpga_state(unsigned dev) int get_fpga_state(unsigned dev)
{ {
return gd->fpga_state[dev]; return gd->arch.fpga_state[dev];
} }
void print_fpga_state(unsigned dev) void print_fpga_state(unsigned dev)
{ {
if (gd->fpga_state[dev] & FPGA_STATE_DONE_FAILED) if (gd->arch.fpga_state[dev] & FPGA_STATE_DONE_FAILED)
puts(" Waiting for FPGA-DONE timed out.\n"); puts(" Waiting for FPGA-DONE timed out.\n");
if (gd->fpga_state[dev] & FPGA_STATE_REFLECTION_FAILED) if (gd->arch.fpga_state[dev] & FPGA_STATE_REFLECTION_FAILED)
puts(" FPGA reflection test failed.\n"); puts(" FPGA reflection test failed.\n");
} }
@ -192,7 +192,7 @@ int board_early_init_r(void)
unsigned ctr; unsigned ctr;
for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
gd->fpga_state[k] = 0; gd->arch.fpga_state[k] = 0;
/* /*
* reset FPGA * reset FPGA
@ -208,7 +208,8 @@ int board_early_init_r(void)
while (!gd405ex_get_fpga_done(k)) { while (!gd405ex_get_fpga_done(k)) {
udelay(100000); udelay(100000);
if (ctr++ > 5) { if (ctr++ > 5) {
gd->fpga_state[k] |= FPGA_STATE_DONE_FAILED; gd->arch.fpga_state[k] |=
FPGA_STATE_DONE_FAILED;
break; break;
} }
} }
@ -240,7 +241,7 @@ int board_early_init_r(void)
udelay(100000); udelay(100000);
if (ctr++ > 5) { if (ctr++ > 5) {
gd->fpga_state[k] |= gd->arch.fpga_state[k] |=
FPGA_STATE_REFLECTION_FAILED; FPGA_STATE_REFLECTION_FAILED;
break; break;
} }

2
board/gdsys/405ex/io64.c
View File

@ -359,7 +359,7 @@ void gd405ex_init(void)
if (i2c_probe(0x22)) { /* i2c_probe returns 0 on success */ if (i2c_probe(0x22)) { /* i2c_probe returns 0 on success */
for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
gd->fpga_state[k] |= FPGA_STATE_PLATFORM; gd->arch.fpga_state[k] |= FPGA_STATE_PLATFORM;
} else { } else {
pca9698_direction_output(0x22, 39, 1); pca9698_direction_output(0x22, 39, 1);
} }