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Xilinx changes for v2018.01-rc2-v2

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fpga:
 - Enable loading bitstream via fit image for !xilinx platforms
 
 zynq:
 - Fix SPL SD boot mode
 
 zynqmp:
 - Not not reset in panic
 - Do not use simple allocator because of fat changes
 - Various dt chagnes
 - modeboot variable setup
 - Fix fpga loading on automotive devices
 - Fix coverity issues
 
 test:
 - Fix env test for !hush case - Stephen's patch
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Merge tag 'xilinx-for-v2018.01-rc2-v2' of git://www.denx.de/git/u-boot-microblaze

Xilinx changes for v2018.01-rc2-v2

fpga:
- Enable loading bitstream via fit image for !xilinx platforms

zynq:
- Fix SPL SD boot mode

zynqmp:
- Not not reset in panic
- Do not use simple allocator because of fat changes
- Various dt chagnes
- modeboot variable setup
- Fix fpga loading on automotive devices
- Fix coverity issues

test:
- Fix env test for !hush case - Stephen's patch
This commit is contained in:
Tom Rini 2017-12-18 12:23:27 -05:00
commit 90d75d2efc
44 changed files with 212 additions and 81 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm/Kconfig
View File

@ -773,7 +773,7 @@ config ARCH_ZYNQMP
select SUPPORT_SPL
select CLK
select SPL_BOARD_INIT if SPL
select SPL_CLK
select SPL_CLK if SPL
select DM_USB if USB
imply FAT_WRITE

4
arch/arm/dts/zynqmp-ep108.dts
View File

@ -65,7 +65,7 @@
status = "okay";
clock-frequency = <400000>;
eeprom@54 {
compatible = "at,24c64";
compatible = "atmel,24c64";
reg = <0x54>;
};
};
@ -74,7 +74,7 @@
status = "okay";
clock-frequency = <400000>;
eeprom@55 {
compatible = "at,24c64";
compatible = "atmel,24c64";
reg = <0x55>;
};
};

9
arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts
View File

@ -43,16 +43,10 @@
/* fpd_dma clk 667MHz, lpd_dma 500MHz */
&fpd_dma_chan1 {
status = "okay";
xlnx,include-sg; /* for testing purpose */
xlnx,overfetch; /* for testing purpose */
xlnx,ratectrl = <0>; /* for testing purpose */
xlnx,src-issue = <31>;
};
&fpd_dma_chan2 {
status = "okay";
xlnx,ratectrl = <100>; /* for testing purpose */
xlnx,src-issue = <4>; /* for testing purpose */
};
&fpd_dma_chan3 {
@ -61,7 +55,6 @@
&fpd_dma_chan4 {
status = "okay";
xlnx,include-sg; /* for testing purpose */
};
&fpd_dma_chan5 {
@ -70,7 +63,6 @@
&fpd_dma_chan6 {
status = "okay";
xlnx,include-sg; /* for testing purpose */
};
&fpd_dma_chan7 {
@ -79,7 +71,6 @@
&fpd_dma_chan8 {
status = "okay";
xlnx,include-sg; /* for testing purpose */
};
&gem3 {

9
arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts
View File

@ -53,16 +53,10 @@
/* fpd_dma clk 667MHz, lpd_dma 500MHz */
&fpd_dma_chan1 {
status = "okay";
xlnx,include-sg; /* for testing purpose */
xlnx,overfetch; /* for testing purpose */
xlnx,ratectrl = <0>; /* for testing purpose */
xlnx,src-issue = <31>;
};
&fpd_dma_chan2 {
status = "okay";
xlnx,ratectrl = <100>; /* for testing purpose */
xlnx,src-issue = <4>; /* for testing purpose */
};
&fpd_dma_chan3 {
@ -71,7 +65,6 @@
&fpd_dma_chan4 {
status = "okay";
xlnx,include-sg; /* for testing purpose */
};
&fpd_dma_chan5 {
@ -80,7 +73,6 @@
&fpd_dma_chan6 {
status = "okay";
xlnx,include-sg; /* for testing purpose */
};
&fpd_dma_chan7 {
@ -89,7 +81,6 @@
&fpd_dma_chan8 {
status = "okay";
xlnx,include-sg; /* for testing purpose */
};
&gem2 {

9
arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts
View File

@ -55,16 +55,10 @@
/* fpd_dma clk 667MHz, lpd_dma 500MHz */
&fpd_dma_chan1 {
status = "okay";
xlnx,include-sg; /* for testing purpose */
xlnx,overfetch; /* for testing purpose */
xlnx,ratectrl = <0>; /* for testing purpose */
xlnx,src-issue = <31>;
};
&fpd_dma_chan2 {
status = "okay";
xlnx,ratectrl = <100>; /* for testing purpose */
xlnx,src-issue = <4>; /* for testing purpose */
};
&fpd_dma_chan3 {
@ -73,7 +67,6 @@
&fpd_dma_chan4 {
status = "okay";
xlnx,include-sg; /* for testing purpose */
};
&fpd_dma_chan5 {
@ -82,7 +75,6 @@
&fpd_dma_chan6 {
status = "okay";
xlnx,include-sg; /* for testing purpose */
};
&fpd_dma_chan7 {
@ -91,7 +83,6 @@
&fpd_dma_chan8 {
status = "okay";
xlnx,include-sg; /* for testing purpose */
};
&lpd_dma_chan1 {

11
arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts
View File

@ -28,7 +28,7 @@
};
chosen {
bootargs = "earlycon=cdns,mmio,0xff000000,115200n8";
bootargs = "earlycon";
stdout-path = "serial0:115200n8";
};
@ -41,16 +41,10 @@
/* fpd_dma clk 667MHz, lpd_dma 500MHz */
&fpd_dma_chan1 {
status = "okay";
xlnx,include-sg; /* for testing purpose */
xlnx,overfetch; /* for testing purpose */
xlnx,ratectrl = <0>; /* for testing purpose */
xlnx,src-issue = <31>;
};
&fpd_dma_chan2 {
status = "okay";
xlnx,ratectrl = <100>; /* for testing purpose */
xlnx,src-issue = <4>; /* for testing purpose */
};
&fpd_dma_chan3 {
@ -59,7 +53,6 @@
&fpd_dma_chan4 {
status = "okay";
xlnx,include-sg; /* for testing purpose */
};
&fpd_dma_chan5 {
@ -68,7 +61,6 @@
&fpd_dma_chan6 {
status = "okay";
xlnx,include-sg; /* for testing purpose */
};
&fpd_dma_chan7 {
@ -77,7 +69,6 @@
&fpd_dma_chan8 {
status = "okay";
xlnx,include-sg; /* for testing purpose */
};
&gem1 {

20
arch/arm/dts/zynqmp-zcu102-revA.dts
View File

@ -14,6 +14,7 @@
#include "zynqmp-clk.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
#include <dt-bindings/phy/phy.h>
/ {
model = "ZynqMP ZCU102 RevA";
@ -80,16 +81,10 @@
/* fpd_dma clk 667MHz, lpd_dma 500MHz */
&fpd_dma_chan1 {
status = "okay";
xlnx,include-sg; /* for testing purpose */
xlnx,overfetch; /* for testing purpose */
xlnx,ratectrl = <0>; /* for testing purpose */
xlnx,src-issue = <31>;
};
&fpd_dma_chan2 {
status = "okay";
xlnx,ratectrl = <100>; /* for testing purpose */
xlnx,src-issue = <4>; /* for testing purpose */
};
&fpd_dma_chan3 {
@ -98,7 +93,6 @@
&fpd_dma_chan4 {
status = "okay";
xlnx,include-sg; /* for testing purpose */
};
&fpd_dma_chan5 {
@ -107,7 +101,6 @@
&fpd_dma_chan6 {
status = "okay";
xlnx,include-sg; /* for testing purpose */
};
&fpd_dma_chan7 {
@ -116,7 +109,6 @@
&fpd_dma_chan8 {
status = "okay";
xlnx,include-sg; /* for testing purpose */
};
&gem3 {
@ -884,6 +876,8 @@ drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751) += max20751.o
ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
phy-names = "sata-phy";
phys = <&lane3 PHY_TYPE_SATA 1 1 125000000>;
};
/* SD1 with level shifter */
@ -895,6 +889,10 @@ drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751) += max20751.o
xlnx,mio_bank = <1>;
};
&serdes {
status = "okay";
};
&uart0 {
status = "okay";
pinctrl-names = "default";
@ -917,6 +915,10 @@ drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751) += max20751.o
&dwc3_0 {
status = "okay";
dr_mode = "host";
snps,usb3_lpm_capable;
phy-names = "usb3-phy";
phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;
maximum-speed = "super-speed";
};
&watchdog0 {

3
arch/arm/dts/zynqmp.dtsi
View File

@ -261,7 +261,7 @@
method = "smc";
};
firmware {
pmufw: firmware {
compatible = "xlnx,zynqmp-pm";
method = "smc";
interrupt-parent = <&gic>;
@ -804,6 +804,7 @@
};
qspi: spi@ff0f0000 {
u-boot,dm-pre-reloc;
compatible = "xlnx,zynqmp-qspi-1.0";
status = "disabled";
clock-names = "ref_clk", "pclk";

1
arch/arm/include/asm/arch-zynqmp/sys_proto.h
View File

@ -30,6 +30,7 @@ enum {
TCM_SPLIT,
};
int zynq_board_read_rom_ethaddr(unsigned char *ethaddr);
unsigned int zynqmp_get_silicon_version(void);
void psu_init(void);

23
board/xilinx/zynqmp/zynqmp.c
View File

@ -260,10 +260,10 @@ int board_init(void)
if (current_el() != 3) {
static char version[ZYNQMP_VERSION_SIZE];
strncat(version, "xczu", 4);
strncat(version, "zu", 2);
zynqmppl.name = strncat(version,
zynqmp_get_silicon_idcode_name(),
ZYNQMP_VERSION_SIZE - 5);
ZYNQMP_VERSION_SIZE - 3);
printf("Chip ID:\t%s\n", zynqmppl.name);
fpga_init();
fpga_add(fpga_xilinx, &zynqmppl);
@ -277,10 +277,13 @@ int board_early_init_r(void)
{
u32 val;
if (current_el() != 3)
return 0;
val = readl(&crlapb_base->timestamp_ref_ctrl);
val &= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
if (current_el() == 3 && !val) {
if (!val) {
val = readl(&crlapb_base->timestamp_ref_ctrl);
val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
writel(val, &crlapb_base->timestamp_ref_ctrl);
@ -343,13 +346,17 @@ int board_late_init(void)
u8 bootmode;
const char *mode;
char *new_targets;
int ret;
if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
debug("Saved variables - Skipping\n");
return 0;
}
reg = readl(&crlapb_base->boot_mode);
ret = zynqmp_mmio_read((ulong)&crlapb_base->boot_mode, &reg);
if (ret)
return -EINVAL;
if (reg >> BOOT_MODE_ALT_SHIFT)
reg >>= BOOT_MODE_ALT_SHIFT;
@ -360,23 +367,28 @@ int board_late_init(void)
case USB_MODE:
puts("USB_MODE\n");
mode = "usb";
env_set("modeboot", "usb_dfu_spl");
break;
case JTAG_MODE:
puts("JTAG_MODE\n");
mode = "pxe dhcp";
env_set("modeboot", "jtagboot");
break;
case QSPI_MODE_24BIT:
case QSPI_MODE_32BIT:
mode = "qspi0";
puts("QSPI_MODE\n");
env_set("modeboot", "qspiboot");
break;
case EMMC_MODE:
puts("EMMC_MODE\n");
mode = "mmc0";
env_set("modeboot", "emmcboot");
break;
case SD_MODE:
puts("SD_MODE\n");
mode = "mmc0";
env_set("modeboot", "sdboot");
break;
case SD1_LSHFT_MODE:
puts("LVL_SHFT_");
@ -385,13 +397,16 @@ int board_late_init(void)
puts("SD_MODE1\n");
#if defined(CONFIG_ZYNQ_SDHCI0) && defined(CONFIG_ZYNQ_SDHCI1)
mode = "mmc1";
env_set("sdbootdev", "1");
#else
mode = "mmc0";
#endif
env_set("modeboot", "sdboot");
break;
case NAND_MODE:
puts("NAND_MODE\n");
mode = "nand0";
env_set("modeboot", "nandboot");
break;
default:
mode = "";

2
common/bootm.c
View File

@ -248,7 +248,7 @@ int bootm_find_images(int flag, int argc, char * const argv[])
#endif
#if IMAGE_ENABLE_FIT
#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_XILINX)
#if defined(CONFIG_FPGA)
/* find bitstreams */
ret = boot_get_fpga(argc, argv, &images, IH_ARCH_DEFAULT,
NULL, NULL);

6
common/image.c
View File

@ -1215,7 +1215,7 @@ int boot_get_setup(bootm_headers_t *images, uint8_t arch,
}
#if IMAGE_ENABLE_FIT
#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_XILINX)
#if defined(CONFIG_FPGA)
int boot_get_fpga(int argc, char * const argv[], bootm_headers_t *images,
uint8_t arch, const ulong *ld_start, ulong * const ld_len)
{
@ -1226,8 +1226,6 @@ int boot_get_fpga(int argc, char * const argv[], bootm_headers_t *images,
const char *uname, *name;
int err;
int devnum = 0; /* TODO support multi fpga platforms */
const fpga_desc * const desc = fpga_get_desc(devnum);
xilinx_desc *desc_xilinx = desc->devdesc;
/* Check to see if the images struct has a FIT configuration */
if (!genimg_has_config(images)) {
@ -1272,7 +1270,7 @@ int boot_get_fpga(int argc, char * const argv[], bootm_headers_t *images,
return fit_img_result;
}
if (img_len >= desc_xilinx->size) {
if (!fpga_is_partial_data(devnum, img_len)) {
name = "full";
err = fpga_loadbitstream(devnum, (char *)img_data,
img_len, BIT_FULL);

2
configs/syzygy_hub_defconfig
View File

@ -3,6 +3,7 @@ CONFIG_SYS_VENDOR="opalkelly"
CONFIG_SYS_CONFIG_NAME="syzygy_hub"
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_DEFAULT_DEVICE_TREE="zynq-syzygy-hub"
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
@ -10,6 +11,7 @@ CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_OS_BOOT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Zynq> "

2
configs/topic_miami_defconfig
View File

@ -3,12 +3,14 @@ CONFIG_SYS_VENDOR="topic"
CONFIG_SYS_CONFIG_NAME="topic_miami"
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_BOOT_INIT_FILE="board/topic/zynq/zynq-topic-miami/ps7_regs.txt"
CONFIG_DEFAULT_DEVICE_TREE="zynq-topic-miami"
CONFIG_DEBUG_UART=y
CONFIG_BOOTDELAY=0
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL=y
CONFIG_SPL_STACK_R=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="zynq-uboot> "
CONFIG_CMD_THOR_DOWNLOAD=y

2
configs/topic_miamilite_defconfig
View File

@ -3,12 +3,14 @@ CONFIG_SYS_VENDOR="topic"
CONFIG_SYS_CONFIG_NAME="topic_miami"
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_BOOT_INIT_FILE="board/topic/zynq/zynq-topic-miamilite/ps7_regs.txt"
CONFIG_DEFAULT_DEVICE_TREE="zynq-topic-miamilite"
CONFIG_DEBUG_UART=y
CONFIG_BOOTDELAY=0
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL=y
CONFIG_SPL_STACK_R=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="zynq-uboot> "
CONFIG_CMD_THOR_DOWNLOAD=y

2
configs/topic_miamiplus_defconfig
View File

@ -3,12 +3,14 @@ CONFIG_SYS_VENDOR="topic"
CONFIG_SYS_CONFIG_NAME="topic_miami"
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_BOOT_INIT_FILE="board/topic/zynq/zynq-topic-miamiplus/ps7_regs.txt"
CONFIG_DEFAULT_DEVICE_TREE="zynq-topic-miamiplus"
CONFIG_DEBUG_UART=y
CONFIG_BOOTDELAY=0
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL=y
CONFIG_SPL_STACK_R=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="zynq-uboot> "
CONFIG_CMD_THOR_DOWNLOAD=y

7
configs/xilinx_zynqmp_ep_defconfig
View File

@ -14,7 +14,6 @@ CONFIG_SPL_LOAD_FIT=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SYS_PROMPT="ZynqMP> "
CONFIG_FASTBOOT=y
@ -25,6 +24,7 @@ CONFIG_FASTBOOT_FLASH_MMC_DEV=0
CONFIG_CMD_THOR_DOWNLOAD=y
# CONFIG_CMD_EDITENV is not set
# CONFIG_CMD_ENV_EXISTS is not set
CONFIG_CMD_CLK=y
CONFIG_CMD_DFU=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
@ -57,6 +57,7 @@ CONFIG_FPGA_ZYNQMPPL=y
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_CADENCE=y
CONFIG_MISC=y
CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
@ -64,6 +65,10 @@ CONFIG_NAND=y
CONFIG_NAND_ARASAN=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_DM_ETH=y
CONFIG_PHY_GIGE=y
CONFIG_ZYNQ_GEM=y

9
configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
View File

@ -15,16 +15,20 @@ CONFIG_SPL_LOAD_FIT=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_RAM_DEVICE=y
CONFIG_SYS_PROMPT="ZynqMP> "
CONFIG_FASTBOOT=y
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
CONFIG_CMD_THOR_DOWNLOAD=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_CLK=y
CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_FPGA_LOADBP=y
CONFIG_CMD_FPGA_LOADP=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
@ -47,14 +51,17 @@ CONFIG_FPGA_ZYNQMPPL=y
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_CADENCE=y
CONFIG_MISC=y
CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_DM_ETH=y
CONFIG_PHY_GIGE=y
CONFIG_ZYNQ_GEM=y

7
configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig
View File

@ -16,15 +16,19 @@ CONFIG_SPL_LOAD_FIT=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_RAM_DEVICE=y
CONFIG_SYS_PROMPT="ZynqMP> "
CONFIG_FASTBOOT=y
CONFIG_FASTBOOT_FLASH=y
CONFIG_CMD_THOR_DOWNLOAD=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_CLK=y
CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_FPGA_LOADBP=y
CONFIG_CMD_FPGA_LOADP=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
@ -46,6 +50,7 @@ CONFIG_FPGA_ZYNQMPPL=y
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_CADENCE=y
CONFIG_MISC=y
# CONFIG_MMC is not set
CONFIG_DM_MMC=y
CONFIG_NAND=y

14
configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig
View File

@ -12,11 +12,15 @@ CONFIG_SPL_LOAD_FIT=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_RAM_DEVICE=y
CONFIG_SYS_PROMPT="ZynqMP> "
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_CLK=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_FPGA_LOADBP=y
CONFIG_CMD_FPGA_LOADP=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_TFTPPUT=y
@ -35,9 +39,17 @@ CONFIG_FPGA_ZYNQMPPL=y
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_CADENCE=y
CONFIG_MISC=y
CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_DM_ETH=y
CONFIG_PHY_GIGE=y
CONFIG_ZYNQ_GEM=y

7
configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig
View File

@ -13,11 +13,15 @@ CONFIG_SPL_LOAD_FIT=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_RAM_DEVICE=y
CONFIG_SYS_PROMPT="ZynqMP> "
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_CLK=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_FPGA_LOADBP=y
CONFIG_CMD_FPGA_LOADP=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_TFTPPUT=y
@ -35,6 +39,7 @@ CONFIG_FPGA_ZYNQMPPL=y
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_CADENCE=y
CONFIG_MISC=y
CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y

9
configs/xilinx_zynqmp_zcu102_rev1_0_defconfig
View File

@ -15,8 +15,9 @@ CONFIG_SPL_LOAD_FIT=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_RAM_DEVICE=y
CONFIG_SYS_PROMPT="ZynqMP> "
CONFIG_FASTBOOT=y
CONFIG_FASTBOOT_FLASH=y
@ -24,8 +25,11 @@ CONFIG_FASTBOOT_FLASH_MMC_DEV=0
CONFIG_CMD_THOR_DOWNLOAD=y
CONFIG_CMD_EEPROM=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_CLK=y
CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_FPGA_LOADBP=y
CONFIG_CMD_FPGA_LOADP=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
@ -49,14 +53,17 @@ CONFIG_FPGA_XILINX=y
CONFIG_FPGA_ZYNQMPPL=y
CONFIG_DM_GPIO=y
CONFIG_CMD_PCA953X=y
CONFIG_MISC=y
CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_DM_ETH=y
CONFIG_PHY_GIGE=y
CONFIG_ZYNQ_GEM=y

9
configs/xilinx_zynqmp_zcu102_revA_defconfig
View File

@ -15,8 +15,9 @@ CONFIG_SPL_LOAD_FIT=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_RAM_DEVICE=y
CONFIG_SYS_PROMPT="ZynqMP> "
CONFIG_FASTBOOT=y
CONFIG_FASTBOOT_FLASH=y
@ -24,8 +25,11 @@ CONFIG_FASTBOOT_FLASH_MMC_DEV=0
CONFIG_CMD_THOR_DOWNLOAD=y
CONFIG_CMD_EEPROM=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_CLK=y
CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_FPGA_LOADBP=y
CONFIG_CMD_FPGA_LOADP=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
@ -49,14 +53,17 @@ CONFIG_FPGA_XILINX=y
CONFIG_FPGA_ZYNQMPPL=y
CONFIG_DM_GPIO=y
CONFIG_CMD_PCA953X=y
CONFIG_MISC=y
CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_DM_ETH=y
CONFIG_PHY_GIGE=y
CONFIG_ZYNQ_GEM=y

9
configs/xilinx_zynqmp_zcu102_revB_defconfig
View File

@ -15,8 +15,9 @@ CONFIG_SPL_LOAD_FIT=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SPL=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_RAM_DEVICE=y
CONFIG_SYS_PROMPT="ZynqMP> "
CONFIG_FASTBOOT=y
CONFIG_FASTBOOT_FLASH=y
@ -24,8 +25,11 @@ CONFIG_FASTBOOT_FLASH_MMC_DEV=0
CONFIG_CMD_THOR_DOWNLOAD=y
CONFIG_CMD_EEPROM=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_CLK=y
CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_FPGA_LOADBP=y
CONFIG_CMD_FPGA_LOADP=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
@ -49,14 +53,17 @@ CONFIG_FPGA_XILINX=y
CONFIG_FPGA_ZYNQMPPL=y
CONFIG_DM_GPIO=y
CONFIG_CMD_PCA953X=y
CONFIG_MISC=y
CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_DM_ETH=y
CONFIG_PHY_GIGE=y
CONFIG_ZYNQ_GEM=y

2
configs/zynq_cc108_defconfig
View File

@ -1,6 +1,7 @@
CONFIG_ARM=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_DEFAULT_DEVICE_TREE="zynq-cc108"
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
@ -8,6 +9,7 @@ CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL=y
CONFIG_SPL_STACK_R=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Zynq> "
CONFIG_CMD_BOOTZ=y

2
configs/zynq_cse_qspi_defconfig
View File

@ -2,6 +2,7 @@ CONFIG_ARM=y
CONFIG_SYS_CONFIG_NAME="zynq_cse"
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0xFFFC0000
CONFIG_SPL_STACK_R_ADDR=0x200000
# CONFIG_ZYNQ_DDRC_INIT is not set
CONFIG_DEFAULT_DEVICE_TREE="zynq-cse-qspi-single"
CONFIG_DEBUG_UART=y
@ -9,6 +10,7 @@ CONFIG_DEBUG_UART=y
CONFIG_BOOTDELAY=-1
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL=y
CONFIG_SPL_STACK_R=y
CONFIG_SYS_PROMPT="Zynq> "
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_CONSOLE is not set

2
configs/zynq_microzed_defconfig
View File

@ -1,12 +1,14 @@
CONFIG_ARM=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_DEFAULT_DEVICE_TREE="zynq-microzed"
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_OS_BOOT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Zynq> "

2
configs/zynq_picozed_defconfig
View File

@ -1,9 +1,11 @@
CONFIG_ARM=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_DEFAULT_DEVICE_TREE="zynq-picozed"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_OS_BOOT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Zynq> "

2
configs/zynq_z_turn_defconfig
View File

@ -1,6 +1,7 @@
CONFIG_ARM=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_DEFAULT_DEVICE_TREE="zynq-zturn-myir"
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
@ -8,6 +9,7 @@ CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_OS_BOOT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Zynq> "

2
configs/zynq_zc702_defconfig
View File

@ -2,6 +2,7 @@ CONFIG_ARM=y
CONFIG_SYS_CONFIG_NAME="zynq_zc70x"
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_DEFAULT_DEVICE_TREE="zynq-zc702"
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
@ -9,6 +10,7 @@ CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_OS_BOOT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Zynq> "

2
configs/zynq_zc706_defconfig
View File

@ -2,6 +2,7 @@ CONFIG_ARM=y
CONFIG_SYS_CONFIG_NAME="zynq_zc70x"
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_DEFAULT_DEVICE_TREE="zynq-zc706"
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
@ -9,6 +10,7 @@ CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_OS_BOOT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Zynq> "

2
configs/zynq_zc770_xm010_defconfig
View File

@ -1,6 +1,7 @@
CONFIG_ARM=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm010"
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
@ -9,6 +10,7 @@ CONFIG_FIT_VERBOSE=y
CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM010"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_OS_BOOT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Zynq> "

2
configs/zynq_zc770_xm011_defconfig
View File

@ -1,6 +1,7 @@
CONFIG_ARM=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SPL_STACK_R_ADDR=0x200000
# CONFIG_SPL_FAT_SUPPORT is not set
CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm011"
CONFIG_FIT=y
@ -9,6 +10,7 @@ CONFIG_FIT_VERBOSE=y
CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM011"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_OS_BOOT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Zynq> "

2
configs/zynq_zc770_xm012_defconfig
View File

@ -1,6 +1,7 @@
CONFIG_ARM=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SPL_STACK_R_ADDR=0x200000
# CONFIG_SPL_FAT_SUPPORT is not set
CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm012"
CONFIG_FIT=y
@ -9,6 +10,7 @@ CONFIG_FIT_VERBOSE=y
CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM012"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_OS_BOOT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Zynq> "

2
configs/zynq_zc770_xm013_defconfig
View File

@ -1,6 +1,7 @@
CONFIG_ARM=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SPL_STACK_R_ADDR=0x200000
# CONFIG_SPL_FAT_SUPPORT is not set
CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm013"
CONFIG_FIT=y
@ -9,6 +10,7 @@ CONFIG_FIT_VERBOSE=y
CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM013"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_OS_BOOT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Zynq> "

2
configs/zynq_zed_defconfig
View File

@ -1,12 +1,14 @@
CONFIG_ARM=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_DEFAULT_DEVICE_TREE="zynq-zed"
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_OS_BOOT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Zynq> "

2
configs/zynq_zybo_defconfig
View File

@ -2,6 +2,7 @@ CONFIG_ARM=y
CONFIG_SYS_CONFIG_NAME="zynq_zybo"
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_DEFAULT_DEVICE_TREE="zynq-zybo"
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
@ -9,6 +10,7 @@ CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_OS_BOOT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Zynq> "

9
drivers/fpga/fpga.c
View File

@ -170,6 +170,15 @@ int fpga_add(fpga_type devtype, void *desc)
return devnum;
}
/*
* Return 1 if the fpga data is partial.
* This is only required for fpga drivers that support bitstream_type.
*/
int __weak fpga_is_partial_data(int devnum, size_t img_len)
{
return 0;
}
/*
* Convert bitstream data and load into the fpga
*/

13
drivers/fpga/xilinx.c
View File

@ -24,6 +24,19 @@ static int xilinx_validate(xilinx_desc *desc, char *fn);
/* ------------------------------------------------------------------------- */
int fpga_is_partial_data(int devnum, size_t img_len)
{
const fpga_desc * const desc = fpga_get_desc(devnum);
xilinx_desc *desc_xilinx = desc->devdesc;
/* Check datasize against FPGA size */
if (img_len >= desc_xilinx->size)
return 0;
/* datasize is smaller, must be partial data */
return 1;
}
int fpga_loadbitstream(int devnum, char *fpgadata, size_t size,
bitstream_type bstype)
{

16
include/configs/xilinx_zynqmp.h
View File

@ -126,6 +126,7 @@
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
#define CONFIG_SYS_LONGHELP
#define CONFIG_CMDLINE_EDITING
#define CONFIG_PANIC_HANG
#define CONFIG_SYS_MAXARGS 64
/* Ethernet driver */
@ -233,6 +234,15 @@
#define CONFIG_SPL_FRAMEWORK
#if defined(CONFIG_SPL_SPI_FLASH_SUPPORT)
# define CONFIG_SPL_SPI_LOAD
# define CONFIG_SYS_SPI_KERNEL_OFFS 0x80000
# define CONFIG_SYS_SPI_ARGS_OFFS 0xa0000
# define CONFIG_SYS_SPI_ARGS_SIZE 0xa0000
# define CONFIG_SYS_SPI_U_BOOT_OFFS 0x170000
#endif
/* u-boot is like dtb */
#define CONFIG_SPL_FS_LOAD_ARGS_NAME "u-boot.bin"
#define CONFIG_SYS_SPL_ARGS_ADDR 0x8000000
@ -257,14 +267,14 @@
# define CONFIG_SPL_ENV_SUPPORT
# define CONFIG_SPL_HASH_SUPPORT
# define CONFIG_ENV_MAX_ENTRIES 10
#endif
# define CONFIG_SYS_SPL_MALLOC_START 0x20000000
# define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
#define CONFIG_SYS_SPL_MALLOC_START 0x20000000
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
#ifdef CONFIG_SPL_SYS_MALLOC_SIMPLE
# error "Disable CONFIG_SPL_SYS_MALLOC_SIMPLE. Full malloc needs to be used"
#endif
#endif
#define CONFIG_BOARD_EARLY_INIT_F

7
include/configs/zynq-common.h
View File

@ -344,12 +344,9 @@
/* 3 * 64kB blocks of OCM - one is on the top because of bootrom */
#define CONFIG_SPL_MAX_SIZE 0x30000
/* The highest 64k OCM address */
#define OCM_HIGH_ADDR 0xffff0000
/* On the top of OCM space */
#define CONFIG_SYS_SPL_MALLOC_START OCM_HIGH_ADDR
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x2000
#define CONFIG_SYS_SPL_MALLOC_START CONFIG_SPL_STACK_R_ADDR
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x2000000
/*
* SPL stack position - and stack goes down

1
include/fpga.h
View File

@ -54,6 +54,7 @@ void fpga_init(void);
int fpga_add(fpga_type devtype, void *desc);
int fpga_count(void);
const fpga_desc *const fpga_get_desc(int devnum);
int fpga_is_partial_data(int devnum, size_t img_len);
int fpga_load(int devnum, const void *buf, size_t bsize,
bitstream_type bstype);
int fpga_fsload(int devnum, const void *buf, size_t size,

11
test/py/tests/test_env.py
View File

@ -125,7 +125,16 @@ def set_var(state_test_env, var, value):
Nothing.
"""
state_test_env.u_boot_console.run_command('setenv %s "%s"' % (var, value))
bc = state_test_env.u_boot_console.config.buildconfig
if bc.get('config_hush_parser', None):
quote = '"'
else:
quote = ''
if ' ' in value:
pytest.skip('Space in variable value on non-Hush shell')
state_test_env.u_boot_console.run_command(
'setenv %s %s%s%s' % (var, quote, value, quote))
state_test_env.env[var] = value
def validate_empty(state_test_env, var):

32
tools/zynqmpimage.c
View File

@ -245,16 +245,38 @@ static int zynqmpimage_check_image_types(uint8_t type)
return EXIT_FAILURE;
}
static int fsize(FILE *fp)
static uint32_t fsize(FILE *fp)
{
int size;
int origin = ftell(fp);
int size, ret, origin;
origin = ftell(fp);
if (origin < 0) {
fprintf(stderr, "Incorrect file size\n");
fclose(fp);
exit(2);
}
ret = fseek(fp, 0L, SEEK_END);
if (ret) {
fprintf(stderr, "Incorrect file SEEK_END\n");
fclose(fp);
exit(3);
}
fseek(fp, 0L, SEEK_END);
size = ftell(fp);
if (size < 0) {
fprintf(stderr, "Incorrect file size\n");
fclose(fp);
exit(4);
}
/* going back */
fseek(fp, origin, SEEK_SET);
ret = fseek(fp, origin, SEEK_SET);
if (ret) {
fprintf(stderr, "Incorrect file SEEK_SET to %d\n", origin);
fclose(fp);
exit(3);
}
return size;
}