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spi: zynqmp_qspi: Add support for 64-bit read/write

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When we pass the 64-bit address to read/write, only lower 32-bit
address is getting updated. Program the upper 32-bit address in the
DMA destination memory address MSBs register, which can handle upto
44-bit destination address.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Link: https://lore.kernel.org/r/20221125104413.26140-1-venkatesh.abbarapu@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
This commit is contained in:
Venkatesh Yadav Abbarapu 2022-11-25 16:14:13 +05:30 committed by Michal Simek
parent 31e66aea37
commit 906e20a613
1 changed files with 4 additions and 2 deletions
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6
drivers/spi/zynqmp_gqspi.c
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@ -662,7 +662,7 @@ static int zynqmp_qspi_start_io(struct zynqmp_qspi_priv *priv,
static int zynqmp_qspi_start_dma(struct zynqmp_qspi_priv *priv,
u32 gen_fifo_cmd, u32 *buf)
{
u32 addr;
unsigned long addr;
u32 size;
u32 actuallen = priv->len;
u32 totallen = priv->len;
@ -678,7 +678,9 @@ static int zynqmp_qspi_start_dma(struct zynqmp_qspi_priv *priv,
totallen -= priv->len; /* Save remaining bytes length to read */
actuallen = priv->len; /* Actual number of bytes reading */
writel((unsigned long)buf, &dma_regs->dmadst);
writel(lower_32_bits((unsigned long)buf), &dma_regs->dmadst);
writel(upper_32_bits((unsigned long)buf) & GENMASK(11, 0),
&dma_regs->dmadstmsb);
writel(roundup(priv->len, GQSPI_DMA_ALIGN), &dma_regs->dmasize);
writel(GQSPI_DMA_DST_I_STS_MASK, &dma_regs->dmaier);
addr = (unsigned long)buf;