Merge remote-tracking branch 'u-boot-imx/master'

This commit is contained in:
Albert ARIBAUD 2012-09-29 11:12:34 +02:00
commit 8f0732ac3d
9 changed files with 50 additions and 25 deletions

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@ -30,6 +30,7 @@
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/crm_regs.h>
#include <ipu_pixfmt.h>
#ifdef CONFIG_FSL_ESDHC
#include <fsl_esdhc.h>
@ -138,3 +139,11 @@ u32 get_ahb_clk(void)
return get_periph_clk() / (ahb_podf + 1);
}
#if defined(CONFIG_VIDEO_IPUV3)
void arch_preboot_os(void)
{
/* disable video before launching O/S */
ipuv3_fb_shutdown();
}
#endif

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@ -321,6 +321,8 @@
#define BOARD_REV_1_0 0x0
#define BOARD_REV_2_0 0x1
#define BOARD_VER_OFFSET 0x8
#define IMX_IIM_BASE (IIM_BASE_ADDR)
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))

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@ -100,19 +100,6 @@ int board_mmc_init(bd_t *bis)
#ifdef CONFIG_CMD_NET
#define MII_OPMODE_STRAP_OVERRIDE 0x16
#define MII_PHY_CTRL1 0x1e
#define MII_PHY_CTRL2 0x1f
int fecmxc_mii_postcall(int phy)
{
miiphy_write("FEC1", phy, MII_BMCR, 0x9000);
miiphy_write("FEC1", phy, MII_OPMODE_STRAP_OVERRIDE, 0x0202);
if (phy == 3)
miiphy_write("FEC1", 3, MII_PHY_CTRL2, 0x8180);
return 0;
}
int board_eth_init(bd_t *bis)
{
struct mxs_clkctrl_regs *clkctrl_regs =
@ -152,24 +139,12 @@ int board_eth_init(bd_t *bis)
return -EINVAL;
}
ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall);
if (ret) {
puts("FEC MXS: Unable to register FEC0 mii postcall\n");
return ret;
}
dev = eth_get_dev_by_name("FEC1");
if (!dev) {
puts("FEC MXS: Unable to get FEC1 device entry\n");
return -EINVAL;
}
ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall);
if (ret) {
puts("FEC MXS: Unable to register FEC1 mii postcall\n");
return ret;
}
return ret;
}

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@ -60,6 +60,14 @@ int dram_init(void)
return 0;
}
u32 get_board_rev(void)
{
u32 rev = get_cpu_rev();
if (!gpio_get_value(IMX_GPIO_NR(1, 22)))
rev |= BOARD_REV_2_0 << BOARD_VER_OFFSET;
return rev;
}
static void setup_iomux_uart(void)
{
unsigned int pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |

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@ -66,6 +66,14 @@
write32 0x53f80064, 0x45600000
write32 0x53f80008, 0x20034000
/*
* PCDR2: NFC = 33.25 MHz
* This is required for the NAND Flash of this board, which is a Samsung
* K9F1G08U0B with 25-ns R/W cycle times, in order to make it work with
* the NFC driver in symmetric (i.e. one-cycle) mode.
*/
write32 0x53f80020, 0x01010103
/*
* enable all implemented clocks in all three
* clock control registers

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@ -38,6 +38,7 @@
#include "videomodes.h"
#include "ipu.h"
#include "mxcfb.h"
#include "ipu_regs.h"
static int mxcfb_map_video_memory(struct fb_info *fbi);
static int mxcfb_unmap_video_memory(struct fb_info *fbi);
@ -576,6 +577,25 @@ err0:
return ret;
}
void ipuv3_fb_shutdown(void)
{
int i;
struct ipu_stat *stat = (struct ipu_stat *)IPU_STAT;
for (i = 0; i < ARRAY_SIZE(mxcfb_info); i++) {
struct fb_info *fbi = mxcfb_info[i];
if (fbi) {
struct mxcfb_info *mxc_fbi = fbi->par;
ipu_disable_channel(mxc_fbi->ipu_ch);
ipu_uninit_channel(mxc_fbi->ipu_ch);
}
}
for (i = 0; i < ARRAY_SIZE(stat->int_stat); i++) {
__raw_writel(__raw_readl(&stat->int_stat[i]),
&stat->int_stat[i]);
}
}
void *video_hw_init(void)
{
int ret;

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@ -63,6 +63,7 @@
#define CONFIG_CMD_NET
#define CONFIG_CMD_NFS
#define CONFIG_CMD_PING
#define CONFIG_CMD_SETEXPR
#define CONFIG_CMD_SF
#define CONFIG_CMD_SPI
#define CONFIG_CMD_USB

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@ -44,6 +44,7 @@
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
#define CONFIG_REVISION_TAG
#define CONFIG_OF_LIBFDT

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@ -77,5 +77,6 @@
#define IPU_PIX_FMT_YUV422P fourcc('4', '2', '2', 'P') /*< 16 YUV 4:2:2 */
int ipuv3_fb_init(struct fb_videomode *mode, uint8_t disp, uint32_t pixfmt);
void ipuv3_fb_shutdown(void);
#endif