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Merge branch 'master' of git://www.denx.de/git/u-boot-ppc4xx

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This commit is contained in:
Wolfgang Denk 2008-01-23 14:19:45 +01:00
commit 8f00731818
36 changed files with 2948 additions and 1106 deletions
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1
MAINTAINERS
View File

@ -154,6 +154,7 @@ Matthias Fuchs <matthias.fuchs@esd-electronics.com>
DASA_SIM IOP480 (PPC401)
DP405 PPC405EP
DU405 PPC405GP
DU440 PPC440EPx
G2000 PPC405EP
HH405 PPC405EP
HUB405 PPC405EP

1
MAKEALL
View File

@ -178,6 +178,7 @@ LIST_4xx=" \
DASA_SIM \
DP405 \
DU405 \
DU440 \
ebony \
ERIC \
EXBITGEN \

3
Makefile
View File

@ -1208,6 +1208,9 @@ DP405_config: unconfig
DU405_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx du405 esd
DU440_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx du440 esd
ebony_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx ebony amcc

2
board/amcc/kilauea/cmd_pll.c
View File

@ -294,4 +294,4 @@ U_BOOT_CMD(
-----------------------------------------------\n"
);
#endif /* (CONFIG_COMMANDS & CFG_CMD_EEPROM) */
#endif /* CONFIG_CMD_EEPROM */

2
board/amcc/makalu/cmd_pll.c
View File

@ -294,4 +294,4 @@ U_BOOT_CMD(
-----------------------------------------------\n"
);
#endif /* (CONFIG_COMMANDS & CFG_CMD_EEPROM) */
#endif /* CONFIG_CMD_EEPROM */

7
board/amcc/sequoia/init.S
View File

@ -1,4 +1,6 @@
/*
* (C) Copyright 2008
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
@ -23,7 +25,7 @@
#include <asm-ppc/mmu.h>
#include <config.h>
/**************************************************************************
/*
* TLB TABLE
*
* This table is used by the cpu boot code to setup the initial tlb
@ -31,8 +33,7 @@
* this table lets each board set things up however they like.
*
* Pointer to the table is returned in r1
*
*************************************************************************/
*/
.section .bootpg,"ax"
.globl tlbtab

246
board/amcc/sequoia/sequoia.c
View File

@ -4,7 +4,7 @@
*
* (C) Copyright 2006
* Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
* Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
* Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
@ -29,11 +29,12 @@
#include <asm/gpio.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <asm/bitops.h>
#include <asm/ppc4xx-intvec.h>
DECLARE_GLOBAL_DATA_PTR;
extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
ulong flash_get_size (ulong base, int banknum);
@ -46,9 +47,9 @@ int board_early_init_f(void)
mtdcr(ebccfga, xbcfg);
mtdcr(ebccfgd, 0xb8400000);
/*--------------------------------------------------------------------
/*
* Setup the interrupt controller polarities, triggers, etc.
*-------------------------------------------------------------------*/
*/
mtdcr(uic0sr, 0xffffffff); /* clear all */
mtdcr(uic0er, 0x00000000); /* disable all */
mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */
@ -87,9 +88,11 @@ int board_early_init_f(void)
/* select Ethernet pins */
mfsdr(SDR0_PFC1, sdr0_pfc1);
sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) | SDR0_PFC1_SELECT_CONFIG_4;
sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |
SDR0_PFC1_SELECT_CONFIG_4;
mfsdr(SDR0_PFC2, sdr0_pfc2);
sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) | SDR0_PFC2_SELECT_CONFIG_4;
sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
SDR0_PFC2_SELECT_CONFIG_4;
mtsdr(SDR0_PFC2, sdr0_pfc2);
mtsdr(SDR0_PFC1, sdr0_pfc1);
@ -109,9 +112,6 @@ int board_early_init_f(void)
return 0;
}
/*---------------------------------------------------------------------------+
| misc_init_r.
+---------------------------------------------------------------------------*/
int misc_init_r(void)
{
uint pbcr;
@ -124,11 +124,7 @@ int misc_init_r(void)
char *act = getenv("usbact");
#endif
/*
* FLASH stuff...
*/
/* Re-do sizing to get full correct info */
/* Re-do flash sizing to get full correct info */
/* adjust flash start and offset */
gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
@ -140,32 +136,7 @@ int misc_init_r(void)
mtdcr(ebccfga, pb0cr);
#endif
pbcr = mfdcr(ebccfgd);
switch (gd->bd->bi_flashsize) {
case 1 << 20:
size_val = 0;
break;
case 2 << 20:
size_val = 1;
break;
case 4 << 20:
size_val = 2;
break;
case 8 << 20:
size_val = 3;
break;
case 16 << 20:
size_val = 4;
break;
case 32 << 20:
size_val = 5;
break;
case 64 << 20:
size_val = 6;
break;
case 128 << 20:
size_val = 7;
break;
}
size_val = ffs(gd->bd->bi_flashsize) - 21;
pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
mtdcr(ebccfga, pb3cr);
@ -197,7 +168,7 @@ int misc_init_r(void)
* USB suff...
*/
#ifdef CONFIG_440EPX
if (act == NULL || strcmp(act, "hostdev") == 0) {
if (act == NULL || strcmp(act, "hostdev") == 0) {
/* SDR Setting */
mfsdr(SDR0_PFC1, sdr0_pfc1);
mfsdr(SDR0_USB2D0CR, usb2d0cr);
@ -205,27 +176,32 @@ int misc_init_r(void)
mfsdr(SDR0_USB2H0CR, usb2h0cr);
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ; /*1*/
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ;
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; /*0*/
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1*/
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1*/
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
/* An 8-bit/60MHz interface is the only possible alternative
when connecting the Device to the PHY */
/*
* An 8-bit/60MHz interface is the only possible alternative
* when connecting the Device to the PHY
*/
usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ; /*1*/
usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ;
/* To enable the USB 2.0 Device function through the UTMI interface */
/*
* To enable the USB 2.0 Device function
* through the UTMI interface
*/
usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
usb2d0cr = usb2d0cr | SDR0_USB2D0CR_USB2DEV_SELECTION; /*1*/
usb2d0cr = usb2d0cr | SDR0_USB2D0CR_USB2DEV_SELECTION;
sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL; /*0*/
sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL;
mtsdr(SDR0_PFC1, sdr0_pfc1);
mtsdr(SDR0_USB2D0CR, usb2d0cr);
@ -245,13 +221,13 @@ int misc_init_r(void)
mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; /*0*/
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1*/
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1*/
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
udelay (1000);
@ -276,31 +252,31 @@ int misc_init_r(void)
mfsdr(SDR0_PFC1, sdr0_pfc1);
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ; /*0*/
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ;
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN; /*1*/
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN;
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_DEV; /*0*/
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_DEV;
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_DEV; /*0*/
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_DEV;
usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_8BIT_60MHZ; /*0*/
usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_8BIT_60MHZ;
usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
usb2d0cr = usb2d0cr | SDR0_USB2D0CR_EBC_SELECTION; /*0*/
usb2d0cr = usb2d0cr | SDR0_USB2D0CR_EBC_SELECTION;
sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL; /*1*/
sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL;
mtsdr(SDR0_USB2H0CR, usb2h0cr);
mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
mtsdr(SDR0_USB2D0CR, usb2d0cr);
mtsdr(SDR0_PFC1, sdr0_pfc1);
/*clear resets*/
/* clear resets */
udelay (1000);
mtsdr(SDR0_SRST1, 0x00000000);
udelay (1000);
@ -398,43 +374,42 @@ void sequoia_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
}
#endif
/*************************************************************************
* pci_pre_init
/*
* pci_pre_init
*
* This routine is called just prior to registering the hose and gives
* the board the opportunity to check things. Returning a value of zero
* indicates that things are bad & PCI initialization should be aborted.
* This routine is called just prior to registering the hose and gives
* the board the opportunity to check things. Returning a value of zero
* indicates that things are bad & PCI initialization should be aborted.
*
* Different boards may wish to customize the pci controller structure
* (add regions, override default access routines, etc) or perform
* certain pre-initialization actions.
*
************************************************************************/
* Different boards may wish to customize the pci controller structure
* (add regions, override default access routines, etc) or perform
* certain pre-initialization actions.
*/
#if defined(CONFIG_PCI)
int pci_pre_init(struct pci_controller *hose)
{
unsigned long addr;
/*-------------------------------------------------------------------------+
| Set priority for all PLB3 devices to 0.
| Set PLB3 arbiter to fair mode.
+-------------------------------------------------------------------------*/
/*
* Set priority for all PLB3 devices to 0.
* Set PLB3 arbiter to fair mode.
*/
mfsdr(sdr_amp1, addr);
mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
addr = mfdcr(plb3_acr);
mtdcr(plb3_acr, addr | 0x80000000);
/*-------------------------------------------------------------------------+
| Set priority for all PLB4 devices to 0.
+-------------------------------------------------------------------------*/
/*
* Set priority for all PLB4 devices to 0.
*/
mfsdr(sdr_amp0, addr);
mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */
mtdcr(plb4_acr, addr);
/*-------------------------------------------------------------------------+
| Set Nebula PLB4 arbiter to fair mode.
+-------------------------------------------------------------------------*/
/*
* Set Nebula PLB4 arbiter to fair mode.
*/
/* Segment0 */
addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
@ -456,47 +431,51 @@ int pci_pre_init(struct pci_controller *hose)
}
#endif /* defined(CONFIG_PCI) */
/*************************************************************************
* pci_target_init
/*
* pci_target_init
*
* The bootstrap configuration provides default settings for the pci
* inbound map (PIM). But the bootstrap config choices are limited and
* may not be sufficient for a given board.
*
************************************************************************/
* The bootstrap configuration provides default settings for the pci
* inbound map (PIM). But the bootstrap config choices are limited and
* may not be sufficient for a given board.
*/
#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
void pci_target_init(struct pci_controller *hose)
{
/*--------------------------------------------------------------------------+
/*
* Set up Direct MMIO registers
*--------------------------------------------------------------------------*/
/*--------------------------------------------------------------------------+
| PowerPC440EPX PCI Master configuration.
| Map one 1Gig range of PLB/processor addresses to PCI memory space.
| PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
| Use byte reversed out routines to handle endianess.
| Make this region non-prefetchable.
+--------------------------------------------------------------------------*/
out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
*/
/*
* PowerPC440EPX PCI Master configuration.
* Map one 1Gig range of PLB/processor addresses to PCI memory space.
* PLB address 0xA0000000-0xDFFFFFFF
* ==> PCI address 0xA0000000-0xDFFFFFFF
* Use byte reversed out routines to handle endianess.
* Make this region non-prefetchable.
*/
out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute */
/* - disabled b4 setting */
out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */
out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */
out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */
out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */
out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, */
/* and enable region */
out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute */
/* - disabled b4 setting */
out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */
out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */
out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */
out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */
out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, */
/* and enable region */
out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */
out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */
out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */
out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */
out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */
out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */
/*--------------------------------------------------------------------------+
/*
* Set up Configuration registers
*--------------------------------------------------------------------------*/
*/
/* Program the board's subsystem id/vendor id */
pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
@ -515,51 +494,46 @@ void pci_target_init(struct pci_controller *hose)
pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
}
#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
/*************************************************************************
* pci_master_init
*
************************************************************************/
#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
void pci_master_init(struct pci_controller *hose)
{
unsigned short temp_short;
/*--------------------------------------------------------------------------+
| Write the PowerPC440 EP PCI Configuration regs.
| Enable PowerPC440 EP to be a master on the PCI bus (PMM).
| Enable PowerPC440 EP to act as a PCI memory target (PTM).
+--------------------------------------------------------------------------*/
/*
* Write the PowerPC440 EP PCI Configuration regs.
* Enable PowerPC440 EP to be a master on the PCI bus (PMM).
* Enable PowerPC440 EP to act as a PCI memory target (PTM).
*/
pci_read_config_word(0, PCI_COMMAND, &temp_short);
pci_write_config_word(0, PCI_COMMAND,
temp_short | PCI_COMMAND_MASTER |
PCI_COMMAND_MEMORY);
}
#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
/*************************************************************************
* is_pci_host
/*
* is_pci_host
*
* This routine is called to determine if a pci scan should be
* performed. With various hardware environments (especially cPCI and
* PPMC) it's insufficient to depend on the state of the arbiter enable
* bit in the strap register, or generic host/adapter assumptions.
* This routine is called to determine if a pci scan should be
* performed. With various hardware environments (especially cPCI and
* PPMC) it's insufficient to depend on the state of the arbiter enable
* bit in the strap register, or generic host/adapter assumptions.
*
* Rather than hard-code a bad assumption in the general 440 code, the
* 440 pci code requires the board to decide at runtime.
* Rather than hard-code a bad assumption in the general 440 code, the
* 440 pci code requires the board to decide at runtime.
*
* Return 0 for adapter mode, non-zero for host (monarch) mode.
*
*
************************************************************************/
* Return 0 for adapter mode, non-zero for host (monarch) mode.
*/
#if defined(CONFIG_PCI)
int is_pci_host(struct pci_controller *hose)
{
/* Cactus is always configured as host. */
return (1);
}
#endif /* defined(CONFIG_PCI) */
#endif /* defined(CONFIG_PCI) */
#if defined(CONFIG_POST)
/*
* Returns 1 if keys pressed to start the power-on long-running tests

51
board/esd/du440/Makefile Normal file
View File

@ -0,0 +1,51 @@
#
# (C) Copyright 2002-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS = $(BOARD).o
SOBJS = init.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

37
board/esd/du440/config.mk Normal file
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@ -0,0 +1,37 @@
#
# (C) Copyright 2002
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
ifndef TEXT_BASE
TEXT_BASE = 0xFFFA0000
endif
PLATFORM_CPPFLAGS += -DCONFIG_440=1
ifeq ($(debug),1)
PLATFORM_CPPFLAGS += -DDEBUG
endif
ifeq ($(dbcr),1)
PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
endif

1018
board/esd/du440/du440.c Normal file
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File diff suppressed because it is too large Load Diff

42
board/esd/du440/du440.h Normal file
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@ -0,0 +1,42 @@
/*
* (C) Copyright 2008
* Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#define SDR0_USB0 0x0320 /* USB Control Register */
#define CFG_GPIO0_EP_EEP (0x80000000 >> 23) /* GPIO0_23 */
#define CFG_GPIO1_DCF77 (0x80000000 >> (42-32)) /* GPIO1_42 */
#define CFG_GPIO1_IORSTN (0x80000000 >> (55-32)) /* GPIO1_55 */
#define CFG_GPIO1_HWVER_MASK 0x000000f0 /* GPIO1_56-59 */
#define CFG_GPIO1_HWVER_SHIFT 4
#define CFG_GPIO1_LEDUSR1 0x00000008 /* GPIO1_60 */
#define CFG_GPIO1_LEDUSR2 0x00000004 /* GPIO1_61 */
#define CFG_GPIO1_LEDPOST 0x00000002 /* GPIO1_62 */
#define CFG_GPIO1_LEDDU 0x00000001 /* GPIO1_63 */
#define CPLD_VERSION_MASK 0x0f
#define PWR_INT_FLAG 0x80
#define PWR_RDY 0x10
#define CPLD_IRQ (32+30)
#define PCI_VENDOR_ID_ESDGMBH 0x12fe
#define PCI_DEVICE_ID_DU440 0x0444

81
board/esd/du440/init.S Normal file
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@ -0,0 +1,81 @@
/*
* (C) Copyright 2008
* Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <ppc_asm.tmpl>
#include <asm-ppc/mmu.h>
#include <config.h>
/*
* TLB TABLE
*
* This table is used by the cpu boot code to setup the initial tlb
* entries. Rather than make broad assumptions in the cpu source tree,
* this table lets each board set things up however they like.
*
* Pointer to the table is returned in r1
*/
.section .bootpg,"ax"
.globl tlbtab
tlbtab:
tlbtab_start
/*
* BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
* speed up boot process. It is patched after relocation to enable SA_I
*/
tlbentry( CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 1, AC_R|AC_W|AC_X|SA_G )
#ifdef CFG_INIT_RAM_DCACHE
/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
tlbentry( CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G )
#endif
/* TLB-entry for PCI Memory */
tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 1, AC_R|AC_W|SA_G|SA_I )
tlbentry( CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 1, AC_R|AC_W|SA_G|SA_I )
tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 1, AC_R|AC_W|SA_G|SA_I )
tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 1, AC_R|AC_W|SA_G|SA_I )
/* TLB-entry for PCI IO */
tlbentry( CFG_PCI_IOBASE, SZ_64K, CFG_PCI_IOBASE, 1, AC_R|AC_W|SA_G|SA_I )
/* TLB-entries for EBC: CPLD, DUMEM, DUIO */
tlbentry( CFG_CPLD_BASE, SZ_1K, CFG_CPLD_BASE, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
tlbentry( CFG_DUMEM_BASE, SZ_1M, CFG_DUMEM_BASE, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
tlbentry( CFG_DUIO_BASE, SZ_64K, CFG_DUIO_BASE, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
/* TLB-entry for NAND */
tlbentry( CFG_NAND0_ADDR, SZ_1K, CFG_NAND0_ADDR, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
tlbentry( CFG_NAND1_ADDR, SZ_1K, CFG_NAND1_ADDR, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
/* TLB-entry for Internal Registers & OCM */
tlbentry( 0xe0000000, SZ_16M, 0xe0000000, 0, AC_R|AC_W|AC_X|SA_I )
/* TLB-entry PCI registers */
tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
/* TLB-entry for peripherals */
tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
tlbtab_end

145
board/esd/du440/u-boot.lds Normal file
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@ -0,0 +1,145 @@
/*
* (C) Copyright 2002
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(powerpc)
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
.resetvec 0xFFFFFFFC :
{
*(.resetvec)
} = 0xffff
.bootpg 0xFFFFF000 :
{
cpu/ppc4xx/start.o (.bootpg)
} = 0xffff
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
cpu/ppc4xx/start.o (.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss (NOLOAD) :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
}
ppcenv_assert = ASSERT(. < 0xFFFF8000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CFG_MONITOR_BASE, CFG_MONITOR_LEN and TEXT_BASE may need to be modified.");
_end = . ;
PROVIDE (end = .);
}

305
board/korat/korat.c
View File

@ -2,12 +2,12 @@
* (C) Copyright 2007-2008
* Larry Johnson, lrj@acm.org
*
* (C) Copyright 2006
* (C) Copyright 2006-2008
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* (C) Copyright 2006
* Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
* Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
* Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
@ -26,15 +26,16 @@
*/
#include <common.h>
#include <asm/gpio.h>
#include <asm/processor.h>
#include <asm-ppc/io.h>
#include <i2c.h>
#include <ppc440.h>
#include <asm/gpio.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <asm/bitops.h>
DECLARE_GLOBAL_DATA_PTR;
extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
ulong flash_get_size(ulong base, int banknum);
@ -47,9 +48,9 @@ int board_early_init_f(void)
mtdcr(ebccfga, xbcfg);
mtdcr(ebccfgd, 0xb8400000);
/*--------------------------------------------------------------------
/*
* Setup the interrupt controller polarities, triggers, etc.
*-------------------------------------------------------------------*/
*/
mtdcr(uic0sr, 0xffffffff); /* clear all */
mtdcr(uic0er, 0x00000000); /* disable all */
mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */
@ -101,10 +102,10 @@ int board_early_init_f(void)
/* select Ethernet pins */
mfsdr(SDR0_PFC1, sdr0_pfc1);
sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |
SDR0_PFC1_SELECT_CONFIG_4;
SDR0_PFC1_SELECT_CONFIG_4;
mfsdr(SDR0_PFC2, sdr0_pfc2);
sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
SDR0_PFC2_SELECT_CONFIG_4;
SDR0_PFC2_SELECT_CONFIG_4;
mtsdr(SDR0_PFC2, sdr0_pfc2);
mtsdr(SDR0_PFC1, sdr0_pfc1);
@ -221,9 +222,6 @@ static void set_mac_addresses(void)
}
}
/*---------------------------------------------------------------------------+
| misc_init_r.
+---------------------------------------------------------------------------*/
int misc_init_r(void)
{
uint pbcr;
@ -234,11 +232,7 @@ int misc_init_r(void)
unsigned long sdr0_pfc1;
char *act = getenv("usbact");
/*
* FLASH stuff...
*/
/* Re-do sizing to get full correct info */
/* Re-do flash sizing to get full correct info */
/* adjust flash start and offset */
gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
@ -246,32 +240,7 @@ int misc_init_r(void)
mtdcr(ebccfga, pb0cr);
pbcr = mfdcr(ebccfgd);
switch (gd->bd->bi_flashsize) {
case 1 << 20:
size_val = 0;
break;
case 2 << 20:
size_val = 1;
break;
case 4 << 20:
size_val = 2;
break;
case 8 << 20:
size_val = 3;
break;
case 16 << 20:
size_val = 4;
break;
case 32 << 20:
size_val = 5;
break;
case 64 << 20:
size_val = 6;
break;
case 128 << 20:
size_val = 7;
break;
}
size_val = ffs(gd->bd->bi_flashsize) - 21;
pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
mtdcr(ebccfga, pb0cr);
mtdcr(ebccfgd, pbcr);
@ -286,8 +255,7 @@ int misc_init_r(void)
&flash_info[0]);
/* Env protection ON by default */
(void)flash_protect(FLAG_PROTECT_SET,
CFG_ENV_ADDR_REDUND,
(void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR_REDUND,
CFG_ENV_ADDR_REDUND + 2 * CFG_ENV_SECT_SIZE - 1,
&flash_info[0]);
@ -301,35 +269,40 @@ int misc_init_r(void)
mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
mfsdr(SDR0_USB2H0CR, usb2h0cr);
usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_XOCLK_MASK;
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0 */
usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_WDINT_MASK;
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ; /*1 */
usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_DVBUS_MASK;
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; /*0 */
usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_DWNSTR_MASK;
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1 */
usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_UTMICN_MASK;
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1 */
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ;
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
/* An 8-bit/60MHz interface is the only possible alternative
when connecting the Device to the PHY */
usb2h0cr = usb2h0cr & ~SDR0_USB2H0CR_WDINT_MASK;
usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ; /*1 */
/*
* An 8-bit/60MHz interface is the only possible alternative
* when connecting the Device to the PHY
*/
usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ;
/* To enable the USB 2.0 Device function through the UTMI interface */
usb2d0cr = usb2d0cr & ~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
usb2d0cr = usb2d0cr | SDR0_USB2D0CR_USB2DEV_SELECTION; /*1 */
/*
* To enable the USB 2.0 Device function
* through the UTMI interface
*/
usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
usb2d0cr = usb2d0cr | SDR0_USB2D0CR_USB2DEV_SELECTION;
sdr0_pfc1 = sdr0_pfc1 & ~SDR0_PFC1_UES_MASK;
sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL; /*0 */
sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL;
mtsdr(SDR0_PFC1, sdr0_pfc1);
mtsdr(SDR0_USB2D0CR, usb2d0cr);
mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
mtsdr(SDR0_USB2H0CR, usb2h0cr);
/*clear resets */
/* clear resets */
udelay(1000);
mtsdr(SDR0_SRST1, 0x00000000);
udelay(1000);
@ -341,14 +314,14 @@ int misc_init_r(void)
/*-------------------PATCH-------------------------------*/
mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_XOCLK_MASK;
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0 */
usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_DVBUS_MASK;
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; /*0 */
usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_DWNSTR_MASK;
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1 */
usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_UTMICN_MASK;
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1 */
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
udelay(1000);
@ -372,32 +345,32 @@ int misc_init_r(void)
mfsdr(SDR0_USB2D0CR, usb2d0cr);
mfsdr(SDR0_PFC1, sdr0_pfc1);
usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_XOCLK_MASK;
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0 */
usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_WDINT_MASK;
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ; /*0 */
usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_DVBUS_MASK;
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN; /*1 */
usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_DWNSTR_MASK;
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_DEV; /*0 */
usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_UTMICN_MASK;
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_DEV; /*0 */
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ;
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN;
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_DEV;
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_DEV;
usb2h0cr = usb2h0cr & ~SDR0_USB2H0CR_WDINT_MASK;
usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_8BIT_60MHZ; /*0 */
usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_8BIT_60MHZ;
usb2d0cr = usb2d0cr & ~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
usb2d0cr = usb2d0cr | SDR0_USB2D0CR_EBC_SELECTION; /*0 */
usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
usb2d0cr = usb2d0cr | SDR0_USB2D0CR_EBC_SELECTION;
sdr0_pfc1 = sdr0_pfc1 & ~SDR0_PFC1_UES_MASK;
sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL; /*1 */
sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL;
mtsdr(SDR0_USB2H0CR, usb2h0cr);
mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
mtsdr(SDR0_USB2D0CR, usb2d0cr);
mtsdr(SDR0_PFC1, sdr0_pfc1);
/*clear resets */
/* clear resets */
udelay(1000);
mtsdr(SDR0_SRST1, 0x00000000);
udelay(1000);
@ -406,7 +379,7 @@ int misc_init_r(void)
printf("USB: Device(int phy)\n");
}
mfsdr(SDR0_SRST1, reg); /* enable security/kasumi engines */
mfsdr(SDR0_SRST1, reg); /* enable security/kasumi engines */
reg &= ~(SDR0_SRST1_CRYP0 | SDR0_SRST1_KASU0);
mtsdr(SDR0_SRST1, reg);
@ -486,43 +459,42 @@ int testdram(void)
}
#endif /* defined(CFG_DRAM_TEST) */
/*************************************************************************
* pci_pre_init
/*
* pci_pre_init
*
* This routine is called just prior to registering the hose and gives
* the board the opportunity to check things. Returning a value of zero
* indicates that things are bad & PCI initialization should be aborted.
* This routine is called just prior to registering the hose and gives
* the board the opportunity to check things. Returning a value of zero
* indicates that things are bad & PCI initialization should be aborted.
*
* Different boards may wish to customize the pci controller structure
* (add regions, override default access routines, etc) or perform
* certain pre-initialization actions.
*
************************************************************************/
* Different boards may wish to customize the pci controller structure
* (add regions, override default access routines, etc) or perform
* certain pre-initialization actions.
*/
#if defined(CONFIG_PCI)
int pci_pre_init(struct pci_controller *hose)
{
unsigned long addr;
/*-------------------------------------------------------------------------+
| Set priority for all PLB3 devices to 0.
| Set PLB3 arbiter to fair mode.
+-------------------------------------------------------------------------*/
/*
* Set priority for all PLB3 devices to 0.
* Set PLB3 arbiter to fair mode.
*/
mfsdr(sdr_amp1, addr);
mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
addr = mfdcr(plb3_acr);
mtdcr(plb3_acr, addr | 0x80000000);
/*-------------------------------------------------------------------------+
| Set priority for all PLB4 devices to 0.
+-------------------------------------------------------------------------*/
/*
* Set priority for all PLB4 devices to 0.
*/
mfsdr(sdr_amp0, addr);
mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */
mtdcr(plb4_acr, addr);
/*-------------------------------------------------------------------------+
| Set Nebula PLB4 arbiter to fair mode.
+-------------------------------------------------------------------------*/
/*
* Set Nebula PLB4 arbiter to fair mode.
*/
/* Segment0 */
addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
@ -541,47 +513,51 @@ int pci_pre_init(struct pci_controller *hose)
}
#endif /* defined(CONFIG_PCI) */
/*************************************************************************
* pci_target_init
/*
* pci_target_init
*
* The bootstrap configuration provides default settings for the pci
* inbound map (PIM). But the bootstrap config choices are limited and
* may not be sufficient for a given board.
*
************************************************************************/
* The bootstrap configuration provides default settings for the pci
* inbound map (PIM). But the bootstrap config choices are limited and
* may not be sufficient for a given board.
*/
#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
void pci_target_init(struct pci_controller *hose)
{
/*--------------------------------------------------------------------------+
/*
* Set up Direct MMIO registers
*--------------------------------------------------------------------------*/
/*--------------------------------------------------------------------------+
| PowerPC440EPX PCI Master configuration.
| Map one 1Gig range of PLB/processor addresses to PCI memory space.
| PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
| Use byte reversed out routines to handle endianess.
| Make this region non-prefetchable.
+--------------------------------------------------------------------------*/
out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
*/
/*
* PowerPC440EPX PCI Master configuration.
* Map one 1Gig range of PLB/processor addresses to PCI memory space.
* PLB address 0xA0000000-0xDFFFFFFF
* ==> PCI address 0xA0000000-0xDFFFFFFF
* Use byte reversed out routines to handle endianess.
* Make this region non-prefetchable.
*/
out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute */
/* - disabled b4 setting */
out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */
out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */
out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */
out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */
out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, */
/* and enable region */
out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */
out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */
out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute */
/* - disabled b4 setting */
out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */
out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */
out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */
out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, */
/* and enable region */
out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */
out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */
out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */
out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */
out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */
out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */
/*--------------------------------------------------------------------------+
/*
* Set up Configuration registers
*--------------------------------------------------------------------------*/
*/
/* Program the board's subsystem id/vendor id */
pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
@ -599,27 +575,24 @@ void pci_target_init(struct pci_controller *hose)
pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
/*--------------------------------------------------------------------------+
* Set up Configuration registers for on-board NEC uPD720101 USB controller
*--------------------------------------------------------------------------*/
/*
* Set up Configuration registers for on-board NEC uPD720101 USB
* controller.
*/
pci_write_config_dword(PCI_BDF(0x0, 0xC, 0x0), 0xE4, 0x00000020);
}
#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
/*************************************************************************
* pci_master_init
*
************************************************************************/
#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
void pci_master_init(struct pci_controller *hose)
{
unsigned short temp_short;
/*--------------------------------------------------------------------------+
| Write the PowerPC440 EP PCI Configuration regs.
| Enable PowerPC440 EP to be a master on the PCI bus (PMM).
| Enable PowerPC440 EP to act as a PCI memory target (PTM).
+--------------------------------------------------------------------------*/
/*
* Write the PowerPC440 EP PCI Configuration regs.
* Enable PowerPC440 EP to be a master on the PCI bus (PMM).
* Enable PowerPC440 EP to act as a PCI memory target (PTM).
*/
pci_read_config_word(0, PCI_COMMAND, &temp_short);
pci_write_config_word(0, PCI_COMMAND,
temp_short | PCI_COMMAND_MASTER |
@ -627,28 +600,26 @@ void pci_master_init(struct pci_controller *hose)
}
#endif
/*************************************************************************
* is_pci_host
/*
* is_pci_host
*
* This routine is called to determine if a pci scan should be
* performed. With various hardware environments (especially cPCI and
* PPMC) it's insufficient to depend on the state of the arbiter enable
* bit in the strap register, or generic host/adapter assumptions.
* This routine is called to determine if a pci scan should be
* performed. With various hardware environments (especially cPCI and
* PPMC) it's insufficient to depend on the state of the arbiter enable
* bit in the strap register, or generic host/adapter assumptions.
*
* Rather than hard-code a bad assumption in the general 440 code, the
* 440 pci code requires the board to decide at runtime.
* Rather than hard-code a bad assumption in the general 440 code, the
* 440 pci code requires the board to decide at runtime.
*
* Return 0 for adapter mode, non-zero for host (monarch) mode.
*
*
************************************************************************/
* Return 0 for adapter mode, non-zero for host (monarch) mode.
*/
#if defined(CONFIG_PCI)
int is_pci_host(struct pci_controller *hose)
{
/* Korat is always configured as host. */
return (1);
}
#endif
#endif /* defined(CONFIG_PCI) */
#if defined(CONFIG_POST)
/*
@ -657,6 +628,6 @@ int is_pci_host(struct pci_controller *hose)
*/
int post_hotkeys_pressed(void)
{
return 0; /* No hotkeys supported */
return 0; /* No hotkeys supported */
}
#endif
#endif /* CONFIG_POST */

105
board/netstal/common/fixed_sdram.c Normal file
View File

@ -0,0 +1,105 @@
/*
*(C) Copyright 2005-2008 Netstal Maschinen AG
* Niklaus Giger (Niklaus.Giger@netstal.com)
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#include <common.h>
#include <ppc4xx.h>
#include <asm/processor.h>
#include "nm.h"
#if defined(DEBUG)
void show_sdram_registers(void)
{
u32 value;
printf("SDRAM Controller Registers --\n");
mfsdram(mem_mcopt1, value);
printf(" SDRAM0_CFG : 0x%08x\n", value);
mfsdram(mem_status, value);
printf(" SDRAM0_STATUS: 0x%08x\n", value);
mfsdram(mem_mb0cf, value);
printf(" SDRAM0_B0CR : 0x%08x\n", value);
mfsdram(mem_mb1cf, value);
printf(" SDRAM0_B1CR : 0x%08x\n", value);
mfsdram(mem_sdtr1, value);
printf(" SDRAM0_TR : 0x%08x\n", value);
mfsdram(mem_rtr, value);
printf(" SDRAM0_RTR : 0x%08x\n", value);
}
#endif
long int fixed_hcu4_sdram (unsigned int dram_size)
{
#ifdef DEBUG
printf(__FUNCTION__);
#endif
/* disable memory controller */
mtsdram(mem_mcopt1, 0x00000000);
udelay (500);
/* Clear SDRAM0_BESR0 (Bus Error Syndrome Register) */
mtsdram(mem_besra, 0xffffffff);
/* Clear SDRAM0_BESR1 (Bus Error Syndrome Register) */
mtsdram(mem_besrb, 0xffffffff);
/* Clear SDRAM0_ECCCFG (disable ECC) */
mtsdram(mem_ecccf, 0x00000000);
/* Clear SDRAM0_ECCESR (ECC Error Syndrome Register) */
mtsdram(mem_eccerr, 0xffffffff);
/* Timing register: CASL=2, PTA=2, CTP=2, LDF=1, RFTA=5, RCD=2
*/
mtsdram(mem_sdtr1, 0x008a4015);
/* Memory Bank 0 Config == BA=0x00000000, SZ=64M, AM=3, BE=1
* and refresh timer
*/
switch (dram_size >> 20) {
case 32:
mtsdram(mem_mb0cf, 0x00062001);
mtsdram(mem_rtr, 0x07F00000);
break;
case 64:
mtsdram(mem_mb0cf, 0x00084001);
mtsdram(mem_rtr, 0x04100000);
break;
case 128:
mtsdram(mem_mb0cf, 0x000A4001);
mtsdram(mem_rtr, 0x04100000);
break;
default:
printf("Invalid memory size of %d MB given\n", dram_size >> 20);
}
/* Power management idle timer set to the default. */
mtsdram(mem_pmit, 0x07c00000);
udelay (500);
/* Enable banks (DCE=1, BPRF=1, ECCDD=1, EMDUL=1) TODO */
mtsdram(mem_mcopt1, 0x90800000);
#ifdef DEBUG
printf("%s: done\n", __FUNCTION__);
#endif
return dram_size;
}

38
board/netstal/common/nm.h Normal file
View File

@ -0,0 +1,38 @@
/*
*(C) Copyright 2005-2007 Netstal Maschinen AG
* Niklaus Giger (Niklaus.Giger@netstal.com)
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
extern void hcu_led_set(u32 value);
extern u32 get_serial_number(void);
extern u32 hcu_get_slot(void);
extern int board_with_pci(void);
extern void nm_show_print(int generation, int index, int hw_capabilities);
extern void set_params_for_sw_install(int install_requested, char *board_name );
extern void common_misc_init_r(void);
enum {
/* HW_GENERATION_HCU1 is no longer supported */
HW_GENERATION_HCU2 = 0x10,
HW_GENERATION_HCU3 = 0x10,
HW_GENERATION_HCU4 = 0x20,
HW_GENERATION_HCU5 = 0x30,
HW_GENERATION_MCU = 0x08,
HW_GENERATION_MCU20 = 0x0a,
HW_GENERATION_MCU25 = 0x09,
};

128
board/netstal/common/nm_bsp.c
View File

@ -1,5 +1,5 @@
/*
*(C) Copyright 2005-2007 Netstal Maschinen AG
*(C) Copyright 2005-2008 Netstal Maschinen AG
* Niklaus Giger (Niklaus.Giger@netstal.com)
*
* This source code is free software; you can redistribute it
@ -20,22 +20,118 @@
#include <common.h>
#include <command.h>
#include <net.h>
#include "nm.h"
#ifdef CONFIG_CMD_BSP
/*
* Command nm_bsp: Netstal Maschinen BSP specific command
*/
int nm_bsp(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
DECLARE_GLOBAL_DATA_PTR;
#define DEFAULT_ETH_ADDR "ethaddr"
typedef struct {u8 id; char *name;} generation_info;
generation_info generations[7] = {
{HW_GENERATION_HCU2, "HCU2"},
{HW_GENERATION_HCU3, "HCU3"},
{HW_GENERATION_HCU4, "HCU4"},
{HW_GENERATION_HCU5, "HCU5"},
{HW_GENERATION_MCU, "MCU"},
{HW_GENERATION_MCU20, "MCU20"},
{HW_GENERATION_MCU25, "MCU25"},
};
void nm_show_print(int generation, int index, int hw_capabilities)
{
printf("%s: flag %d, argc %d, argv[0] %s\n", __FUNCTION__,
flag, argc, argv[0]);
printf("Netstal Maschinen BSP specific command. None at the moment.\n");
return 0;
int j;
char *generationName=0;
/* reset ANSI terminal color mode */
printf("\x1B""[0m""Netstal Maschinen AG: ");
for (j=0; j < (sizeof(generations)/sizeof(generations[0])); j++) {
if (generations[j].id == generation) {
generationName = generations[j].name;
break;
}
}
printf("%s: index %d HW 0x%x\n", generationName, index, hw_capabilities);
for (j = 0;j < 6; j++) {
hcu_led_set(1 << j);
udelay(200 * 1000);
}
}
void set_params_for_sw_install(int install_requested, char *board_name )
{
if (install_requested) {
char string[128];
printf("\n\n%s SW-Installation: %d patching boot parameters\n",
board_name, install_requested);
setenv("bootdelay", "0");
setenv("loadaddr", "0x01000000");
setenv("serverip", "172.25.1.1");
setenv("bootcmd", "run install");
sprintf(string, "tftp ${loadaddr} admin/sw_on_hd; "
"tftp ${loadaddr} installer/%s_sw_inst; "
"run boot_sw_inst", board_name);
setenv("install", string);
sprintf(string, "setenv bootargs emac(0,0)c:%s/%s_sw_inst "
"e=${ipaddr} h=${serverip} f=0x1000; "
"bootvx ${loadaddr}\0",
board_name, board_name);
setenv("boot_sw_inst", string);
}
}
void common_misc_init_r(void)
{
char *s = getenv(DEFAULT_ETH_ADDR);
char *e;
int i;
u32 serial = get_serial_number();
IPaddr_t ipaddr;
char *ipstring;
for (i = 0; i < 6; ++i) {
gd->bd->bi_enetaddr[i] = s ? simple_strtoul(s, &e, 16) : 0;
if (s)
s = (*e) ? e + 1 : e;
}
if (gd->bd->bi_enetaddr[3] == 0 &&
gd->bd->bi_enetaddr[4] == 0 &&
gd->bd->bi_enetaddr[5] == 0) {
char ethaddr[22];
/* Must be in sync with CONFIG_ETHADDR */
gd->bd->bi_enetaddr[0] = 0x00;
gd->bd->bi_enetaddr[1] = 0x60;
gd->bd->bi_enetaddr[2] = 0x13;
gd->bd->bi_enetaddr[3] = (serial >> 16) & 0xff;
gd->bd->bi_enetaddr[4] = (serial >> 8) & 0xff;
gd->bd->bi_enetaddr[5] = hcu_get_slot();
sprintf(ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X\0",
gd->bd->bi_enetaddr[0], gd->bd->bi_enetaddr[1],
gd->bd->bi_enetaddr[2], gd->bd->bi_enetaddr[3],
gd->bd->bi_enetaddr[4], gd->bd->bi_enetaddr[5]) ;
printf("%s: Setting eth %s serial 0x%x\n", __FUNCTION__,
ethaddr, serial);
setenv(DEFAULT_ETH_ADDR, ethaddr);
}
/* IP-Adress update */
ipstring = getenv("ipaddr");
if (ipstring == 0)
ipaddr = string_to_ip("172.25.1.99");
else
ipaddr = string_to_ip(ipstring);
if ((ipaddr & 0xff) != (32 + hcu_get_slot())) {
char tmp[22];
ipaddr = (ipaddr & 0xffffff00) + 32 + hcu_get_slot();
ip_to_string (ipaddr, tmp);
printf("%s: enforce %s\n", __FUNCTION__, tmp);
setenv("ipaddr", tmp);
saveenv();
}
}
U_BOOT_CMD(
nm_bsp, 1, 1, nm_bsp,
"nm_bsp - Netstal Maschinen BSP specific command. \n",
"Help for Netstal Maschinen BSP specific command.\n"
);
#endif

6
board/netstal/hcu4/Makefile
View File

@ -22,14 +22,16 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
vpath fixed_sdram.c ../common
vpath hcu_flash.c ../common
vpath nm_bsp.c ../common
# NOBJS : Netstal common objects
NOBJS = hcu_flash.o
NOBJS = ../common/fixed_sdram.o ../common/hcu_flash.o ../common/nm_bsp.o
COBJS = $(BOARD).o
SOBJS =
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) ../common/$(NOBJS:.o=.c)
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) $(NOBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
NOBJS := $(addprefix $(obj),$(NOBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))

2
board/netstal/hcu4/config.mk
View File

@ -21,7 +21,7 @@
# Netstal Maschinen AG: HCU4 boards
#
TEXT_BASE = 0xFFFa0000
TEXT_BASE = 0xFFFB0000
ifeq ($(debug),1)
PLATFORM_CPPFLAGS += -DDEBUG -g

341
board/netstal/hcu4/hcu4.c
View File

@ -23,36 +23,21 @@
#include <asm/processor.h>
#include <asm/io.h>
#include <asm-ppc/u-boot.h>
#include "../common/nm_bsp.c"
#include "../common/nm.h"
DECLARE_GLOBAL_DATA_PTR;
#define HCU_MACH_VERSIONS_REGISTER (0x7C000000 + 0xF00000)
#define SYS_SLOT_ADDRESS (0x7C000000 + 0x400000)
#define HCU3_DIGITAL_IO_REGISTER (0x7C000000 + 0x500000)
#define HCU_SW_INSTALL_REQUESTED 0x10
#define SDRAM_LEN 32*1024*1024 /* 32 MB -RAM */
#define DO_UGLY_SDRAM_WORKAROUND
enum {
/* HW_GENERATION_HCU wird nicht mehr unterstuetzt */
HW_GENERATION_HCU2 = 0x10,
HW_GENERATION_HCU3 = 0x10,
HW_GENERATION_HCU4 = 0x20,
HW_GENERATION_MCU = 0x08,
HW_GENERATION_MCU20 = 0x0a,
HW_GENERATION_MCU25 = 0x09,
};
void hcu_led_set(u32 value);
long int spd_sdram(int(read_spd)(uint addr));
#ifdef CONFIG_SPD_EEPROM
#define DEBUG
#endif
#undef DEBUG
#if defined(DEBUG)
void show_sdram_registers(void);
#endif
long int fixed_hcu4_sdram (unsigned int dram_size);
/*
* This function is run very early, out of flash, and before devices are
@ -69,6 +54,7 @@ void show_sdram_registers(void);
/* Attention: If you want 1 microsecs times from the external oscillator
* use 0x00804051. But this causes problems with u-boot and linux!
*/
#define CPC0_CR0_VALUE 0x0030103c
#define CPC0_CR1_VALUE 0x00004051
#define CPC0_ECR 0xaa /* Edge condition register */
#define EBC0_CFG 0x23 /* External Peripheral Control Register */
@ -77,18 +63,18 @@ void show_sdram_registers(void);
int board_early_init_f (void)
{
/*-------------------------------------------------------------------+
| Interrupt controller setup for the HCU4 board.
| Note: IRQ 0-15 405GP internally generated; high; level sensitive
| IRQ 16 405GP internally generated; low; level sensitive
| IRQ 17-24 RESERVED/UNUSED
| IRQ 31 (EXT IRQ 6) (unused)
+-------------------------------------------------------------------*/
/*
* Interrupt controller setup for the HCU4 board.
* Note: IRQ 0-15 405GP internally generated; high; level sensitive
* IRQ 16 405GP internally generated; low; level sensitive
* IRQ 17-24 RESERVED/UNUSED
* IRQ 31 (EXT IRQ 6) (unused)
*/
mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr (uicer, 0x00000000); /* disable all ints */
mtdcr (uiccr, 0x00000000); /* set all to be non-critical */
mtdcr (uicpr, 0xFFFFFF87); /* set int polarities */
mtdcr (uictr, 0x10000000); /* set int trigger levels */
mtdcr (uicpr, 0xFFFFE000); /* set int polarities */
mtdcr (uictr, 0x00000000); /* set int trigger levels */
mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(CPC0_CR1, CPC0_CR1_VALUE);
@ -105,47 +91,44 @@ int board_pre_init (void)
}
#endif
int sys_install_requested(void)
{
u16 *ioValuePtr = (u16 *)HCU3_DIGITAL_IO_REGISTER;
return (in_be16(ioValuePtr) & HCU_SW_INSTALL_REQUESTED) != 0;
}
int checkboard (void)
{
unsigned int j;
u16 *boardVersReg = (u16 *) HCU_MACH_VERSIONS_REGISTER;
u16 generation = *boardVersReg & 0xf0;
u16 index = *boardVersReg & 0x0f;
u16 *boardVersReg = (u16 *)HCU_MACH_VERSIONS_REGISTER;
u16 generation = in_be16(boardVersReg) & 0xf0;
u16 index = in_be16(boardVersReg) & 0x0f;
/* Cannot be done, in board_early_init */
mtdcr(CPC0_CR0, CPC0_CR0_VALUE);
/* Force /RTS to active. The board it not wired quite
correctly to use cts/rtc flow control, so just force the
/RST active and forget about it. */
* correctly to use cts/rtc flow control, so just force the
* /RST active and forget about it.
*/
writeb (readb (0xef600404) | 0x03, 0xef600404);
printf ("\nNetstal Maschinen AG ");
if (generation == HW_GENERATION_HCU3)
printf ("HCU3: index %d\n\n", index);
else if (generation == HW_GENERATION_HCU4)
printf ("HCU4: index %d\n\n", index);
hcu_led_set(0);
for (j = 0; j < 7; j++) {
hcu_led_set(1 << j);
udelay(50 * 1000);
}
nm_show_print(generation, index, 0);
return 0;
}
u32 hcu_led_get(void)
{
return (~((*(u32 *)GPIO0_OR)) >> 23) & 0xff;
return (~(in_be32((u32 *)GPIO0_OR)) >> 23) & 0xff;
}
/*---------------------------------------------------------------------------+
/*
* hcu_led_set value to be placed into the LEDs (max 6 bit)
*---------------------------------------------------------------------------*/
*/
void hcu_led_set(u32 value)
{
u32 tmp = ~value;
u32 *ledReg;
tmp = (tmp << 23) | 0x7FFFFF;
ledReg = (u32 *)GPIO0_OR;
*ledReg = tmp;
out_be32((u32 *)GPIO0_OR, tmp);
}
/*
@ -157,246 +140,72 @@ void sdram_init(void)
return;
}
#if defined(DEBUG)
void show_sdram_registers(void)
/*
* hcu_get_slot
*/
u32 hcu_get_slot(void)
{
u32 value;
printf ("SDRAM Controller Registers --\n");
mfsdram(mem_mcopt1, value);
printf (" SDRAM0_CFG : 0x%08x\n", value);
mfsdram(mem_status, value);
printf (" SDRAM0_STATUS: 0x%08x\n", value);
mfsdram(mem_mb0cf, value);
printf (" SDRAM0_B0CR : 0x%08x\n", value);
mfsdram(mem_mb1cf, value);
printf (" SDRAM0_B1CR : 0x%08x\n", value);
mfsdram(mem_sdtr1, value);
printf (" SDRAM0_TR : 0x%08x\n", value);
mfsdram(mem_rtr, value);
printf (" SDRAM0_RTR : 0x%08x\n", value);
u16 *slot = (u16 *)SYS_SLOT_ADDRESS;
return in_be16(slot) & 0x7f;
}
#endif
/*
* this is even after checkboard. It returns the size of the SDRAM
* that we have installed. This function is called by board_init_f
* in lib_ppc/board.c to initialize the memory and return what I
* found. These are default value, which will be overridden later.
* get_serial_number
*/
long int fixed_hcu4_sdram (int board_type)
{
#ifdef DEBUG
printf (__FUNCTION__);
#endif
/* disable memory controller */
mtdcr (memcfga, mem_mcopt1);
mtdcr (memcfgd, 0x00000000);
udelay (500);
/* Clear SDRAM0_BESR0 (Bus Error Syndrome Register) */
mtdcr (memcfga, mem_besra);
mtdcr (memcfgd, 0xffffffff);
/* Clear SDRAM0_BESR1 (Bus Error Syndrome Register) */
mtdcr (memcfga, mem_besrb);
mtdcr (memcfgd, 0xffffffff);
/* Clear SDRAM0_ECCCFG (disable ECC) */
mtdcr (memcfga, mem_ecccf);
mtdcr (memcfgd, 0x00000000);
/* Clear SDRAM0_ECCESR (ECC Error Syndrome Register) */
mtdcr (memcfga, mem_eccerr);
mtdcr (memcfgd, 0xffffffff);
/* Timing register: CASL=2, PTA=2, CTP=2, LDF=1, RFTA=5, RCD=2
* TODO ngngng
*/
mtdcr (memcfga, mem_sdtr1);
mtdcr (memcfgd, 0x008a4015);
/* Memory Bank 0 Config == BA=0x00000000, SZ=64M, AM=3, BE=1
* TODO ngngng
*/
mtdcr (memcfga, mem_mb0cf);
mtdcr (memcfgd, 0x00062001);
/* refresh timer = 0x400 */
mtdcr (memcfga, mem_rtr);
mtdcr (memcfgd, 0x04000000);
/* Power management idle timer set to the default. */
mtdcr (memcfga, mem_pmit);
mtdcr (memcfgd, 0x07c00000);
udelay (500);
/* Enable banks (DCE=1, BPRF=1, ECCDD=1, EMDUL=1) TODO */
mtdcr (memcfga, mem_mcopt1);
mtdcr (memcfgd, 0x90800000);
#ifdef DEBUG
printf ("%s: done\n", __FUNCTION__);
#endif
return SDRAM_LEN;
}
/*---------------------------------------------------------------------------+
* hcu_serial_number
*---------------------------------------------------------------------------*/
static u32 hcu_serial_number(void)
u32 get_serial_number(void)
{
u32 *serial = (u32 *)CFG_FLASH_BASE;
if (*serial == 0xffffffff)
return get_ticks();
if (in_be32(serial) == 0xffffffff)
return 0;
return *serial;
return in_be32(serial);
}
/*---------------------------------------------------------------------------+
/*
* misc_init_r.
*---------------------------------------------------------------------------*/
*/
int misc_init_r(void)
{
char *s = getenv("ethaddr");
char *e;
int i;
u32 serial = hcu_serial_number();
for (i = 0; i < 6; ++i) {
gd->bd->bi_enetaddr[i] = s ? simple_strtoul (s, &e, 16) : 0;
if (s)
s = (*e) ? e + 1 : e;
}
if (gd->bd->bi_enetaddr[3] == 0 &&
gd->bd->bi_enetaddr[4] == 0 &&
gd->bd->bi_enetaddr[5] == 0) {
char ethaddr[22];
/* [0..3] Must be in sync with CONFIG_ETHADDR */
gd->bd->bi_enetaddr[0] = 0x00;
gd->bd->bi_enetaddr[1] = 0x60;
gd->bd->bi_enetaddr[2] = 0x13;
gd->bd->bi_enetaddr[3] = (serial >> 16) & 0xff;
gd->bd->bi_enetaddr[4] = (serial >> 8) & 0xff;
gd->bd->bi_enetaddr[5] = (serial >> 0) & 0xff;
sprintf (ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X\0",
gd->bd->bi_enetaddr[0], gd->bd->bi_enetaddr[1],
gd->bd->bi_enetaddr[2], gd->bd->bi_enetaddr[3],
gd->bd->bi_enetaddr[4], gd->bd->bi_enetaddr[5]) ;
printf("%s: Setting eth %s serial 0x%x\n", __FUNCTION__,
ethaddr, serial);
setenv ("ethaddr", ethaddr);
}
common_misc_init_r();
set_params_for_sw_install( sys_install_requested(), "hcu4" );
return 0;
}
#ifdef DO_UGLY_SDRAM_WORKAROUND
#include "i2c.h"
void set_spd_default_value(unsigned int spd_addr,uchar def_val)
{
uchar value;
int res = i2c_read(SPD_EEPROM_ADDRESS, spd_addr, 1, &value, 1) ;
if (res == 0 && value == 0xff) {
res = i2c_write(SPD_EEPROM_ADDRESS,
spd_addr, 1, &def_val, 1) ;
#ifdef DEBUG
printf("%s: Setting spd offset %3d to %3d res %d\n",
__FUNCTION__, spd_addr, def_val, res);
#endif
}
}
#endif
long int initdram(int board_type)
{
long dram_size = 0;
#if !defined(CONFIG_SPD_EEPROM)
dram_size = fixed_hcu4_sdram();
#else
#ifdef DO_UGLY_SDRAM_WORKAROUND
/* Workaround if you have no working I2C-EEPROM-SPD-configuration */
i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
set_spd_default_value(2, 4); /* SDRAM Type */
set_spd_default_value(7, 0); /* module width, high byte */
set_spd_default_value(12, 1); /* Refresh or 0x81 */
/* Only correct for HCU3 with 32 MB RAM*/
/* Number of bytes used by module manufacturer */
set_spd_default_value( 0, 128);
set_spd_default_value( 1, 11 ); /* Total SPD memory size */
set_spd_default_value( 2, 4 ); /* Memory type */
set_spd_default_value( 3, 12 ); /* Number of row address bits */
set_spd_default_value( 4, 9 ); /* Number of column address bits */
set_spd_default_value( 5, 1 ); /* Number of module rows */
set_spd_default_value( 6, 32 ); /* Module data width, LSB */
set_spd_default_value( 7, 0 ); /* Module data width, MSB */
set_spd_default_value( 8, 1 ); /* Module interface signal levels */
/* SDRAM cycle time for highest CL (Tclk) */
set_spd_default_value( 9, 112);
/* SDRAM access time from clock for highest CL (Tac) */
set_spd_default_value(10, 84 );
set_spd_default_value(11, 2 ); /* Module configuration type */
set_spd_default_value(12, 128); /* Refresh rate/type */
set_spd_default_value(13, 16 ); /* Primary SDRAM width */
set_spd_default_value(14, 8 ); /* Error Checking SDRAM width */
/* SDRAM device attributes, min clock delay for back to back */
/*random column addresses (Tccd) */
set_spd_default_value(15, 1 );
/* SDRAM device attributes, burst lengths supported */
set_spd_default_value(16, 143);
/* SDRAM device attributes, number of banks on SDRAM device */
set_spd_default_value(17, 4 );
/* SDRAM device attributes, CAS latency */
set_spd_default_value(18, 6 );
/* SDRAM device attributes, CS latency */
set_spd_default_value(19, 1 );
/* SDRAM device attributes, WE latency */
set_spd_default_value(20, 1 );
set_spd_default_value(21, 0 ); /* SDRAM module attributes */
/* SDRAM device attributes, general */
set_spd_default_value(22, 14 );
/* SDRAM cycle time for 2nd highest CL (Tclk) */
set_spd_default_value(23, 117);
/* SDRAM access time from clock for2nd highest CL (Tac) */
set_spd_default_value(24, 84 );
/* SDRAM cycle time for 3rd highest CL (Tclk) */
set_spd_default_value(25, 0 );
/* SDRAM access time from clock for3rd highest CL (Tac) */
set_spd_default_value(26, 0 );
set_spd_default_value(27, 15 ); /* Minimum row precharge time (Trp) */
/* Minimum row active to row active delay (Trrd) */
set_spd_default_value(28, 14 );
set_spd_default_value(29, 15 ); /* Minimum CAS to RAS delay (Trcd) */
set_spd_default_value(30, 37 ); /* Minimum RAS pulse width (Tras) */
set_spd_default_value(31, 8 ); /* Module bank density */
/* Command and Address signal input setup time */
set_spd_default_value(32, 21 );
/* Command and Address signal input hold time */
set_spd_default_value(33, 8 );
set_spd_default_value(34, 21 ); /* Data signal input setup time */
set_spd_default_value(35, 8 ); /* Data signal input hold time */
#endif /* DO_UGLY_SDRAM_WORKAROUND */
dram_size = spd_sdram(0);
#endif
u16 *boardVersReg = (u16 *) HCU_MACH_VERSIONS_REGISTER;
u16 generation = in_be16(boardVersReg) & 0xf0;
if (generation == HW_GENERATION_HCU3)
dram_size = 32*1024*1024;
else dram_size = 64*1024*1024;
fixed_hcu4_sdram(dram_size);
#ifdef DEBUG
show_sdram_registers();
#endif
#if defined(CFG_DRAM_TEST)
bcu4_testdram(dram_size);
printf("%s %d MB of SDRAM\n", __FUNCTION__, dram_size/(1024*1024));
#endif
return dram_size;
}
#if defined(CONFIG_POST)
/*
* Returns 1 if keys pressed to start the power-on long-running tests
* Called from board_init_f().
*/
int post_hotkeys_pressed(void)
{
return 0; /* No hotkeys supported */
}
#endif /* CONFIG_POST */
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
void ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
}
#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */

5
board/netstal/hcu5/Makefile
View File

@ -23,13 +23,14 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
vpath hcu_flash.c ../common
vpath nm_bsp.c ../common
# NOBJS : Netstal common objects
NOBJS = hcu_flash.o
NOBJS = ../common/hcu_flash.o ../common/nm_bsp.o
COBJS = $(BOARD).o sdram.o
SOBJS = init.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) ../common/$(NOBJS:.o=.c)
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) $(NOBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
NOBJS := $(addprefix $(obj),$(NOBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))

3
board/netstal/hcu5/README.txt
View File

@ -10,9 +10,6 @@ TODO:
- Fix RTS/CTS problem (HW?)
CONFIG_SERIAL_MULTI/CONFIG_SERIAL_SOFTWARE_FIFO hangs after
Switching to interrupt driven serial input mode
- Make vxWorks start from u-boot. Possible reasons
- Does vxWorks need an entry for the Machine Check interrupt like this
tlbentry( 0x40000000, SZ_256M, 0, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) ?
Caveats:
--------

2
board/netstal/hcu5/config.mk
View File

@ -21,7 +21,7 @@
# Netstal Maschinen AG: HCU5 boards
#
TEXT_BASE = 0xFFFa0000
TEXT_BASE = 0xFFFB0000
PLATFORM_CPPFLAGS += -DCONFIG_440=1

289
board/netstal/hcu5/hcu5.c
View File

@ -1,5 +1,5 @@
/*
*(C) Copyright 2005-2007 Netstal Maschinen AG
*(C) Copyright 2005-2008 Netstal Maschinen AG
* Niklaus Giger (Niklaus.Giger@netstal.com)
*
* This source code is free software; you can redistribute it
@ -21,13 +21,11 @@
#include <common.h>
#include <asm/processor.h>
#include <ppc440.h>
#include <asm/mmu.h>
#include <net.h>
#include <asm/io.h>
#include "../common/nm.h"
DECLARE_GLOBAL_DATA_PTR;
void hcu_led_set(u32 value);
extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
#undef BOOTSTRAP_OPTION_A_ACTIVE
@ -42,23 +40,10 @@ extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
#define SDR0_ECID2 0x0082
#define SDR0_ECID3 0x0083
#define SYS_IO_ADDRESS (CFG_CS_2 + 0x00e00000)
#define SYS_IO_ADDRESS (CFG_CS_2 + 0x00e00000)
#define SYS_SLOT_ADDRESS (CFG_CPLD + 0x00400000)
#define DEFAULT_ETH_ADDR "ethaddr"
/* ethaddr for first or etha1ddr for second ethernet */
enum {
/* HW_GENERATION_HCU1 is no longer supported */
HW_GENERATION_HCU2 = 0x10,
HW_GENERATION_HCU3 = 0x10,
HW_GENERATION_HCU4 = 0x20,
HW_GENERATION_HCU5 = 0x30,
HW_GENERATION_MCU = 0x08,
HW_GENERATION_MCU20 = 0x0a,
HW_GENERATION_MCU25 = 0x09,
};
#define HCU_DIGITAL_IO_REGISTER (CFG_CPLD + 0x0500000)
#define HCU_SW_INSTALL_REQUESTED 0x10
/*
* This function is run very early, out of flash, and before devices are
@ -72,7 +57,6 @@ enum {
int board_early_init_f(void)
{
u32 reg;
#ifdef BOOTSTRAP_OPTION_A_ACTIVE
/* Booting with Bootstrap Option A
@ -113,10 +97,9 @@ int board_early_init_f(void)
mtdcr(ebccfga, xbcfg);
mtdcr(ebccfgd, 0xb8400000);
/*--------------------------------------------------------------------
/*
* Setup the GPIO pins
*-------------------------------------------------------------------*/
/* test-only: take GPIO init from pcs440ep ???? in config file */
*/
out32(GPIO0_OR, 0x00000000);
out32(GPIO0_TCR, 0x7C2FF1CF);
out32(GPIO0_OSRL, 0x40055000);
@ -143,9 +126,9 @@ int board_early_init_f(void)
out32(GPIO1_ISR3L, 0x00000000);
out32(GPIO1_ISR3H, 0x00000000);
/*--------------------------------------------------------------------
/*
* Setup the interrupt controller polarities, triggers, etc.
*-------------------------------------------------------------------*/
*/
mtdcr(uic0sr, 0xffffffff); /* clear all */
mtdcr(uic0er, 0x00000000); /* disable all */
mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */
@ -172,12 +155,6 @@ int board_early_init_f(void)
mtsdr(sdr_pfc0, 0x00003E00); /* Pin function: */
mtsdr(sdr_pfc1, 0x00848000); /* Pin function: UART0 has 4 pins */
/* PCI arbiter enabled */
mfsdr(sdr_pci0, reg);
mtsdr(sdr_pci0, 0x80000000 | reg);
pci_pre_init(0);
/* setup BOOT FLASH */
mtsdr(SDR0_CUST0, 0xC0082350);
@ -192,33 +169,27 @@ int board_pre_init(void)
#endif
int sys_install_requested(void)
{
u16 *ioValuePtr = (u16 *)HCU_DIGITAL_IO_REGISTER;
return (in_be16(ioValuePtr) & HCU_SW_INSTALL_REQUESTED) != 0;
}
int checkboard(void)
{
unsigned int j;
u16 *hwVersReg = (u16 *) HCU_HW_VERSION_REGISTER;
u16 *boardVersReg = (u16 *) HCU_CPLD_VERSION_REGISTER;
u16 generation = *boardVersReg & 0xf0;
u16 index = *boardVersReg & 0x0f;
u16 generation = in_be16(boardVersReg) & 0xf0;
u16 index = in_be16(boardVersReg) & 0x0f;
u32 ecid0, ecid1, ecid2, ecid3;
printf("Netstal Maschinen AG: ");
if (generation == HW_GENERATION_HCU3)
printf("HCU3: index %d", index);
else if (generation == HW_GENERATION_HCU4)
printf("HCU4: index %d", index);
else if (generation == HW_GENERATION_HCU5)
printf("HCU5: index %d", index);
printf(" HW 0x%02x\n", *hwVersReg & 0xff);
nm_show_print(generation, index, in_be16(hwVersReg) & 0xff);
mfsdr(SDR0_ECID0, ecid0);
mfsdr(SDR0_ECID1, ecid1);
mfsdr(SDR0_ECID2, ecid2);
mfsdr(SDR0_ECID3, ecid3);
printf("Chip ID 0x%x 0x%x 0x%x 0x%x\n", ecid0, ecid1, ecid2, ecid3);
for (j = 0;j < 6; j++) {
hcu_led_set(1 << j);
udelay(200 * 1000);
}
return 0;
}
@ -228,97 +199,47 @@ u32 hcu_led_get(void)
return in16(SYS_IO_ADDRESS) & 0x3f;
}
/*---------------------------------------------------------------------------+
/*
* hcu_led_set value to be placed into the LEDs (max 6 bit)
*---------------------------------------------------------------------------*/
*/
void hcu_led_set(u32 value)
{
out16(SYS_IO_ADDRESS, value);
}
/*---------------------------------------------------------------------------+
/*
* get_serial_number
*---------------------------------------------------------------------------*/
static u32 get_serial_number(void)
*/
u32 get_serial_number(void)
{
u32 *serial = (u32 *)CFG_FLASH_BASE;
if (*serial == 0xffffffff)
if (in_be32(serial) == 0xffffffff)
return 0;
return *serial;
return in_be32(serial);
}
/*---------------------------------------------------------------------------+
/*
* hcu_get_slot
*---------------------------------------------------------------------------*/
*/
u32 hcu_get_slot(void)
{
u16 *slot = (u16 *)SYS_SLOT_ADDRESS;
return (*slot) & 0x7f;
return in_be16(slot) & 0x7f;
}
/*---------------------------------------------------------------------------+
/*
* misc_init_r.
*---------------------------------------------------------------------------*/
*/
int misc_init_r(void)
{
char *s = getenv(DEFAULT_ETH_ADDR);
char *e;
int i;
u32 serial = get_serial_number();
unsigned long usb2d0cr = 0;
unsigned long usb2phy0cr, usb2h0cr = 0;
unsigned long sdr0_pfc1;
for (i = 0; i < 6; ++i) {
gd->bd->bi_enetaddr[i] = s ? simple_strtoul(s, &e, 16) : 0;
if (s)
s = (*e) ? e + 1 : e;
}
if (gd->bd->bi_enetaddr[3] == 0 &&
gd->bd->bi_enetaddr[4] == 0 &&
gd->bd->bi_enetaddr[5] == 0) {
char ethaddr[22];
/* Must be in sync with CONFIG_ETHADDR */
gd->bd->bi_enetaddr[0] = 0x00;
gd->bd->bi_enetaddr[1] = 0x60;
gd->bd->bi_enetaddr[2] = 0x13;
gd->bd->bi_enetaddr[3] = (serial >> 16) & 0xff;
gd->bd->bi_enetaddr[4] = (serial >> 8) & 0xff;
gd->bd->bi_enetaddr[5] = hcu_get_slot();
sprintf(ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X\0",
gd->bd->bi_enetaddr[0], gd->bd->bi_enetaddr[1],
gd->bd->bi_enetaddr[2], gd->bd->bi_enetaddr[3],
gd->bd->bi_enetaddr[4], gd->bd->bi_enetaddr[5]) ;
printf("%s: Setting eth %s serial 0x%x\n", __FUNCTION__,
ethaddr, serial);
setenv(DEFAULT_ETH_ADDR, ethaddr);
}
/* IP-Adress update */
{
IPaddr_t ipaddr;
char *ipstring;
ipstring = getenv("ipaddr");
if (ipstring == 0)
ipaddr = string_to_ip("172.25.1.99");
else
ipaddr = string_to_ip(ipstring);
if ((ipaddr & 0xff) != (32 + hcu_get_slot())) {
char tmp[22];
ipaddr = (ipaddr & 0xffffff00) + 32 + hcu_get_slot();
ip_to_string (ipaddr, tmp);
printf("%s: enforce %s\n", __FUNCTION__, tmp);
setenv("ipaddr", tmp);
}
}
#ifdef CFG_ENV_IS_IN_FLASH
/* Monitor protection ON by default */
(void)flash_protect(FLAG_PROTECT_SET,
@ -326,11 +247,13 @@ int misc_init_r(void)
0xffffffff,
&flash_info[0]);
#ifdef CFG_ENV_ADDR_REDUND
/* Env protection ON by default */
(void)flash_protect(FLAG_PROTECT_SET,
CFG_ENV_ADDR_REDUND,
CFG_ENV_ADDR_REDUND + 2*CFG_ENV_SECT_SIZE - 1,
&flash_info[0]);
#endif
#endif
/*
@ -355,7 +278,8 @@ int misc_init_r(void)
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1*/
/* An 8-bit/60MHz interface is the only possible alternative
when connecting the Device to the PHY */
* when connecting the Device to the PHY
*/
usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ; /*1*/
@ -376,14 +300,37 @@ int misc_init_r(void)
mtsdr(SDR0_SRST1, 0x00000000);
udelay(1000);
mtsdr(SDR0_SRST0, 0x00000000);
printf("USB: Host(int phy) Device(ext phy)\n");
common_misc_init_r();
set_params_for_sw_install( sys_install_requested(), "hcu5" );
/* We cannot easily enable trace before, as there are other
* routines messing around with sdr0_pfc1. And I do not need it.
*/
if (mfspr(dbcr0) & 0x80000000) {
/* External debugger alive
* enable trace facilty for Lauterback
* CCR0[DAPUIB]=0 Enable broadcast of instruction data
* to auxiliary processor interface
* CCR0[DTB]=0 Enable broadcast of trace information
* SDR0_PFC0[TRE] Trace signals are enabled instead of
* GPIO49-63
*/
mtspr(ccr0, mfspr(ccr0) &~ 0x00108000);
mtsdr(SDR0_PFC0, sdr0_pfc1 | 0x00000100);
}
return 0;
}
#ifdef CONFIG_PCI
int board_with_pci(void)
{
u32 reg;
#if defined(CONFIG_PCI)
/*************************************************************************
mfsdr(sdr_pci0, reg);
return (reg & SDR0_XCR_PAE_MASK);
}
/*
* pci_pre_init
*
* This routine is called just prior to registering the hose and gives
@ -394,81 +341,64 @@ int misc_init_r(void)
* (add regions, override default access routines, etc) or perform
* certain pre-initialization actions.
*
************************************************************************/
*/
int pci_pre_init(struct pci_controller *hose)
{
unsigned long addr;
/*-------------------------------------------------------------------+
* As of errata version 0.4, CHIP_8: Incorrect Write to DDR SDRAM.
* Workaround: Disable write pipelining to DDR SDRAM by setting
* PLB0_ACR[WRP] = 0.
*-------------------------------------------------------------------*/
if (!board_with_pci()) { return 0; }
/*-------------------------------------------------------------------+
| Set priority for all PLB3 devices to 0.
| Set PLB3 arbiter to fair mode.
+-------------------------------------------------------------------*/
/*
* Set priority for all PLB3 devices to 0.
* Set PLB3 arbiter to fair mode.
*/
mfsdr(sdr_amp1, addr);
mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
addr = mfdcr(plb3_acr);
/* mtdcr(plb3_acr, addr & ~plb1_acr_wrp_mask); */ /* ngngng */
mtdcr(plb3_acr, addr | 0x80000000); /* Sequoia */
/*-------------------------------------------------------------------+
| Set priority for all PLB4 devices to 0.
+-------------------------------------------------------------------*/
/*
* Set priority for all PLB4 devices to 0.
*/
mfsdr(sdr_amp0, addr);
mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */
/* mtdcr(plb4_acr, addr & ~plb1_acr_wrp_mask); */ /* ngngng */
mtdcr(plb4_acr, addr); /* Sequoia */
/*-------------------------------------------------------------------+
| Set Nebula PLB4 arbiter to fair mode.
+-------------------------------------------------------------------*/
/* Segment0 */
addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
/* addr = (addr & ~plb0_acr_wrp_mask); */ /* ngngng */
addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep; /* Sequoia */
/* mtdcr(plb0_acr, addr); */ /* Sequoia */
/*
* As of errata version 0.4, CHIP_8: Incorrect Write to DDR SDRAM.
* Workaround: Disable write pipelining to DDR SDRAM by setting
* PLB0_ACR[WRP] = 0.
*/
mtdcr(plb0_acr, 0); /* PATCH HAB: WRITE PIPELINING OFF */
/* Segment1 */
addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
addr = (addr & ~plb1_acr_wrp_mask) ;
/* mtdcr(plb1_acr, addr); */ /* Sequoia */
mtdcr(plb1_acr, 0); /* PATCH HAB: WRITE PIPELINING OFF */
return 1;
return board_with_pci();
}
/*************************************************************************
/*
* pci_target_init
*
* The bootstrap configuration provides default settings for the pci
* inbound map (PIM). But the bootstrap config choices are limited and
* may not be sufficient for a given board.
*
************************************************************************/
*/
void pci_target_init(struct pci_controller *hose)
{
/*-------------------------------------------------------------+
if (!board_with_pci()) { return; }
/*
* Set up Direct MMIO registers
*-------------------------------------------------------------*/
/*-------------------------------------------------------------+
| PowerPC440EPX PCI Master configuration.
| Map one 1Gig range of PLB/processor addresses to PCI memory space.
| PLB address 0xA0000000-0xDFFFFFFF ==> PCI address
| 0xA0000000-0xDFFFFFFF
| Use byte reversed out routines to handle endianess.
| Make this region non-prefetchable.
+-------------------------------------------------------------*/
*
* PowerPC440EPX PCI Master configuration.
* Map one 1Gig range of PLB/processor addresses to PCI memory space.
* PLB address 0xA0000000-0xDFFFFFFF ==> PCI address
* 0xA0000000-0xDFFFFFFF
* Use byte reversed out routines to handle endianess.
* Make this region non-prefetchable.
*/
/* PMM0 Mask/Attribute - disabled b4 setting */
out32r(PCIX0_PMM0MA, 0x00000000);
out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */
@ -492,9 +422,9 @@ void pci_target_init(struct pci_controller *hose)
out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */
out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */
/*------------------------------------------------------------------+
/*
* Set up Configuration registers
*------------------------------------------------------------------*/
*/
/* Program the board's subsystem id/vendor id */
pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
@ -513,26 +443,27 @@ void pci_target_init(struct pci_controller *hose)
pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
}
/*************************************************************************
/*
* pci_master_init
*
************************************************************************/
*/
void pci_master_init(struct pci_controller *hose)
{
unsigned short temp_short;
if (!board_with_pci()) { return; }
/*---------------------------------------------------------------+
| Write the PowerPC440 EP PCI Configuration regs.
| Enable PowerPC440 EP to be a master on the PCI bus (PMM).
| Enable PowerPC440 EP to act as a PCI memory target (PTM).
+--------------------------------------------------------------*/
/*---------------------------------------------------------------
* Write the PowerPC440 EP PCI Configuration regs.
* Enable PowerPC440 EP to be a master on the PCI bus (PMM).
* Enable PowerPC440 EP to act as a PCI memory target (PTM).
*--------------------------------------------------------------*/
pci_read_config_word(0, PCI_COMMAND, &temp_short);
pci_write_config_word(0, PCI_COMMAND,
temp_short | PCI_COMMAND_MASTER |
PCI_COMMAND_MEMORY);
}
/*************************************************************************
/*
* is_pci_host
*
* This routine is called to determine if a pci scan should be
@ -545,10 +476,28 @@ void pci_master_init(struct pci_controller *hose)
*
* Return 0 for adapter mode, non-zero for host (monarch) mode.
*
*
************************************************************************/
*/
int is_pci_host(struct pci_controller *hose)
{
return 1;
}
#endif /* defined(CONFIG_PCI) */
#if defined(CONFIG_POST)
/*
* Returns 1 if keys pressed to start the power-on long-running tests
* Called from board_init_f().
*/
int post_hotkeys_pressed(void)
{
return 0; /* No hotkeys supported */
}
#endif /* CONFIG_POST */
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
void ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
}
#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */

71
board/netstal/hcu5/init.S
View File

@ -39,41 +39,68 @@
tlbtab:
tlbtab_start
/* vxWorks needs this entry for the Machine Check interrupt, */
/* tlbentry( 0x40000000, SZ_256M, 0, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) */
/* TLB#0: vxWorks needs this entry for the Machine Check interrupt, */
tlbentry( 0x40000000, SZ_256M, 0, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
/* TLB#1: TLB-entry for DDR SDRAM (Up to 2GB) */
tlbentry( CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0,
AC_R|AC_W|AC_X|SA_G|SA_I )
/* TLB#2: TLB-entry for EBC */
tlbentry( 0x80000000, SZ_256M, 0x80000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
/*
* BOOT_CS (FLASH) must be second. Before relocation SA_I can be off to use the
* speed up boot process. It is patched after relocation to enable SA_I
* TLB#3: BOOT_CS (FLASH) must be forth. Before relocation SA_I can be
* off to use the speed up boot process. It is patched after relocation
* to enable SA_I
*/
tlbentry( CFG_BOOT_BASE_ADDR, SZ_1M, CFG_BOOT_BASE_ADDR, 1, AC_R|AC_W|AC_X|SA_G )
tlbentry( CFG_BOOT_BASE_ADDR, SZ_1M, CFG_BOOT_BASE_ADDR, 1,
AC_R|AC_W|AC_X|SA_G)
/* TLB-entry for PCI Memory */
tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 1, AC_R|AC_W|SA_G|SA_I )
tlbentry( CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 1, AC_R|AC_W|SA_G|SA_I )
tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 1, AC_R|AC_W|SA_G|SA_I )
tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 1, AC_R|AC_W|SA_G|SA_I )
/*
* TLB entries for SDRAM are not needed on this platform.
* They are dynamically generated in the SPD DDR(2) detection
* routine.
*/
/* TLB-entry for EBC (CFG_CPLD) */
/* tlbentry( CFG_CPLD, SZ_1K, CFG_CPLD, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) */
/* CAN */
tlbentry( CFG_CS_1, SZ_16M, CFG_CS_1, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
/* IMC + CPLD */
tlbentry( CFG_CS_2, SZ_16M, CFG_CS_2, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
tlbentry( CFG_CS_2 + 0x1000000, SZ_16M, CFG_CS_2 + 0x1000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
/* IMC-Fast */
tlbentry( CFG_CS_3, SZ_16M, CFG_CS_3, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
tlbentry( CFG_CS_3 + 0x1000000, SZ_16M, CFG_CS_3 + 0x1000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
/* TLB#4: */
tlbentry( CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 1,
AC_R|AC_W|SA_G|SA_I )
/* TLB#5: */
tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 1,
AC_R|AC_W|SA_G|SA_I )
/* TLB#6: */
tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 1,
AC_R|AC_W|SA_G|SA_I )
/* TLB-entry for Internal Registers & OCM */
tlbentry( CFG_PCI_BASE, SZ_16M, 0xe0000000, 0, AC_R|AC_W|AC_X|SA_I )
/* TLB#7: */
tlbentry( 0xe0000000, SZ_16M, 0xe0000000, 0,
AC_R|AC_W|AC_X|SA_G|SA_I )
/*TLB-entry PCI registers*/
/* TLB#8: */
tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
/* TLB-entry for peripherals */
/* TLB#9: */
tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
/* TLB for SDRAM will be added by initdram (sdram.c) */
/* CAN */
/* TLB#10: */
tlbentry( CFG_CS_1, SZ_1K, CFG_CS_1, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
/* TLB#11: CPLD and IMC-Standard 32 MB */
tlbentry( CFG_CS_2, SZ_16M, CFG_CS_2, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
/* TLB#12: */
tlbentry( CFG_CS_2 + 0x1000000, SZ_16M, CFG_CS_2 + 0x1000000, 1,
AC_R|AC_W|AC_X|SA_G|SA_I )
/* IMC-Fast 32 MB */
/* TLB#13: */
tlbentry( CFG_CS_3, SZ_16M, CFG_CS_3, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
/* TLB#14: */
tlbentry( CFG_CS_3 + 0x1000000, SZ_16M, CFG_CS_3, 1,
AC_R|AC_W|AC_X|SA_G|SA_I )
tlbtab_end

86
board/netstal/hcu5/sdram.c
View File

@ -62,11 +62,13 @@ void dflush(void);
#define DDR0_22_CTRL_RAW_ECC_ENABLE 0x03000000 /* ECC correcting on */
#define DDR0_03_CASLAT_DECODE(n) ((((unsigned long)(n))>>16)&0x7)
#ifdef CFG_ENABLE_SDRAM_CACHE
#define MY_TLB_WORD2_I_ENABLE 0 /* enable caching on DDR2 */
#else
#define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on DDR2 */
#endif
#define ECC_RAM 0x03267F0B
#define NO_ECC_RAM 0x00267F0B
#define HCU_HW_SDRAM_CONFIG_MASK 0x7
#define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE
/* disable caching on DDR2 */
void program_tlb(u32 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value);
@ -74,6 +76,7 @@ void board_add_ram_info(int use_default)
{
PPC4xx_SYS_INFO board_cfg;
u32 val;
mfsdram(DDR0_22, val);
val &= DDR0_22_CTRL_RAW_MASK;
switch (val) {
@ -157,38 +160,35 @@ static void blank_string(int size)
/*---------------------------------------------------------------------------+
* program_ecc.
*---------------------------------------------------------------------------*/
static void program_ecc(unsigned long start_address, unsigned long num_bytes,
unsigned long tlb_word2_i_value)
static void program_ecc(unsigned long start_address, unsigned long num_bytes)
{
unsigned long current_address= start_address;
int loopi = 0;
u32 val;
char str[] = "ECC generation -";
char slash[] = "\\|/-\\|/-";
#if defined(CONFIG_PRAM)
u32 *magic;
/* Check whether vxWorks is using EDR logging, if yes zero */
/* also PostMortem and user reserved memory */
magic = (u32 *)in_be32((u32 *)(start_address + num_bytes -
(CONFIG_PRAM*1024) + sizeof(u32)));
debug("\n%s: CONFIG_PRAM %d kB magic 0x%x 0x%p -> 0x%x\n", __FUNCTION__,
CONFIG_PRAM,
start_address + num_bytes - (CONFIG_PRAM*1024) + sizeof(u32),
magic, in_be32(magic));
if (in_be32(magic) == 0xbeefbabe)
num_bytes -= (CONFIG_PRAM*1024) - PM_RESERVED_MEM;
#endif
sync();
eieio();
puts(str);
if (tlb_word2_i_value == TLB_WORD2_I_ENABLE) {
/* ECC bit set method for non-cached memory */
/* This takes various seconds */
for(current_address = 0; current_address < num_bytes;
current_address += sizeof(u32)) {
*(u32 *)current_address = 0;
if ((current_address % (2 << 20)) == 0) {
putc('\b');
putc(slash[loopi++ % 8]);
}
}
} else {
/* ECC bit set method for cached memory */
/* Fast method, no noticeable delay */
dcbz_area(start_address, num_bytes);
dflush();
}
/* ECC bit set method for cached memory */
/* Fast method, no noticeable delay */
dcbz_area(start_address, num_bytes);
dflush();
blank_string(strlen(str));
/* Clear error status */
@ -196,7 +196,7 @@ static void program_ecc(unsigned long start_address, unsigned long num_bytes,
mtsdram(DDR0_00, val | DDR0_00_INT_ACK_ALL);
/*
* Clear possible errors
* Clear possible ECC errors
* If not done, then we could get an interrupt later on when
* exceptions are enabled.
*/
@ -209,9 +209,9 @@ static void program_ecc(unsigned long start_address, unsigned long num_bytes,
return;
}
#endif
/***********************************************************************
*
* initdram -- 440EPx's DDR controller is a DENALI Core
@ -219,9 +219,6 @@ static void program_ecc(unsigned long start_address, unsigned long num_bytes,
************************************************************************/
long int initdram (int board_type)
{
#define HCU_HW_SDRAM_CONFIG_MASK 0x7
#define INVALID_HW_CONFIG "Invalid HW-Config"
u16 *hwVersReg = (u16 *) HCU_HW_VERSION_REGISTER;
unsigned int dram_size = 0;
mtsdram(DDR0_02, 0x00000000);
@ -232,24 +229,23 @@ long int initdram (int board_type)
mtsdram(DDR0_03, 0x02030602);
mtsdram(DDR0_04, 0x0A020200);
mtsdram(DDR0_05, 0x02020307);
switch (*hwVersReg & HCU_HW_SDRAM_CONFIG_MASK) {
case 0:
dram_size = 128 * 1024 * 1024 ;
mtsdram(DDR0_06, 0x0102C80D); /* 128MB RAM */
mtsdram(DDR0_11, 0x000FC800); /* 128MB RAM */
mtsdram(DDR0_43, 0x030A0300); /* 128MB RAM */
break;
switch (in_be16((u16 *)HCU_HW_VERSION_REGISTER) & HCU_HW_SDRAM_CONFIG_MASK) {
case 1:
dram_size = 256 * 1024 * 1024 ;
mtsdram(DDR0_06, 0x0102C812); /* 256MB RAM */
mtsdram(DDR0_11, 0x0014C800); /* 256MB RAM */
mtsdram(DDR0_43, 0x030A0200); /* 256MB RAM */
break;
case 0:
default:
sdram_panic(INVALID_HW_CONFIG);
dram_size = 128 * 1024 * 1024 ;
mtsdram(DDR0_06, 0x0102C80D); /* 128MB RAM */
mtsdram(DDR0_11, 0x000FC800); /* 128MB RAM */
mtsdram(DDR0_43, 0x030A0300); /* 128MB RAM */
break;
}
mtsdram(DDR0_07, 0x00090100);
/*
* TCPD=200 cycles of clock input is required to lock the DLL.
* CKE must be HIGH the entire time.mtsdram(DDR0_08, 0x02C80001);
@ -264,8 +260,6 @@ long int initdram (int board_type)
mtsdram(DDR0_19, 0x1D1D1D1D);
mtsdram(DDR0_20, 0x0B0B0B0B);
mtsdram(DDR0_21, 0x0B0B0B0B);
#define ECC_RAM 0x03267F0B
#define NO_ECC_RAM 0x00267F0B
#ifdef CONFIG_DDR_ECC
mtsdram(DDR0_22, ECC_RAM);
#else
@ -288,7 +282,7 @@ long int initdram (int board_type)
* Program tlb entries for this size (dynamic)
*/
remove_tlb(CFG_SDRAM_BASE, 256 << 20);
program_tlb(0, 0, dram_size, MY_TLB_WORD2_I_ENABLE);
program_tlb(0, 0, dram_size, TLB_WORD2_W_ENABLE | TLB_WORD2_I_ENABLE);
/*
* Setup 2nd TLB with same physical address but different virtual
@ -296,13 +290,11 @@ long int initdram (int board_type)
*/
program_tlb(0, CFG_DDR_CACHED_ADDR, dram_size, 0);
/* Diminish RAM to initialize */
dram_size = dram_size - 32 ;
#ifdef CONFIG_DDR_ECC
/*
* If ECC is enabled, initialize the parity bits.
*/
program_ecc(CFG_DDR_CACHED_ADDR, dram_size, 0);
program_ecc(CFG_DDR_CACHED_ADDR, dram_size);
#endif
return (dram_size);

2
board/netstal/hcu5/u-boot.lds
View File

@ -137,7 +137,7 @@ SECTIONS
*(COMMON)
}
ppcenv_assert = ASSERT(. < 0xFFFF8000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CFG_MONITOR_BASE, CFG_MONITOR_LEN and TEXT_BASE may need to be modified.");
ppcenv_assert = ASSERT(. < 0xFFFFB000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CFG_MONITOR_BASE, CFG_MONITOR_LEN and TEXT_BASE may need to be modified.");
_end = . ;
PROVIDE (end = .);

4
cpu/ppc4xx/44x_spd_ddr2.c
View File

@ -387,9 +387,9 @@ long int initdram(int board_type)
unsigned char spd1[MAX_SPD_BYTES];
unsigned char *dimm_spd[MAXDIMMS];
unsigned long dimm_populated[MAXDIMMS];
unsigned long num_dimm_banks; /* on board dimm banks */
unsigned long num_dimm_banks; /* on board dimm banks */
unsigned long val;
ddr_cas_id_t selected_cas;
ddr_cas_id_t selected_cas = DDR_CAS_5; /* preset to silence compiler */
int write_recovery;
unsigned long dram_size = 0;

438
include/configs/DU440.h Normal file
View File

@ -0,0 +1,438 @@
/*
* (C) Copyright 2008
* Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com
*
* based on the Sequoia board configuration by
* Stefan Roese, Jacqueline Pira-Ferriol and Alain Saurel
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
**********************************************************************
* DU440.h - configuration for esd's DU440 board (Power PC440EPx)
**********************************************************************
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*
* High Level Configuration Options
*/
#define CONFIG_DU440 1 /* Board is esd DU440 */
#define CONFIG_440EPX 1 /* Specific PPC440EPx */
#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_SYS_CLK_FREQ 33333400 /* external freq to pll */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
#define CONFIG_LAST_STAGE_INIT 1 /* last_stage_init */
/*
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
*/
#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */
#define CFG_MALLOC_LEN (8 << 20) /* Reserve 8 MB for malloc() */
#define CFG_BOOT_BASE_ADDR 0xf0000000
#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
#define CFG_FLASH_BASE 0xfc000000 /* start of FLASH */
#define CFG_MONITOR_BASE TEXT_BASE
#define CFG_NAND0_ADDR 0xd0000000 /* NAND Flash */
#define CFG_NAND1_ADDR 0xd0100000 /* NAND Flash */
#define CFG_OCM_BASE 0xe0010000 /* ocm */
#define CFG_PCI_BASE 0xe0000000 /* Internal PCI regs */
#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */
#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000
#define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000
#define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000
#define CFG_PCI_IOBASE 0xe8000000
/* Don't change either of these */
#define CFG_PERIPHERAL_BASE 0xef600000 /* internal peripherals */
#define CFG_USB2D0_BASE 0xe0000100
#define CFG_USB_DEVICE 0xe0000000
#define CFG_USB_HOST 0xe0000400
/*
* Initial RAM & stack pointer
*/
/* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache */
#define CFG_INIT_RAM_OCM 1 /* OCM as init ram */
#define CFG_INIT_RAM_ADDR CFG_OCM_BASE /* OCM */
#define CFG_INIT_RAM_END (4 << 10)
#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
/*
* Serial Port
*/
/* TODO: external clock oscillator will be removed */
#define CFG_EXT_SERIAL_CLOCK 11059200 /* ext. 11.059MHz clk */
#define CONFIG_BAUDRATE 115200
#define CONFIG_SERIAL_MULTI 1
#undef CONFIG_UART1_CONSOLE
#define CFG_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
/*
* Video Port
*/
#define CONFIG_VIDEO
#define CONFIG_VIDEO_SMI_LYNXEM
#define CONFIG_CFB_CONSOLE
#define CONFIG_VIDEO_LOGO
#define CONFIG_VGA_AS_SINGLE_DEVICE
#define CONFIG_SPLASH_SCREEN
#define CONFIG_SPLASH_SCREEN_ALIGN
#define CONFIG_VIDEO_BMP_GZIP /* gzip compressed bmp images */
#define CFG_VIDEO_LOGO_MAX_SIZE (4 << 20) /* for decompressed img */
#define CFG_DEFAULT_VIDEO_MODE 0x31a /* 1280x1024,16bpp */
#define CFG_CONSOLE_IS_IN_ENV
#define CFG_ISA_IO CFG_PCI_IOBASE
/*
* Environment
*/
#define CFG_ENV_IS_IN_EEPROM 1 /* use FLASH for environment vars */
/*
* FLASH related
*/
#define CFG_FLASH_CFI /* The flash is CFI compatible */
#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
/* CFI_FLASH_PROTECTION make flash_protect hang sometimes -> disabled */
#define CFG_FLASH_PROTECTION 1 /* use hardware flash protection */
#define CFG_FLASH_EMPTY_INFO
#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
#ifdef CFG_ENV_IS_IN_FLASH
#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
#define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
/* Address and size of Redundant Environment Sector */
#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
#endif
#ifdef CFG_ENV_IS_IN_EEPROM
#define CFG_ENV_OFFSET 0 /* environment starts at */
/* the beginning of the EEPROM */
#define CFG_ENV_SIZE 0x1000 /* 4096 bytes may be used for env vars */
#endif
/*
* DDR SDRAM
*/
#define CFG_MBYTES_SDRAM (1024) /* 512 MiB TODO: remove */
#define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */
#if 0
#define CONFIG_ZERO_SDRAM /* Zero SDRAM after setup */
#endif
#define CONFIG_DDR_ECC /* Use ECC when available */
#define SPD_EEPROM_ADDRESS {0x50}
#define CONFIG_PROG_SDRAM_TLB
/*
* I2C
*/
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CFG_I2C_SPEED 100000 /* I2C speed and slave address */
#define CFG_I2C_SLAVE 0x7F
#define CONFIG_I2C_CMD_TREE 1
#define CONFIG_I2C_MULTI_BUS 1
#define CFG_SPD_BUS_NUM 0
#define IIC1_MCP3021_ADDR 0x4d
#define IIC1_USB2507_ADDR 0x2c
#ifdef CONFIG_I2C_MULTI_BUS
#define CFG_I2C_NOPROBES {{1, IIC1_USB2507_ADDR}}
#endif
#define CFG_I2C_MULTI_EEPROMS
#define CFG_I2C_EEPROM_ADDR 0x54
#define CFG_I2C_EEPROM_ADDR_LEN 2
#define CFG_EEPROM_PAGE_WRITE_ENABLE
#define CFG_EEPROM_PAGE_WRITE_BITS 5
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x01
#define CFG_EEPROM_WREN 1
#define CFG_I2C_BOOT_EEPROM_ADDR 0x52
/*
* standard dtt sensor configuration - bottom bit will determine local or
* remote sensor of the TMP401
*/
#define CONFIG_DTT_SENSORS { 0, 1 }
/*
* The PMC440 uses a TI TMP401 temperature sensor. This part
* is basically compatible to the ADM1021 that is supported
* by U-Boot.
*
* - i2c addr 0x4c
* - conversion rate 0x02 = 0.25 conversions/second
* - ALERT ouput disabled
* - local temp sensor enabled, min set to 0 deg, max set to 70 deg
* - remote temp sensor enabled, min set to 0 deg, max set to 70 deg
*/
#define CONFIG_DTT_ADM1021
#define CFG_DTT_ADM1021 { { 0x4c, 0x02, 0, 1, 70, 0, 1, 70, 0} }
/*
* RTC stuff
*/
#define CONFIG_RTC_DS1338
#define CFG_I2C_RTC_ADDR 0x68
#undef CONFIG_BOOTARGS
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"ethrotate=no\0" \
"hostname=du440\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=${serverip}:${rootpath}\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
"addip=setenv bootargs ${bootargs} " \
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
":${hostname}:${netdev}:off panic=1\0" \
"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
"flash_self=run ramargs addip addtty optargs;" \
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
"net_nfs=tftp 200000 ${img};run nfsargs addip addtty optargs;" \
"bootm\0" \
"rootpath=/tftpboot/du440/target_root_du440\0" \
"img=/tftpboot/du440/uImage\0" \
"kernel_addr=FFC00000\0" \
"ramdisk_addr=FFE00000\0" \
"initrd_high=30000000\0" \
"load=tftp 100000 /tftpboot/du440/u-boot.bin\0" \
"update=protect off FFFA0000 FFFFFFFF;era FFFA0000 FFFFFFFF;" \
"cp.b 100000 FFFA0000 60000\0" \
""
#if 0
#define CONFIG_BOOTCOMMAND "run flash_self"
#endif
#define CONFIG_PREBOOT /* enable preboot variable */
#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#ifndef __ASSEMBLY__
int du440_phy_addr(int devnum);
#endif
#define CONFIG_IBM_EMAC4_V4 1
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR du440_phy_addr(0) /* PHY address */
#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
#define CONFIG_PHY_GIGE 1 /* Include GbE detection */
#define CONFIG_HAS_ETH0
#define CFG_RX_ETH_BUFFER 128
#define CONFIG_NET_MULTI 1
#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
#define CONFIG_PHY1_ADDR du440_phy_addr(1)
/*
* USB
*/
#define CONFIG_USB_OHCI_NEW
#define CONFIG_USB_STORAGE
#define CFG_OHCI_BE_CONTROLLER
#define CFG_USB_OHCI_CPU_INIT 1
#define CFG_USB_OHCI_REGS_BASE CFG_USB_HOST
#define CFG_USB_OHCI_SLOT_NAME "du440"
#define CFG_USB_OHCI_MAX_ROOT_PORTS 15
/* Comment this out to enable USB 1.1 device */
#define USB_2_0_DEVICE
/* Partitions */
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_ISO_PARTITION
#include <config_cmd_default.h>
#define CONFIG_CMD_BSP
#define CONFIG_CMD_DATE
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_DTT
#define CONFIG_CMD_DIAG
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_ELF
#define CONFIG_CMD_FAT
#define CONFIG_CMD_I2C
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_MII
#define CONFIG_CMD_NAND
#define CONFIG_CMD_NET
#define CONFIG_CMD_NFS
#define CONFIG_CMD_PCI
#define CONFIG_CMD_PING
#define CONFIG_CMD_USB
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_SDRAM
#define CONFIG_SUPPORT_VFAT
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
/* Print Buffer Size */
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_MEMTEST_START 0x00400000 /* memtest works on */
#define CFG_MEMTEST_END 0x3f000000 /* 4 ... < 1GB DRAM */
#define CFG_LOAD_ADDR 0x100000 /* default load address */
#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
#define CONFIG_LOOPW 1 /* enable loopw command */
#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
#define CONFIG_AUTOBOOT_KEYED 1
#define CONFIG_AUTOBOOT_PROMPT "Press SPACE to abort autoboot in %d seconds\n"
#define CONFIG_AUTOBOOT_DELAY_STR "d"
#define CONFIG_AUTOBOOT_STOP_STR " "
/*
* PCI stuff
*/
#define CONFIG_PCI /* include pci support */
#define CONFIG_PCI_PNP /* do (not) pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/
/* Board-specific PCI */
#define CFG_PCI_TARGET_INIT
#define CFG_PCI_MASTER_INIT
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*
* External Bus Controller (EBC) Setup
*/
#define CFG_FLASH CFG_FLASH_BASE
#define CFG_CPLD_BASE 0xC0000000
#define CFG_CPLD_RANGE 0x00000010
#define CFG_DUMEM_BASE 0xC0100000
#define CFG_DUMEM_RANGE 0x00100000
#define CFG_DUIO_BASE 0xC0200000
#define CFG_DUIO_RANGE 0x00010000
#define CFG_NAND0_CS 2 /* NAND chip connected to CSx */
#define CFG_NAND1_CS 3 /* NAND chip connected to CSx */
/* Memory Bank 0 (NOR-FLASH) initialization */
#define CFG_EBC_PB0AP 0x04017200
#define CFG_EBC_PB0CR (CFG_FLASH_BASE | 0xda000)
/* Memory Bank 1 (CPLD, 16 bytes needed, but 1MB is minimum) */
#define CFG_EBC_PB1AP 0x018003c0
#define CFG_EBC_PB1CR (CFG_CPLD_BASE | 0x18000)
/* Memory Bank 2 (NAND-FLASH) initialization */
#define CFG_EBC_PB2AP 0x018003c0
#define CFG_EBC_PB2CR (CFG_NAND0_ADDR | 0x1c000)
/* Memory Bank 3 (NAND-FLASH) initialization */
#define CFG_EBC_PB3AP 0x018003c0
#define CFG_EBC_PB3CR (CFG_NAND1_ADDR | 0x1c000)
/* Memory Bank 4 (DUMEM, 1MB) initialization */
#define CFG_EBC_PB4AP 0x018053c0
#define CFG_EBC_PB4CR (CFG_DUMEM_BASE | 0x18000)
/* Memory Bank 5 (DUIO, 64KB needed, but 1MB is minimum) */
#define CFG_EBC_PB5AP 0x018053c0
#define CFG_EBC_PB5CR (CFG_DUIO_BASE | 0x18000)
/*
* NAND FLASH
*/
#define CFG_MAX_NAND_DEVICE 2
#define NAND_MAX_CHIPS CFG_MAX_NAND_DEVICE
#define CFG_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
#define CFG_NAND_BASE_LIST {CFG_NAND0_ADDR + CFG_NAND0_CS, \
CFG_NAND1_ADDR + CFG_NAND1_CS}
/*
* Internal Definitions
*
* Boot Flags
*/
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
#if 0
#define CONFIG_SHOW_ACTIVITY 1
#endif
#endif /* __CONFIG_H */

4
include/configs/PMC440.h
View File

@ -385,7 +385,7 @@
*----------------------------------------------------------------------*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
@ -503,7 +503,7 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif

115
include/configs/hcu4.h
View File

@ -46,8 +46,8 @@
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
*----------------------------------------------------------------------*/
#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */
#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
#define CFG_MONITOR_LEN (320 * 1024) /* Reserve 320 kB for Monitor */
#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
@ -67,7 +67,7 @@
#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE
#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR
/*-----------------------------------------------------------------------
* Serial Port
@ -82,8 +82,8 @@
* set Linux BASE_BAUD to 403200.
*/
#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */
#undef CONFIG_SERIAL_MULTI /* needed to be able to define
CONFIG_SERIAL_SOFTWARE_FIFO */
#define CONFIG_SERIAL_MULTI 1
/* needed to be able to define CONFIG_SERIAL_SOFTWARE_FIFO */
#undef CFG_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
#define CFG_BASE_BAUD 691200
@ -100,13 +100,24 @@
#define CFG_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
/*-----------------------------------------------------------------------
* Flash
*----------------------------------------------------------------------*/
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
#define CFG_MAX_FLASH_SECT 8 /* max number of sectors on one chip */
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
/*-----------------------------------------------------------------------
* Environment
*----------------------------------------------------------------------*/
#undef CFG_ENV_IS_IN_NVRAM
#undef CFG_ENV_IS_IN_FLASH
#define CFG_ENV_IS_IN_EEPROM
#define CFG_ENV_IS_IN_FLASH
#undef CFG_ENV_IS_NOWHERE
#ifdef CFG_ENV_IS_IN_EEPROM
@ -120,7 +131,7 @@
/* Put the environment in Flash */
#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
#define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */
#define CFG_ENV_SIZE 8*1024 /* 8 KB Environment Sector */
/* Address and size of Redundant Environment Sector */
#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
@ -158,7 +169,7 @@
/* Setup some board specific values for the default environment variables */
#define CONFIG_HOSTNAME hcu4
#define CONFIG_IPADDR 172.25.1.42
#define CONFIG_IPADDR 172.25.1.99
#define CONFIG_ETHADDR 00:60:13:00:00:00 /* Netstal Machines AG MAC */
#define CONFIG_OVERWRITE_ETHADDR_ONCE
#define CONFIG_SERVERIP 172.25.1.3
@ -180,21 +191,17 @@
"rootpath=/home/diagnose/eldk/ppc_4xx\0" \
"bootfile=/tftpboot/hcu4/uImage\0" \
"load=tftp 100000 hcu4/u-boot.bin\0" \
"update=protect off FFFa0000 FFFFFFFF;era FFFa0000 FFFFFFFF;" \
"cp.b 100000 FFFa0000 60000\0" \
"update=protect off FFFB0000 FFFFFFFF;era FFFC0000 FFFFFFFF;" \
"cp.b 100000 FFFB0000 50000\0" \
"upd=run load;run update\0" \
"vx=tftp ${loadaddr} hcu4_vx_rom;" \
"setenv bootargs emac(0,0)hcu4_vx_rom e=${ipaddr} " \
" h=${serverip} u=dpu pw=netstal8752 tn=hcu4 f=0x3008;" \
"vx=tftp ${loadaddr} hcu4/hcu4_vx_rom;" \
"setenv bootargs emac(0,0)c:hcu4/hcu4_vx_rom e=${ipaddr} " \
"bootvx ${loadaddr}\0" \
""
#define CONFIG_BOOTCOMMAND "run vx"
#if 0
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
#else
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#endif
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
@ -202,10 +209,10 @@
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 1 /* PHY address */
#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
#define CONFIG_HAS_ETH0
#define CFG_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */
#define CFG_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & desC */
/*
* BOOTP options
@ -221,7 +228,6 @@
#include <config_cmd_default.h>
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_BSP
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_DIAG
@ -241,15 +247,30 @@
#define CONFIG_SPD_EEPROM 1
#define SPD_EEPROM_ADDRESS 0x50
/* POST support */
#define CONFIG_POST (CFG_POST_MEMORY | \
CFG_POST_CPU | \
CFG_POST_UART | \
CFG_POST_I2C | \
CFG_POST_CACHE | \
CFG_POST_ETHER | \
CFG_POST_SPR)
#define CFG_POST_UART_TABLE {UART0_BASE}
#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4)
#undef CONFIG_LOGBUFFER
#define CFG_POST_CACHE_ADDR 0x00800000 /* free virtual address */
#define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
/*-----------------------------------------------------------------------
* Miscellaneous configurable options
*----------------------------------------------------------------------*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
@ -266,47 +287,40 @@
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
#define CONFIG_LOOPW 1 /* enable loopw command */
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
/*-----------------------------------------------------------------------
* External Bus Controller (EBC) Setup
*/
/* Memory Bank 0 (Flash Bank 0) initialization */
#define CFG_EBC_PB0AP 0x02005400
#define CFG_EBC_PB0CR 0xFFF18000 /* BAS=0xFFF,BS=1MB,BU=R/W,BW=8bit */
#define CFG_EBC_CFG 0x98400000
#define CFG_EBC_PB1AP 0x03041200
#define CFG_EBC_PB1CR 0x7009A000 /* BAS=,BS=MB,BU=R/W,BW=bit */
/* Memory Bank 0 (Flash Bank 0) initialization */
#define CFG_EBC_PB0AP 0x02005400
#define CFG_EBC_PB0CR 0xFFF18000 /* BAS=0xFFF,BS=1MB,BU=R/W,BW=8bit */
#define CFG_EBC_PB2AP 0x02054500
#define CFG_EBC_PB2CR 0x78018000 /* BAS=,BS=MB,BU=R/W,BW=bit */
#define CFG_EBC_PB1AP 0x03041200
#define CFG_EBC_PB1CR 0x7009A000 /* BAS=,BS=MB,BU=R/W,BW=bit */
#define CFG_EBC_PB3AP 0x01840300
#define CFG_EBC_PB3CR 0x7c0ba000 /* BAS=,BS=MB,BU=R/W,BW=bit */
#define CFG_EBC_PB2AP 0x02054500
#define CFG_EBC_PB2CR 0x78018000 /* BAS=,BS=MB,BU=R/W,BW=bit */
#define CFG_EBC_PB4AP 0x01800300
#define CFG_EBC_PB4CR 0x7e0ba000 /* BAS=,BS=MB,BU=R/W,BW=bit */
#define CFG_EBC_PB3AP 0x01840300
#define CFG_EBC_PB3CR 0x7c0ba000 /* BAS=,BS=MB,BU=R/W,BW=bit */
#define CFG_GPIO0_TCR 0x7ffe0000 /* GPIO value */
#define CFG_EBC_PB4AP 0x01800300
#define CFG_EBC_PB4CR 0x7e0ba000 /* BAS=,BS=MB,BU=R/W,BW=bit */
#define CFG_GPIO0_OR 0xF27FFFFF /* GPIO value */
#define CFG_GPIO0_TCR 0x7FFE0000 /* GPIO value */
#define CFG_GPIO0_ODR 0x00E897FC /* GPIO value */
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
* FLASH organization
*/
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
#define CFG_BOOTMAPSZ (8 << 20)/* Initial Memory map for Linux */
/* Init Memory Controller:
*
@ -326,8 +340,8 @@
*
* Boot Flags
*/
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
#define CFG_HUSH_PARSER /* use "hush" command parser */
#ifdef CFG_HUSH_PARSER
@ -338,4 +352,9 @@
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
/* pass open firmware flat tree */
#define CONFIG_OF_LIBFDT 1
#define CONFIG_OF_BOARD_SETUP 1
#endif /* __CONFIG_H */

136
include/configs/hcu5.h
View File

@ -48,14 +48,16 @@
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
*----------------------------------------------------------------------*/
#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */
#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
#define CFG_MONITOR_LEN (320 * 1024) /* Reserve 320 kB for Monitor */
#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
#define CFG_TLB_FOR_BOOT_FLASH 3
#define CFG_BOOT_BASE_ADDR 0xfff00000
#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
#define CFG_FLASH_BASE 0xfff80000 /* start of FLASH */
#define CFG_MONITOR_BASE TEXT_BASE
#define CFG_OCM_BASE 0xe0010000 /* ocm */
#define CFG_OCM_DATA_ADDR CFG_OCM_BASE
#define CFG_PCI_BASE 0xe0000000 /* Internal PCI regs */
#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */
#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000
@ -78,14 +80,15 @@
#define CFG_INIT_RAM_END (4 << 10)
#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR
/*-----------------------------------------------------------------------
* Serial Port
*----------------------------------------------------------------------*/
#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */
#define CONFIG_BAUDRATE 9600
#undef CONFIG_SERIAL_MULTI /* needed to be able to define
#define CONFIG_SERIAL_MULTI 1
/* needed to be able to define
CONFIG_SERIAL_SOFTWARE_FIFO, but
CONFIG_SERIAL_SOFTWARE_FIFO (16) does not work */
/* Size (bytes) of interrupt driven serial port buffer.
@ -95,6 +98,7 @@
#undef CONFIG_SERIAL_SOFTWARE_FIFO
#undef CONFIG_UART1_CONSOLE
#undef CONFIG_CMD_HWFLOW
#define CFG_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
@ -103,8 +107,8 @@
*----------------------------------------------------------------------*/
#undef CFG_ENV_IS_IN_NVRAM
#undef CFG_ENV_IS_IN_FLASH
#define CFG_ENV_IS_IN_EEPROM
#define CFG_ENV_IS_IN_FLASH
#undef CFG_ENV_IS_IN_EEPROM
#undef CFG_ENV_IS_NOWHERE
#ifdef CFG_ENV_IS_IN_EEPROM
@ -117,22 +121,28 @@
#ifdef CFG_ENV_IS_IN_FLASH
/* Put the environment in Flash */
#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
#define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */
#define CFG_ENV_SIZE 8*1024 /* 8 KB Environment Sector */
/* Address and size of Redundant Environment Sector */
#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
#endif
/*-----------------------------------------------------------------------
* DDR SDRAM
*----------------------------------------------------------------------*/
#define CFG_MBYTES_SDRAM (128) /* 128 MB or 256 MB */
#define CFG_DDR_CACHED_ADDR 0x40000000 /* setup 2nd TLB cached here */
#undef CONFIG_DDR_DATA_EYE /* Do not use DDR2 optimization */
#define CONFIG_DDR_ECC 1 /* enable ECC */
#define CFG_MBYTES_SDRAM (128) /* 128 MB or 256 MB */
#define CFG_DDR_CACHED_ADDR 0x50000000 /* setup 2nd TLB cached here */
#undef CONFIG_DDR_DATA_EYE /* Do not use DDR2 optimization */
#define CONFIG_DDR_ECC 1 /* enable ECC */
/* Following two definitions must be kept in sync with config.h of vxWorks */
#define USER_RESERVED_MEM ( 0) /* in kB */
#define PM_RESERVED_MEM ( 64) /* in kB: pmLib reserved area size */
#define CONFIG_PRAM ( USER_RESERVED_MEM + PM_RESERVED_MEM )
/*-----------------------------------------------------------------------
* I2C stuff for a ATMEL AT24C16 (2kB holding ENV, we are using the
@ -165,8 +175,8 @@
/* Setup some board specific values for the default environment variables */
#define CONFIG_HOSTNAME hcu5
#define CONFIG_IPADDR 172.25.1.42
#define CONFIG_ETHADDR 00:60:13:00:00:00 /* Netstal Machines AG MAC */
#define CONFIG_IPADDR 172.25.1.99
#define CONFIG_ETHADDR 00:60:13:00:00:00 /* Netstal Machines AG MAC */
#define CONFIG_OVERWRITE_ETHADDR_ONCE
#define CONFIG_SERVERIP 172.25.1.3
@ -187,21 +197,27 @@
"bootfile=hcu5/uImage\0" \
"rootpath=/home/hcu/eldk/ppc_4xxFP\0" \
"load=tftp 100000 hcu5/u-boot.bin\0" \
"update=protect off FFFa0000 FFFFFFFF;era FFFa0000 FFFFFFFF;" \
"cp.b 100000 FFFa0000 60000\0" \
"update=protect off FFFb0000 FFFFFFFF;era FFFb0000 FFFFFFFF;" \
"cp.b 100000 FFFb0000 50000\0" \
"upd=run load;run update\0" \
"vx=tftp ${loadaddr} hcu5/hcu5_vx_rom;" \
"setenv bootargs emac(0,0)hcu5_vx_rom e=${ipaddr} " \
" h=${serverip} u=dpu pw=netstal8752 tn=hcu5 f=0x3008;" \
"bootvx ${loadaddr}\0" \
"vx=tftp ${loadaddr} hcu5/hcu5_vx_rom; run vxboot\0" \
"vxusb=usb start; fatload usb 0 ${loadaddr} vxWorks.st; run vxboot\0" \
"vxargs=emac(0,0)c:hcu5/hcu5_vx_rom e=${ipaddr} h=${serverip}" \
" u=dpu pw=netstal8752 tn=hcu5 f=0x3008\0" \
"vxboot=setenv bootargs $(vxargs); bootvx ${loadaddr}\0" \
"usbargs=setenv bootargs root=/dev/sda1 ro\0" \
"linux=usb start; ext2load usb 0 ${loadaddr} /boot/uImage;" \
"run usbargs addip addtty; bootm\0" \
"net_nfs_fdt=tftp 200000 ${bootfile};" \
"tftp ${fdt_addr} ${fdt_file};" \
"run nfsargs addip addtty;" \
"bootm 200000 - ${fdt_addr}\0" \
"fdt_file=hcu5/hcu5.dtb\0" \
"fdt_addr=400000\0" \
""
#define CONFIG_BOOTCOMMAND "run vx"
#if 0
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
#else
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#endif
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
@ -214,7 +230,7 @@
#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
#define CONFIG_HAS_ETH0
#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & desc. */
#define CONFIG_NET_MULTI 1
#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
@ -246,7 +262,6 @@
#include <config_cmd_default.h>
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_BSP
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_DIAG
#define CONFIG_CMD_EEPROM
@ -264,6 +279,21 @@
#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_USB
/* POST support */
#define CONFIG_POST (CFG_POST_MEMORY | \
CFG_POST_CPU | \
CFG_POST_UART | \
CFG_POST_I2C | \
CFG_POST_CACHE | \
CFG_POST_FPU | \
CFG_POST_ETHER | \
CFG_POST_SPR)
#define CFG_POST_UART_TABLE {UART0_BASE}
#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4)
#define CFG_POST_CACHE_ADDR 0x7fff0000 /* free virtual address */
#define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
#define CONFIG_SUPPORT_VFAT
/*-----------------------------------------------------------------------
@ -276,7 +306,7 @@
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
@ -291,17 +321,16 @@
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
#define CONFIG_LOOPW 1 /* enable loopw command */
#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
/*-----------------------------------------------------------------------
* PCI stuff
*----------------------------------------------------------------------*/
/* General PCI */
#define CONFIG_PCI /* include pci support */
#define CONFIG_PCI 1 /* include pci support */
#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr map to CFG_PCI_MEMBASE*/
/* Board-specific PCI */
#define CFG_PCI_TARGET_INIT
@ -315,7 +344,17 @@
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
* Flash
*----------------------------------------------------------------------*/
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
#define CFG_MAX_FLASH_SECT 8 /* max number of sectors on one chip */
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
/*-----------------------------------------------------------------------
* External Bus Controller (EBC) Setup
@ -324,40 +363,30 @@
#define CFG_CS_1 0xC8000000 /* CAN */
#define CFG_CS_2 0xCC000000 /* CPLD and IMC-Bus Standard */
#define CFG_CPLD CFG_CS_2
#define CFG_CS_3 0xCD000000 /* CPLD and IMC-Bus Fast */
#define CFG_CS_3 0xCE000000 /* CPLD and IMC-Bus Fast */
/*-----------------------------------------------------------------------
* FLASH organization
* Memory Bank 0 (BOOT-FLASH) initialization
*/
#define CFG_BOOTFLASH_CS 0 /* Boot Flash chip connected to CSx */
#define CFG_BOOTFLASH_CS 0 /* Boot Flash chip connected to CSx */
#define CFG_EBC_PB0AP 0x02005400
#define CFG_EBC_PB0CR 0xFFF18000 /* (CFG_FLASH | 0xda000) */
#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
#define CFG_MAX_FLASH_SECT 32 /* max number of sectors on one chip */
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
/* Memory Bank 1 CAN-Chips initialization */
/* Memory Bank 1 CAN-Chips initialization */
#define CFG_EBC_PB1AP 0x02054500
#define CFG_EBC_PB1CR 0xC8018000
/* Memory Bank 2 CPLD/IMC-Bus standard initialization */
/* Memory Bank 2 CPLD/IMC-Bus standard initialization */
#define CFG_EBC_PB2AP 0x01840300
#define CFG_EBC_PB2CR 0xCC0BA000
/* Memory Bank 3 IMC-Bus fast mode initialization */
/* Memory Bank 3 IMC-Bus fast mode initialization */
#define CFG_EBC_PB3AP 0x01800300
#define CFG_EBC_PB3CR 0xCE0BA000
/* Memory Bank 4 (not used) initialization */
/* Memory Bank 4 (not used) initialization */
#undef CFG_EBC_PB4AP
#undef CFG_EBC_PB4CR
/* Memory Bank 5 (not used) initialization */
/* Memory Bank 5 (not used) initialization */
#undef CFG_EBC_PB5AP
#undef CFG_EBC_PB5CR
@ -369,8 +398,8 @@
*
* Boot Flags
*/
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
#define CFG_HUSH_PARSER /* use "hush" command parser */
#ifdef CFG_HUSH_PARSER
@ -381,4 +410,9 @@
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
/* pass open firmware flat tree */
#define CONFIG_OF_LIBFDT 1
#define CONFIG_OF_BOARD_SETUP 1
#endif /* __CONFIG_H */

2
include/configs/kilauea.h
View File

@ -476,7 +476,7 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif

2
include/configs/makalu.h
View File

@ -385,7 +385,7 @@
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif

328
post/cpu/ppc4xx/denali_ecc.c
View File

@ -49,7 +49,7 @@
DECLARE_GLOBAL_DATA_PTR;
const static unsigned char syndrome_codes[] = {
const static uint8_t syndrome_codes[] = {
0xF4, 0XF1, 0XEC, 0XEA, 0XE9, 0XE6, 0XE5, 0XE3,
0XDC, 0XDA, 0XD9, 0XD6, 0XD5, 0XD3, 0XCE, 0XCB,
0xB5, 0XB0, 0XAD, 0XAB, 0XA8, 0XA7, 0XA4, 0XA2,
@ -65,174 +65,183 @@ const static unsigned char syndrome_codes[] = {
#define ECC_STOP_ADDR 0x2000
#define ECC_PATTERN 0x01010101
#define ECC_PATTERN_CORR 0x11010101
#define ECC_PATTERN_UNCORR 0xF1010101
#define ECC_PATTERN_UNCORR 0x61010101
static int test_ecc_error(void)
inline static void disable_ecc(void)
{
unsigned long value;
unsigned long hdata, ldata, haddr, laddr;
unsigned int bit;
uint32_t value;
int ret = 0;
mfsdram(DDR0_23, value);
for (bit = 0; bit < sizeof(syndrome_codes); bit++)
if (syndrome_codes[bit] == ((value >> 16) & 0xff))
break;
mfsdram(DDR0_00, value);
if (value & DDR0_00_INT_STATUS_BIT0) {
debug("Bit0. A single access outside the defined PHYSICAL"
" memory space detected\n");
mfsdram(DDR0_32, laddr);
mfsdram(DDR0_33, haddr);
debug(" addr = 0x%08x%08x\n", haddr, laddr);
ret = 1;
}
if (value & DDR0_00_INT_STATUS_BIT1) {
debug("Bit1. Multiple accesses outside the defined PHYSICAL"
" memory space detected\n");
ret = 2;
}
if (value & DDR0_00_INT_STATUS_BIT2) {
debug("Bit2. Single correctable ECC event detected\n");
mfsdram(DDR0_38, laddr);
mfsdram(DDR0_39, haddr);
mfsdram(DDR0_40, ldata);
mfsdram(DDR0_41, hdata);
debug(" 0x%08x - 0x%08x%08x, bit - %d\n",
laddr, hdata, ldata, bit);
ret = 3;
}
if (value & DDR0_00_INT_STATUS_BIT3) {
debug("Bit3. Multiple correctable ECC events detected\n");
mfsdram(DDR0_38, laddr);
mfsdram(DDR0_39, haddr);
mfsdram(DDR0_40, ldata);
mfsdram(DDR0_41, hdata);
debug(" 0x%08x - 0x%08x%08x, bit - %d\n",
laddr, hdata, ldata, bit);
ret = 4;
}
if (value & DDR0_00_INT_STATUS_BIT4) {
debug("Bit4. Single uncorrectable ECC event detected\n");
mfsdram(DDR0_34, laddr);
mfsdram(DDR0_35, haddr);
mfsdram(DDR0_36, ldata);
mfsdram(DDR0_37, hdata);
debug(" 0x%08x - 0x%08x%08x, bit - %d\n",
laddr, hdata, ldata, bit);
ret = 5;
}
if (value & DDR0_00_INT_STATUS_BIT5) {
debug("Bit5. Multiple uncorrectable ECC events detected\n");
mfsdram(DDR0_34, laddr);
mfsdram(DDR0_35, haddr);
mfsdram(DDR0_36, ldata);
mfsdram(DDR0_37, hdata);
debug(" 0x%08x - 0x%08x%08x, bit - %d\n",
laddr, hdata, ldata, bit);
ret = 6;
}
if (value & DDR0_00_INT_STATUS_BIT6) {
debug("Bit6. DRAM initialization complete\n");
ret = 7;
}
/* error status cleared */
mfsdram(DDR0_00, value);
mtsdram(DDR0_00, value | DDR0_00_INT_ACK_ALL);
return ret;
}
static int test_ecc(unsigned long ecc_addr)
{
unsigned long value;
volatile unsigned *const ecc_mem = (volatile unsigned *) ecc_addr;
int pret;
int ret = 0;
sync();
eieio();
WATCHDOG_RESET();
debug("Entering test_ecc(0x%08lX)\n", ecc_addr);
out_be32(ecc_mem, ECC_PATTERN);
out_be32(ecc_mem + 1, ECC_PATTERN);
in_be32(ecc_mem);
pret = test_ecc_error();
if (pret != 0) {
debug("pret: expected 0, got %d\n", pret);
ret = 1;
}
/* test for correctable error */
/* disconnect from ecc storage */
sync(); /* Wait for any pending memory accesses to complete. */
mfsdram(DDR0_22, value);
mtsdram(DDR0_22, (value & ~DDR0_22_CTRL_RAW_MASK)
| DDR0_22_CTRL_RAW_ECC_DISABLE);
}
/* creating (correctable) single-bit error */
out_be32(ecc_mem, ECC_PATTERN_CORR);
inline static void clear_and_enable_ecc(void)
{
uint32_t value;
/* enable ecc */
mfsdram(DDR0_22, value);
mtsdram(DDR0_22, (value & ~DDR0_22_CTRL_RAW_MASK)
| DDR0_22_CTRL_RAW_ECC_ENABLE);
sync();
eieio();
in_be32(ecc_mem);
pret = test_ecc_error();
/* if read data ok, 1 correctable error must be fixed */
if (pret != 3) {
debug("pret: expected 3, got %d\n", pret);
ret = 1;
}
/* test for uncorrectable error */
/* disconnect from ecc storage */
mfsdram(DDR0_22, value);
mtsdram(DDR0_22, (value & ~DDR0_22_CTRL_RAW_MASK)
| DDR0_22_CTRL_RAW_NO_ECC_RAM);
/* creating (uncorrectable) multiple-bit error */
out_be32(ecc_mem, ECC_PATTERN_UNCORR);
/* enable ecc */
mfsdram(DDR0_22, value);
mtsdram(DDR0_22, (value & ~DDR0_22_CTRL_RAW_MASK)
| DDR0_22_CTRL_RAW_ECC_ENABLE);
sync();
eieio();
in_be32(ecc_mem);
pret = test_ecc_error();
/* info about uncorrectable error must appear */
if (pret != 5) {
debug("pret: expected 5, got %d\n", pret);
ret = 1;
}
/* remove error from SDRAM */
out_be32(ecc_mem, ECC_PATTERN);
/* clear error caused by read-modify-write */
sync(); /* Wait for any pending memory accesses to complete. */
mfsdram(DDR0_00, value);
mtsdram(DDR0_00, value | DDR0_00_INT_ACK_ALL);
mfsdram(DDR0_22, value);
mtsdram(DDR0_22, (value & ~DDR0_22_CTRL_RAW_MASK)
| DDR0_22_CTRL_RAW_ECC_ENABLE);
}
static uint32_t get_ecc_status(void)
{
uint32_t int_status;
#if defined(DEBUG)
uint8_t syndrome;
uint32_t hdata, ldata, haddr, laddr;
uint32_t value;
#endif
mfsdram(DDR0_00, int_status);
int_status &= DDR0_00_INT_STATUS_MASK;
#if defined(DEBUG)
if (int_status & (DDR0_00_INT_STATUS_BIT0 | DDR0_00_INT_STATUS_BIT1)) {
mfsdram(DDR0_32, laddr);
mfsdram(DDR0_33, haddr);
haddr &= 0x00000001;
if (int_status & DDR0_00_INT_STATUS_BIT1)
debug("Multiple accesses");
else
debug("A single access");
debug(" outside the defined physical memory space detected\n"
" addr = 0x%01x%08x\n", haddr, laddr);
}
if (int_status & (DDR0_00_INT_STATUS_BIT2 | DDR0_00_INT_STATUS_BIT3)) {
unsigned int bit;
mfsdram(DDR0_23, value);
syndrome = (value >> 16) & 0xff;
for (bit = 0; bit < sizeof(syndrome_codes); bit++)
if (syndrome_codes[bit] == syndrome)
break;
mfsdram(DDR0_38, laddr);
mfsdram(DDR0_39, haddr);
haddr &= 0x00000001;
mfsdram(DDR0_40, ldata);
mfsdram(DDR0_41, hdata);
if (int_status & DDR0_00_INT_STATUS_BIT3)
debug("Multiple correctable ECC events");
else
debug("Single correctable ECC event");
debug(" detected\n 0x%01x%08x - 0x%08x%08x, bit - %d\n",
haddr, laddr, hdata, ldata, bit);
}
if (int_status & (DDR0_00_INT_STATUS_BIT4 | DDR0_00_INT_STATUS_BIT5)) {
mfsdram(DDR0_23, value);
syndrome = (value >> 8) & 0xff;
mfsdram(DDR0_34, laddr);
mfsdram(DDR0_35, haddr);
haddr &= 0x00000001;
mfsdram(DDR0_36, ldata);
mfsdram(DDR0_37, hdata);
if (int_status & DDR0_00_INT_STATUS_BIT5)
debug("Multiple uncorrectable ECC events");
else
debug("Single uncorrectable ECC event");
debug(" detected\n 0x%01x%08x - 0x%08x%08x, "
"syndrome - 0x%02x\n",
haddr, laddr, hdata, ldata, syndrome);
}
if (int_status & DDR0_00_INT_STATUS_BIT6)
debug("DRAM initialization complete\n");
#endif /* defined(DEBUG) */
return int_status;
}
static int test_ecc(uint32_t ecc_addr)
{
uint32_t value;
volatile uint32_t *const ecc_mem = (volatile uint32_t *)ecc_addr;
int ret = 0;
WATCHDOG_RESET();
debug("Entering test_ecc(0x%08x)\n", ecc_addr);
/* Set up correct ECC in memory */
disable_ecc();
clear_and_enable_ecc();
out_be32(ecc_mem, ECC_PATTERN);
out_be32(ecc_mem + 1, ECC_PATTERN);
/* Verify no ECC error reading back */
value = in_be32(ecc_mem);
disable_ecc();
if (ECC_PATTERN != value) {
debug("Data read error (no-error case): "
"expected 0x%08x, read 0x%08x\n", ECC_PATTERN, value);
ret = 1;
}
value = get_ecc_status();
if (0x00000000 != value) {
/* Expected no ECC status reported */
debug("get_ecc_status(): expected 0x%08x, got 0x%08x\n",
0x00000000, value);
ret = 1;
}
/* Test for correctable error by creating a one-bit error */
out_be32(ecc_mem, ECC_PATTERN_CORR);
clear_and_enable_ecc();
value = in_be32(ecc_mem);
disable_ecc();
/* Test that the corrected data was read */
if (ECC_PATTERN != value) {
debug("Data read error (correctable-error case): "
"expected 0x%08x, read 0x%08x\n", ECC_PATTERN, value);
ret = 1;
}
value = get_ecc_status();
if ((DDR0_00_INT_STATUS_BIT2 | DDR0_00_INT_STATUS_BIT7) != value) {
/* Expected a single correctable error reported */
debug("get_ecc_status(): expected 0x%08x, got 0x%08x\n",
DDR0_00_INT_STATUS_BIT2, value);
ret = 1;
}
/* Test for uncorrectable error by creating a two-bit error */
out_be32(ecc_mem, ECC_PATTERN_UNCORR);
clear_and_enable_ecc();
value = in_be32(ecc_mem);
disable_ecc();
/* Test that the corrected data was read */
if (ECC_PATTERN_UNCORR != value) {
debug("Data read error (uncorrectable-error case): "
"expected 0x%08x, read 0x%08x\n", ECC_PATTERN_UNCORR,
value);
ret = 1;
}
value = get_ecc_status();
if ((DDR0_00_INT_STATUS_BIT4 | DDR0_00_INT_STATUS_BIT7) != value) {
/* Expected a single uncorrectable error reported */
debug("get_ecc_status(): expected 0x%08x, got 0x%08x\n",
DDR0_00_INT_STATUS_BIT4, value);
ret = 1;
}
/* Remove error from SDRAM and enable ECC. */
out_be32(ecc_mem, ECC_PATTERN);
clear_and_enable_ecc();
sync();
eieio();
return ret;
}
int ecc_post_test (int flags)
int ecc_post_test(int flags)
{
int ret = 0;
unsigned long value;
unsigned long iaddr;
sync();
eieio();
uint32_t value;
uint32_t iaddr;
mfsdram(DDR0_22, value);
if (0x3 != DDR0_22_CTRL_RAW_DECODE(value)) {
@ -240,28 +249,23 @@ int ecc_post_test (int flags)
return 0;
}
/* mask all int */
/* Mask all interrupts. */
mfsdram(DDR0_01, value);
mtsdram(DDR0_01, (value & ~DDR0_01_INT_MASK_MASK)
| DDR0_01_INT_MASK_ALL_OFF);
/* clear error status */
mfsdram(DDR0_00, value);
mtsdram(DDR0_00, value | DDR0_00_INT_ACK_ALL);
for (iaddr = ECC_START_ADDR; iaddr <= ECC_STOP_ADDR; iaddr += iaddr) {
ret = test_ecc(iaddr);
if (ret)
break;
}
/*
* Clear possible errors resulting from ECC testing.
* If not done, then we could get an interrupt later on when
* exceptions are enabled.
* Clear possible errors resulting from ECC testing. (If not done, we
* we could get an interrupt later on when exceptions are enabled.)
*/
set_mcsr(get_mcsr());
debug("ecc_post_test() returning %d\n", ret);
return ret;
}
#endif /* CONFIG_POST & CFG_POST_ECC */
#endif /* defined(CONFIG_POST) && ... */

6
post/cpu/ppc4xx/spr.c
View File

@ -80,7 +80,9 @@ static struct {
{0x107, "SPRG7", 0x00000000, 0x00000000},
{0x10c, "TBL", 0x00000000, 0x00000000},
{0x10d, "TBU", 0x00000000, 0x00000000},
#ifdef CONFIG_440
{0x11e, "PIR", 0x0000000f, 0x00000000},
#endif
{0x130, "DBSR", 0x00000000, 0x00000000},
{0x134, "DBCR0", 0x00000000, 0x00000000},
{0x135, "DBCR1", 0x00000000, 0x00000000},
@ -95,6 +97,7 @@ static struct {
{0x13f, "DVC2", 0x00000000, 0x00000000},
{0x150, "TSR", 0x00000000, 0x00000000},
{0x154, "TCR", 0x00000000, 0x00000000},
#ifdef CONFIG_440
{0x190, "IVOR0", 0x0000fff0, 0x00000100},
{0x191, "IVOR1", 0x0000fff0, 0x00000200},
{0x192, "IVOR2", 0x0000fff0, 0x00000300},
@ -111,6 +114,7 @@ static struct {
{0x19d, "IVOR13", 0x0000fff0, 0x00001300},
{0x19e, "IVOR14", 0x0000fff0, 0x00001400},
{0x19f, "IVOR15", 0x0000fff0, 0x00002000},
#endif
{0x23a, "MCSRR0", 0x00000000, 0x00000000},
{0x23b, "MCSRR1", 0x00000000, 0x00000000},
{0x23c, "MCSR", 0x00000000, 0x00000000},
@ -131,8 +135,10 @@ static struct {
{0x395, "DTV1", 0x00000000, 0x00000000},
{0x396, "DTV2", 0x00000000, 0x00000000},
{0x397, "DTV3", 0x00000000, 0x00000000},
#ifdef CONFIG_440
{0x398, "DVLIM", 0x0fc1f83f, 0x0001f800},
{0x399, "IVLIM", 0x0fc1f83f, 0x0001f800},
#endif
{0x39b, "RSTCFG", 0x00000000, 0x00000000},
{0x39c, "DCDBTRL", 0x00000000, 0x00000000},
{0x39d, "DCDBTRH", 0x00000000, 0x00000000},