ARM: imx6q_logic: Correct phy fixup for broken ethernet
The Ethernet has been broken for some time. This patch unifies this board with a few others that use a similar approach to enabling phy. This fixes ar8031 Ethernet controller so it works. Signed-off-by: Adam Ford <aford173@gmail.com>
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@ -60,57 +60,6 @@ static iomux_v3_cfg_t const uart3_pads[] = {
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MX6_PAD_EIM_EB3__UART3_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
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MX6_PAD_EIM_EB3__UART3_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
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};
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};
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#ifndef CONFIG_SPL_BUILD
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static void fixup_enet_clock(void)
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{
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struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
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struct gpio_desc nint;
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struct gpio_desc reset;
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int ret;
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/* Set Ref Clock to 50 MHz */
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enable_fec_anatop_clock(0, ENET_50MHZ);
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/* Set GPIO_16 as ENET_REF_CLK_OUT */
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setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
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/* Request GPIO Pins to reset Ethernet with new clock */
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ret = dm_gpio_lookup_name("GPIO4_7", &nint);
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if (ret) {
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printf("Unable to lookup GPIO4_7\n");
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return;
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}
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ret = dm_gpio_request(&nint, "eth0_nInt");
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if (ret) {
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printf("Unable to request eth0_nInt\n");
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return;
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}
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/* Ensure nINT is input or PHY won't startup */
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dm_gpio_set_dir_flags(&nint, GPIOD_IS_IN);
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ret = dm_gpio_lookup_name("GPIO4_9", &reset);
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if (ret) {
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printf("Unable to lookup GPIO4_9\n");
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return;
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}
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ret = dm_gpio_request(&reset, "eth0_reset");
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if (ret) {
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printf("Unable to request eth0_reset\n");
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return;
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}
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/* Reset LAN8710A PHY */
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dm_gpio_set_dir_flags(&reset, GPIOD_IS_OUT);
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dm_gpio_set_value(&reset, 0);
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udelay(150);
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dm_gpio_set_value(&reset, 1);
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mdelay(50);
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}
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#endif
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static void setup_iomux_uart(void)
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static void setup_iomux_uart(void)
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{
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{
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imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
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imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
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@ -141,8 +90,33 @@ static void setup_nand_pins(void)
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imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));
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imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));
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}
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}
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static int ar8031_phy_fixup(struct phy_device *phydev)
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{
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unsigned short val;
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/* To enable AR8031 output a 125MHz clk from CLK_25M */
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phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
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phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
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phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
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val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
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val &= 0xffe3;
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val |= 0x18;
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phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
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/* introduce tx clock delay */
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
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val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
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val |= 0x0100;
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
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return 0;
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}
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int board_phy_config(struct phy_device *phydev)
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int board_phy_config(struct phy_device *phydev)
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{
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{
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ar8031_phy_fixup(phydev);
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if (phydev->drv->config)
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if (phydev->drv->config)
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phydev->drv->config(phydev);
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phydev->drv->config(phydev);
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@ -160,9 +134,6 @@ int overwrite_console(void)
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int board_early_init_f(void)
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int board_early_init_f(void)
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{
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{
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#ifndef CONFIG_SPL_BUILD
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fixup_enet_clock();
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#endif
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setup_iomux_uart();
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setup_iomux_uart();
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setup_nand_pins();
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setup_nand_pins();
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return 0;
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return 0;
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