Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'
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8dc16cf9dd
@ -230,6 +230,7 @@
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#define MXC_CSPICTRL_EN (1 << 0)
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#define MXC_CSPICTRL_MODE (1 << 1)
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#define MXC_CSPICTRL_XCH (1 << 2)
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#define MXC_CSPICTRL_MODE_MASK (0xf << 4)
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#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12)
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#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20)
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#define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12)
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@ -346,6 +346,7 @@ struct cspi_regs {
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#define MXC_CSPICTRL_EN (1 << 0)
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#define MXC_CSPICTRL_MODE (1 << 1)
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#define MXC_CSPICTRL_XCH (1 << 2)
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#define MXC_CSPICTRL_MODE_MASK (0xf << 4)
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#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12)
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#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20)
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#define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12)
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@ -137,11 +137,15 @@ static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs,
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return -1;
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}
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/* Reset spi */
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reg_write(®s->ctrl, 0);
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reg_write(®s->ctrl, MXC_CSPICTRL_EN);
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reg_ctrl = reg_read(®s->ctrl);
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/*
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* Reset SPI and set all CSs to master mode, if toggling
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* between slave and master mode we might see a glitch
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* on the clock line
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*/
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reg_ctrl = MXC_CSPICTRL_MODE_MASK;
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reg_write(®s->ctrl, reg_ctrl);
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reg_ctrl |= MXC_CSPICTRL_EN;
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reg_write(®s->ctrl, reg_ctrl);
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/*
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* The following computation is taken directly from Freescale's code.
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@ -174,9 +178,6 @@ static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs,
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reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_POSTDIV(0x0F)) |
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MXC_CSPICTRL_POSTDIV(post_div);
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/* always set to master mode */
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reg_ctrl |= 1 << (cs + 4);
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/* We need to disable SPI before changing registers */
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reg_ctrl &= ~MXC_CSPICTRL_EN;
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@ -148,7 +148,7 @@
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#define CONFIG_BOOTCOMMAND \
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"mmc dev ${mmcdev};" \
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"if mmc rescan ${mmcdev}; then " \
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"if mmc rescan; then " \
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"if run loadbootscript; then " \
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"run bootscript; " \
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"else " \
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