ARM64: zynqmp: Read RAM information from DT
Read information about memory from DT. This patch simplify life with synchronization between DT and board files. dram_init() only needs maximum RAM size below 4GB that's why please sort banks in memory node. dram_init_banksize() copies memory setup to bi_dram[]. This will avoid reading information from DT twice. Memory test start/end were changed to DDR location to let memtest still compiled. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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Michal Simek
parent
a3afb4a4bf
commit
8d59d7f63b
@ -50,12 +50,133 @@ int board_early_init_r(void)
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return 0;
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}
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#if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
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/*
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* fdt_get_reg - Fill buffer by information from DT
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*/
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static phys_size_t fdt_get_reg(const void *fdt, int nodeoffset, void *buf,
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const u32 *cell, int n)
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{
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int i = 0, b, banks;
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int parent_offset = fdt_parent_offset(fdt, nodeoffset);
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int address_cells = fdt_address_cells(fdt, parent_offset);
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int size_cells = fdt_size_cells(fdt, parent_offset);
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char *p = buf;
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phys_addr_t val;
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phys_size_t vals;
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debug("%s: addr_cells=%x, size_cell=%x, buf=%p, cell=%p\n",
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__func__, address_cells, size_cells, buf, cell);
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/* Check memory bank setup */
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banks = n % (address_cells + size_cells);
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if (banks)
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panic("Incorrect memory setup cells=%d, ac=%d, sc=%d\n",
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n, address_cells, size_cells);
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banks = n / (address_cells + size_cells);
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for (b = 0; b < banks; b++) {
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debug("%s: Bank #%d:\n", __func__, b);
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if (address_cells == 2) {
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val = cell[i + 1];
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val <<= 32;
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val |= cell[i];
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val = fdt64_to_cpu(val);
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debug("%s: addr64=%llx, ptr=%p, cell=%p\n",
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__func__, val, p, &cell[i]);
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*(phys_addr_t *)p = val;
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} else {
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debug("%s: addr32=%x, ptr=%p\n",
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__func__, fdt32_to_cpu(cell[i]), p);
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*(phys_addr_t *)p = fdt32_to_cpu(cell[i]);
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}
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p += sizeof(phys_addr_t);
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i += address_cells;
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debug("%s: pa=%p, i=%x, size=%zu\n", __func__, p, i,
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sizeof(phys_addr_t));
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if (size_cells == 2) {
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vals = cell[i + 1];
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vals <<= 32;
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vals |= cell[i];
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vals = fdt64_to_cpu(vals);
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debug("%s: size64=%llx, ptr=%p, cell=%p\n",
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__func__, vals, p, &cell[i]);
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*(phys_size_t *)p = vals;
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} else {
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debug("%s: size32=%x, ptr=%p\n",
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__func__, fdt32_to_cpu(cell[i]), p);
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*(phys_size_t *)p = fdt32_to_cpu(cell[i]);
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}
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p += sizeof(phys_size_t);
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i += size_cells;
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debug("%s: ps=%p, i=%x, size=%zu\n",
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__func__, p, i, sizeof(phys_size_t));
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}
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/* Return the first address size */
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return *(phys_size_t *)((char *)buf + sizeof(phys_addr_t));
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}
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#define FDT_REG_SIZE sizeof(u32)
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/* Temp location for sharing data for storing */
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/* Up to 64-bit address + 64-bit size */
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static u8 tmp[CONFIG_NR_DRAM_BANKS * 16];
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void dram_init_banksize(void)
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{
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int bank;
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memcpy(&gd->bd->bi_dram[0], &tmp, sizeof(tmp));
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for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
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debug("Bank #%d: start %llx\n", bank,
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(unsigned long long)gd->bd->bi_dram[bank].start);
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debug("Bank #%d: size %llx\n", bank,
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(unsigned long long)gd->bd->bi_dram[bank].size);
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}
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}
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int dram_init(void)
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{
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int node, len;
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const void *blob = gd->fdt_blob;
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const u32 *cell;
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memset(&tmp, 0, sizeof(tmp));
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/* find or create "/memory" node. */
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node = fdt_subnode_offset(blob, 0, "memory");
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if (node < 0) {
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printf("%s: Can't get memory node\n", __func__);
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return node;
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}
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/* Get pointer to cells and lenght of it */
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cell = fdt_getprop(blob, node, "reg", &len);
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if (!cell) {
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printf("%s: Can't get reg property\n", __func__);
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return -1;
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}
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gd->ram_size = fdt_get_reg(blob, node, &tmp, cell, len / FDT_REG_SIZE);
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debug("%s: Initial DRAM size %llx\n", __func__, gd->ram_size);
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return 0;
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}
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#else
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int dram_init(void)
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{
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gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
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return 0;
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}
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#endif
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void reset_cpu(ulong addr)
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{
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@ -26,8 +26,11 @@
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#define CONFIG_SYS_ALT_MEMTEST
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#define CONFIG_SYS_MEMTEST_SCRATCH 0xfffc0000
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#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
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#define CONFIG_SYS_MEMTEST_END CONFIG_SYS_SDRAM_SIZE
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#ifndef CONFIG_NR_DRAM_BANKS
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# define CONFIG_NR_DRAM_BANKS 2
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#endif
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#define CONFIG_SYS_MEMTEST_START 0
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#define CONFIG_SYS_MEMTEST_END 1000
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/* Have release address at the end of 256MB for now */
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#define CPU_RELEASE_ADDR 0xFFFFFF0
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@ -39,7 +42,7 @@
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# define CONFIG_IDENT_STRING " Xilinx ZynqMP"
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#endif
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#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
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#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE
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/* Flat Device Tree Definitions */
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@ -22,11 +22,6 @@
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#define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR, \
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ZYNQMP_USB1_XHCI_BASEADDR}
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/* Physical Memory Map */
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#define CONFIG_NR_DRAM_BANKS 1
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#define CONFIG_SYS_SDRAM_BASE 0
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#define CONFIG_SYS_SDRAM_SIZE 0x40000000
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#define COUNTER_FREQUENCY 4000000
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#include <configs/xilinx_zynqmp.h>
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