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powerpc/85xx: Fix NAND SPL support

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We cause CCSRBAR to be relocated in the SPL phase of NAND boot which
isn't expected and breaks things.  Fixing the board config.h to NOT
relocate CCSR during the CONFIG_NAND_SPL phase.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Kumar Gala 2011-11-09 09:10:49 -06:00
parent e4382acb1f
commit 8d22ddca3d
5 changed files with 5 additions and 5 deletions
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2
include/configs/MPC8536DS.h
View File

@ -131,7 +131,7 @@
#define CONFIG_SYS_CCSRBAR 0xffe00000
#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
#if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL)
#if defined(CONFIG_NAND_SPL)
#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
#endif

2
include/configs/MPC8569MDS.h
View File

@ -108,7 +108,7 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_SYS_CCSRBAR 0xe0000000
#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
#if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL)
#if defined(CONFIG_NAND_SPL)
#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
#endif

2
include/configs/MPC8572DS.h
View File

@ -115,7 +115,7 @@
#define CONFIG_SYS_CCSRBAR 0xffe00000
#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
#if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL)
#if defined(CONFIG_NAND_SPL)
#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
#endif

2
include/configs/P1_P2_RDB.h
View File

@ -151,7 +151,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_SYS_CCSRBAR 0xffe00000
#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
#if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL)
#if defined(CONFIG_NAND_SPL)
#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
#endif

2
include/configs/p1_p2_rdb_pc.h
View File

@ -221,7 +221,7 @@
/* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
SPL code*/
#if defined(CONFIG_NAND_U_BOOT) && defined(CONFIG_NAND_SPL)
#if defined(CONFIG_NAND_SPL)
#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
#endif