Merge branch 'master' of git://git.denx.de/u-boot-mips
This commit is contained in:
Wolfgang Denk
commit
8c65b8a937
@ -50,3 +50,5 @@ PLATFORM_CPPFLAGS += -DCONFIG_MIPS -D__MIPS__
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PLATFORM_CPPFLAGS += -G 0 -mabicalls -fpic
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PLATFORM_CPPFLAGS += -msoft-float
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PLATFORM_LDFLAGS += -G 0 -static -n -nostdlib
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PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections
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LDFLAGS_FINAL += --gc-sections
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@ -27,7 +27,7 @@ LIB = $(obj)lib$(CPU).o
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START = start.o
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SOBJS-y = cache.o
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COBJS-y = cpu.o interrupts.o
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COBJS-y = cpu.o interrupts.o time.o
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SRCS := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
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OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
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@ -51,75 +51,6 @@
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.set pop
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.endm
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/*
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* cacheop macro to automate cache operations
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* first some helpers...
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*/
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#define _mincache(size, maxsize) \
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bltu size,maxsize,9f ; \
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move size,maxsize ; \
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9:
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#define _align(minaddr, maxaddr, linesize) \
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.set noat ; \
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subu AT,linesize,1 ; \
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not AT ; \
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and minaddr,AT ; \
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addu maxaddr,-1 ; \
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and maxaddr,AT ; \
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.set at
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/* general operations */
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#define doop1(op1) \
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cache op1,0(a0)
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#define doop2(op1, op2) \
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cache op1,0(a0) ; \
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nop ; \
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cache op2,0(a0)
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/* specials for cache initialisation */
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#define doop1lw(op1) \
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lw zero,0(a0)
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#define doop1lw1(op1) \
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cache op1,0(a0) ; \
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lw zero,0(a0) ; \
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cache op1,0(a0)
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#define doop121(op1,op2) \
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cache op1,0(a0) ; \
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nop; \
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cache op2,0(a0) ; \
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nop; \
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cache op1,0(a0)
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#define _oploopn(minaddr, maxaddr, linesize, tag, ops) \
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.set noreorder ; \
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10: doop##tag##ops ; \
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bne minaddr,maxaddr,10b ; \
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add minaddr,linesize ; \
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.set reorder
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/* finally the cache operation macros */
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#define vcacheopn(kva, n, cacheSize, cacheLineSize, tag, ops) \
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blez n,11f ; \
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addu n,kva ; \
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_align(kva, n, cacheLineSize) ; \
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_oploopn(kva, n, cacheLineSize, tag, ops) ; \
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11:
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#define icacheopn(kva, n, cacheSize, cacheLineSize, tag, ops) \
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_mincache(n, cacheSize); \
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blez n,11f ; \
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addu n,kva ; \
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_align(kva, n, cacheLineSize) ; \
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_oploopn(kva, n, cacheLineSize, tag, ops) ; \
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11:
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#define vcacheop(kva, n, cacheSize, cacheLineSize, op) \
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vcacheopn(kva, n, cacheSize, cacheLineSize, 1, (op))
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#define icacheop(kva, n, cacheSize, cacheLineSize, op) \
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icacheopn(kva, n, cacheSize, cacheLineSize, 1, (op))
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.macro f_fill64 dst, offset, val
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LONG_S \val, (\offset + 0 * LONGSIZE)(\dst)
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LONG_S \val, (\offset + 1 * LONGSIZE)(\dst)
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@ -145,8 +76,8 @@
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* mips_init_icache(uint PRId, ulong icache_size, unchar icache_linesz)
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*/
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LEAF(mips_init_icache)
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blez a1, 9f
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mtc0 zero, CP0_TAGLO
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blez a1, 9f
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mtc0 zero, CP0_TAGLO
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/* clear tag to invalidate */
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PTR_LI t0, INDEX_BASE
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PTR_ADDU t1, t0, a1
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@ -163,15 +94,15 @@ LEAF(mips_init_icache)
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1: cache_op Index_Store_Tag_I t0
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PTR_ADDU t0, a2
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bne t0, t1, 1b
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9: jr ra
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9: jr ra
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END(mips_init_icache)
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/*
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* mips_init_dcache(uint PRId, ulong dcache_size, unchar dcache_linesz)
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*/
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LEAF(mips_init_dcache)
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blez a1, 9f
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mtc0 zero, CP0_TAGLO
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blez a1, 9f
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mtc0 zero, CP0_TAGLO
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/* clear all tags */
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PTR_LI t0, INDEX_BASE
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PTR_ADDU t1, t0, a1
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@ -188,25 +119,23 @@ LEAF(mips_init_dcache)
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1: cache_op Index_Store_Tag_D t0
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PTR_ADDU t0, a2
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bne t0, t1, 1b
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9: jr ra
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9: jr ra
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END(mips_init_dcache)
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/*******************************************************************************
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*
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* mips_cache_reset - low level initialisation of the primary caches
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*
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* This routine initialises the primary caches to ensure that they
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* have good parity. It must be called by the ROM before any cached locations
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* are used to prevent the possibility of data with bad parity being written to
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* memory.
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* To initialise the instruction cache it is essential that a source of data
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* with good parity is available. This routine
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* will initialise an area of memory starting at location zero to be used as
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* a source of parity.
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*
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* RETURNS: N/A
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*
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*/
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/*
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* mips_cache_reset - low level initialisation of the primary caches
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*
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* This routine initialises the primary caches to ensure that they have good
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* parity. It must be called by the ROM before any cached locations are used
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* to prevent the possibility of data with bad parity being written to memory.
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*
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* To initialise the instruction cache it is essential that a source of data
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* with good parity is available. This routine will initialise an area of
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* memory starting at location zero to be used as a source of parity.
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*
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* RETURNS: N/A
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*
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*/
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NESTED(mips_cache_reset, 0, ra)
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move RA, ra
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li t2, CONFIG_SYS_ICACHE_SIZE
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@ -254,13 +183,12 @@ NESTED(mips_cache_reset, 0, ra)
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jr RA
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END(mips_cache_reset)
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/*******************************************************************************
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*
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* dcache_status - get cache status
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*
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* RETURNS: 0 - cache disabled; 1 - cache enabled
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*
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*/
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/*
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* dcache_status - get cache status
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*
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* RETURNS: 0 - cache disabled; 1 - cache enabled
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*
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*/
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LEAF(dcache_status)
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mfc0 t0, CP0_CONFIG
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li t1, CONF_CM_UNCACHED
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@ -271,13 +199,12 @@ LEAF(dcache_status)
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2: jr ra
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END(dcache_status)
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/*******************************************************************************
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*
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* dcache_disable - disable cache
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*
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* RETURNS: N/A
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*
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*/
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/*
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* dcache_disable - disable cache
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*
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* RETURNS: N/A
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*
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*/
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LEAF(dcache_disable)
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mfc0 t0, CP0_CONFIG
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li t1, -8
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@ -287,13 +214,12 @@ LEAF(dcache_disable)
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jr ra
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END(dcache_disable)
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/*******************************************************************************
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*
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* dcache_enable - enable cache
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*
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* RETURNS: N/A
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*
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*/
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/*
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* dcache_enable - enable cache
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*
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* RETURNS: N/A
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*
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*/
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LEAF(dcache_enable)
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mfc0 t0, CP0_CONFIG
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ori t0, CONF_CM_CMASK
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@ -302,27 +228,3 @@ LEAF(dcache_enable)
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mtc0 t0, CP0_CONFIG
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jr ra
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END(dcache_enable)
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#ifdef CONFIG_SYS_INIT_RAM_LOCK_MIPS
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/*******************************************************************************
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*
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* mips_cache_lock - lock RAM area pointed to by a0 in cache.
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*
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* RETURNS: N/A
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*
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*/
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# define CACHE_LOCK_SIZE (CONFIG_SYS_DCACHE_SIZE)
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.globl mips_cache_lock
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.ent mips_cache_lock
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mips_cache_lock:
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li a1, CKSEG0 - CACHE_LOCK_SIZE
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addu a0, a1
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li a2, CACHE_LOCK_SIZE
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li a3, CONFIG_SYS_CACHELINE_SIZE
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move a1, a2
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icacheop(a0,a1,a2,a3,0x1d)
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jr ra
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.end mips_cache_lock
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#endif /* CONFIG_SYS_INIT_RAM_LOCK_MIPS */
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@ -62,11 +62,11 @@
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.globl _start
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.text
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_start:
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RVECENT(reset,0) /* U-boot entry point */
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RVECENT(reset,1) /* software reboot */
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#if defined(CONFIG_INCA_IP)
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.word INFINEON_EBU_BOOTCFG /* EBU init code, fetched during booting */
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.word 0x00000000 /* phase of the flash */
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RVECENT(reset,0) # U-boot entry point
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RVECENT(reset,1) # software reboot
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#ifdef CONFIG_INCA_IP
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.word INFINEON_EBU_BOOTCFG # EBU init code, fetched during
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.word 0x00000000 # booting phase of the flash
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#else
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RVECENT(romReserved,2)
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#endif
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@ -131,7 +131,7 @@ _start:
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RVECENT(romReserved,61)
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RVECENT(romReserved,62)
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RVECENT(romReserved,63)
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XVECENT(romExcHandle,0x200) /* bfc00200: R4000 tlbmiss vector */
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XVECENT(romExcHandle,0x200) # bfc00200: R4000 tlbmiss vector
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RVECENT(romReserved,65)
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RVECENT(romReserved,66)
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RVECENT(romReserved,67)
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@ -147,7 +147,7 @@ _start:
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RVECENT(romReserved,77)
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RVECENT(romReserved,78)
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RVECENT(romReserved,79)
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XVECENT(romExcHandle,0x280) /* bfc00280: R4000 xtlbmiss vector */
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XVECENT(romExcHandle,0x280) # bfc00280: R4000 xtlbmiss vector
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RVECENT(romReserved,81)
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RVECENT(romReserved,82)
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RVECENT(romReserved,83)
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@ -163,7 +163,7 @@ _start:
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RVECENT(romReserved,93)
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RVECENT(romReserved,94)
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RVECENT(romReserved,95)
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XVECENT(romExcHandle,0x300) /* bfc00300: R4000 cache vector */
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XVECENT(romExcHandle,0x300) # bfc00300: R4000 cache vector
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RVECENT(romReserved,97)
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RVECENT(romReserved,98)
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RVECENT(romReserved,99)
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@ -179,7 +179,7 @@ _start:
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RVECENT(romReserved,109)
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RVECENT(romReserved,110)
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RVECENT(romReserved,111)
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XVECENT(romExcHandle,0x380) /* bfc00380: R4000 general vector */
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XVECENT(romExcHandle,0x380) # bfc00380: R4000 general vector
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RVECENT(romReserved,113)
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RVECENT(romReserved,114)
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RVECENT(romReserved,115)
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@ -196,19 +196,19 @@ _start:
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RVECENT(romReserved,126)
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RVECENT(romReserved,127)
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/* We hope there are no more reserved vectors!
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/*
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* We hope there are no more reserved vectors!
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* 128 * 8 == 1024 == 0x400
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* so this is address R_VEC+0x400 == 0xbfc00400
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*/
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.align 4
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reset:
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/* Clear watch registers.
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*/
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/* Clear watch registers */
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mtc0 zero, CP0_WATCHLO
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mtc0 zero, CP0_WATCHHI
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/* WP(Watch Pending), SW0/1 should be cleared. */
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/* WP(Watch Pending), SW0/1 should be cleared */
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mtc0 zero, CP0_CAUSE
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setup_c0_status_reset
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@ -217,54 +217,42 @@ reset:
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mtc0 zero, CP0_COUNT
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mtc0 zero, CP0_COMPARE
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#if !defined(CONFIG_SKIP_LOWLEVEL_INIT)
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#ifndef CONFIG_SKIP_LOWLEVEL_INIT
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/* CONFIG0 register */
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li t0, CONF_CM_UNCACHED
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mtc0 t0, CP0_CONFIG
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#endif /* !CONFIG_SKIP_LOWLEVEL_INIT */
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#endif
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/* Initialize $gp.
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*/
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/* Initialize $gp */
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bal 1f
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nop
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nop
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.word _gp
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1:
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lw gp, 0(ra)
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#if !defined(CONFIG_SKIP_LOWLEVEL_INIT)
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/* Initialize any external memory.
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*/
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#ifndef CONFIG_SKIP_LOWLEVEL_INIT
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/* Initialize any external memory */
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la t9, lowlevel_init
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jalr t9
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nop
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nop
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/* Initialize caches...
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*/
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/* Initialize caches... */
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la t9, mips_cache_reset
|
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jalr t9
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nop
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nop
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|
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/* ... and enable them.
|
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*/
|
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/* ... and enable them */
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li t0, CONF_CM_CACHABLE_NONCOHERENT
|
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mtc0 t0, CP0_CONFIG
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#endif /* !CONFIG_SKIP_LOWLEVEL_INIT */
|
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|
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/* Set up temporary stack.
|
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*/
|
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#ifdef CONFIG_SYS_INIT_RAM_LOCK_MIPS
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li a0, CONFIG_SYS_INIT_SP_OFFSET
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la t9, mips_cache_lock
|
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jalr t9
|
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nop
|
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#endif
|
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|
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/* Set up temporary stack */
|
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li t0, CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET
|
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la sp, 0(t0)
|
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|
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la t9, board_init_f
|
||||
jr t9
|
||||
nop
|
||||
nop
|
||||
|
||||
/*
|
||||
* void relocate_code (addr_sp, gd, addr_moni)
|
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@ -279,13 +267,13 @@ reset:
|
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.globl relocate_code
|
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.ent relocate_code
|
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relocate_code:
|
||||
move sp, a0 /* Set new stack pointer */
|
||||
move sp, a0 # set new stack pointer
|
||||
|
||||
li t0, CONFIG_SYS_MONITOR_BASE
|
||||
la t3, in_ram
|
||||
lw t2, -12(t3) /* t2 <-- uboot_end_data */
|
||||
lw t2, -12(t3) # t2 <-- uboot_end_data
|
||||
move t1, a2
|
||||
move s2, a2 /* s2 <-- destination address */
|
||||
move s2, a2 # s2 <-- destination address
|
||||
|
||||
/*
|
||||
* Fix $gp:
|
||||
@ -294,8 +282,8 @@ relocate_code:
|
||||
*/
|
||||
move t6, gp
|
||||
sub gp, CONFIG_SYS_MONITOR_BASE
|
||||
add gp, a2 /* gp now adjusted */
|
||||
sub s1, gp, t6 /* s1 <-- relocation offset */
|
||||
add gp, a2 # gp now adjusted
|
||||
sub s1, gp, t6 # s1 <-- relocation offset
|
||||
|
||||
/*
|
||||
* t0 = source address
|
||||
@ -306,30 +294,28 @@ relocate_code:
|
||||
/*
|
||||
* Save destination address and size for later usage in flush_cache()
|
||||
*/
|
||||
move s0, a1 /* save gd in s0 */
|
||||
move a0, t1 /* a0 <-- destination addr */
|
||||
sub a1, t2, t0 /* a1 <-- size */
|
||||
move s0, a1 # save gd in s0
|
||||
move a0, t1 # a0 <-- destination addr
|
||||
sub a1, t2, t0 # a1 <-- size
|
||||
|
||||
1:
|
||||
lw t3, 0(t0)
|
||||
sw t3, 0(t1)
|
||||
addu t0, 4
|
||||
ble t0, t2, 1b
|
||||
addu t1, 4 /* delay slot */
|
||||
addu t1, 4
|
||||
|
||||
/* If caches were enabled, we would have to flush them here.
|
||||
*/
|
||||
/* If caches were enabled, we would have to flush them here. */
|
||||
|
||||
/* a0 & a1 are already set up for flush_cache(start, size) */
|
||||
la t9, flush_cache
|
||||
jalr t9
|
||||
nop
|
||||
nop
|
||||
|
||||
/* Jump to where we've relocated ourselves.
|
||||
*/
|
||||
/* Jump to where we've relocated ourselves */
|
||||
addi t0, s2, in_ram - _start
|
||||
jr t0
|
||||
nop
|
||||
nop
|
||||
|
||||
.word _gp
|
||||
.word _GLOBAL_OFFSET_TABLE_
|
||||
@ -344,45 +330,43 @@ in_ram:
|
||||
* GOT[0] is reserved. GOT[1] is also reserved for the dynamic object
|
||||
* generated by GNU ld. Skip these reserved entries from relocation.
|
||||
*/
|
||||
lw t3, -4(t0) /* t3 <-- num_got_entries */
|
||||
lw t4, -16(t0) /* t4 <-- _GLOBAL_OFFSET_TABLE_ */
|
||||
lw t5, -20(t0) /* t5 <-- _gp */
|
||||
sub t4, t5 /* compute offset*/
|
||||
add t4, t4, gp /* t4 now holds relocated _GLOBAL_OFFSET_TABLE_ */
|
||||
addi t4, t4, 8 /* Skipping first two entries. */
|
||||
lw t3, -4(t0) # t3 <-- num_got_entries
|
||||
lw t4, -16(t0) # t4 <-- _GLOBAL_OFFSET_TABLE_
|
||||
lw t5, -20(t0) # t5 <-- _gp
|
||||
sub t4, t5 # compute offset
|
||||
add t4, t4, gp # t4 now holds relocated _G_O_T_
|
||||
addi t4, t4, 8 # skipping first two entries
|
||||
li t2, 2
|
||||
1:
|
||||
lw t1, 0(t4)
|
||||
beqz t1, 2f
|
||||
add t1, s1
|
||||
add t1, s1
|
||||
sw t1, 0(t4)
|
||||
2:
|
||||
addi t2, 1
|
||||
blt t2, t3, 1b
|
||||
addi t4, 4 /* delay slot */
|
||||
addi t4, 4
|
||||
|
||||
/* Clear BSS.
|
||||
*/
|
||||
lw t1, -12(t0) /* t1 <-- uboot_end_data */
|
||||
lw t2, -8(t0) /* t2 <-- uboot_end */
|
||||
add t1, s1 /* adjust pointers */
|
||||
/* Clear BSS */
|
||||
lw t1, -12(t0) # t1 <-- uboot_end_data
|
||||
lw t2, -8(t0) # t2 <-- uboot_end
|
||||
add t1, s1 # adjust pointers
|
||||
add t2, s1
|
||||
|
||||
sub t1, 4
|
||||
1:
|
||||
addi t1, 4
|
||||
bltl t1, t2, 1b
|
||||
sw zero, 0(t1) /* delay slot */
|
||||
sw zero, 0(t1)
|
||||
|
||||
move a0, s0 /* a0 <-- gd */
|
||||
move a0, s0 # a0 <-- gd
|
||||
la t9, board_init_r
|
||||
jr t9
|
||||
move a1, s2 /* delay slot */
|
||||
move a1, s2
|
||||
|
||||
.end relocate_code
|
||||
|
||||
/* Exception handlers.
|
||||
*/
|
||||
/* Exception handlers */
|
||||
romReserved:
|
||||
b romReserved
|
||||
|
||||
|
||||
@ -33,7 +33,6 @@ COBJS-y += bootm_qemu_mips.o
|
||||
else
|
||||
COBJS-y += bootm.o
|
||||
endif
|
||||
COBJS-y += time.o
|
||||
|
||||
SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
|
||||
|
||||
@ -34,14 +34,14 @@ SECTIONS
|
||||
. = ALIGN(4);
|
||||
.text :
|
||||
{
|
||||
*(.text)
|
||||
*(.text*)
|
||||
}
|
||||
|
||||
. = ALIGN(4);
|
||||
.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
|
||||
|
||||
. = ALIGN(4);
|
||||
.data : { *(.data) }
|
||||
.data : { *(.data*) }
|
||||
|
||||
. = .;
|
||||
_gp = ALIGN(16) + 0x7ff0;
|
||||
@ -52,7 +52,7 @@ SECTIONS
|
||||
__got_end = .;
|
||||
}
|
||||
|
||||
.sdata : { *(.sdata) }
|
||||
.sdata : { *(.sdata*) }
|
||||
|
||||
.u_boot_cmd : {
|
||||
__u_boot_cmd_start = .;
|
||||
@ -64,7 +64,7 @@ SECTIONS
|
||||
num_got_entries = (__got_end - __got_start) >> 2;
|
||||
|
||||
. = ALIGN(4);
|
||||
.sbss (NOLOAD) : { *(.sbss) }
|
||||
.bss (NOLOAD) : { *(.bss) . = ALIGN(4); }
|
||||
.sbss (NOLOAD) : { *(.sbss*) }
|
||||
.bss (NOLOAD) : { *(.bss*) . = ALIGN(4); }
|
||||
uboot_end = .;
|
||||
}
|
||||
|
||||
@ -34,14 +34,14 @@ SECTIONS
|
||||
. = ALIGN(4);
|
||||
.text :
|
||||
{
|
||||
*(.text)
|
||||
*(.text*)
|
||||
}
|
||||
|
||||
. = ALIGN(4);
|
||||
.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
|
||||
|
||||
. = ALIGN(4);
|
||||
.data : { *(.data) }
|
||||
.data : { *(.data*) }
|
||||
|
||||
. = .;
|
||||
_gp = ALIGN(16) + 0x7ff0;
|
||||
@ -52,7 +52,7 @@ SECTIONS
|
||||
__got_end = .;
|
||||
}
|
||||
|
||||
.sdata : { *(.sdata) }
|
||||
.sdata : { *(.sdata*) }
|
||||
|
||||
.u_boot_cmd : {
|
||||
__u_boot_cmd_start = .;
|
||||
@ -64,7 +64,7 @@ SECTIONS
|
||||
num_got_entries = (__got_end - __got_start) >> 2;
|
||||
|
||||
. = ALIGN(4);
|
||||
.sbss (NOLOAD) : { *(.sbss) }
|
||||
.bss (NOLOAD) : { *(.bss) . = ALIGN(4); }
|
||||
.sbss (NOLOAD) : { *(.sbss*) }
|
||||
.bss (NOLOAD) : { *(.bss*) . = ALIGN(4); }
|
||||
uboot_end = .;
|
||||
}
|
||||
|
||||
@ -34,14 +34,14 @@ SECTIONS
|
||||
. = ALIGN(4);
|
||||
.text :
|
||||
{
|
||||
*(.text)
|
||||
*(.text*)
|
||||
}
|
||||
|
||||
. = ALIGN(4);
|
||||
.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
|
||||
|
||||
. = ALIGN(4);
|
||||
.data : { *(.data) }
|
||||
.data : { *(.data*) }
|
||||
|
||||
. = .;
|
||||
_gp = ALIGN(16) + 0x7ff0;
|
||||
@ -52,7 +52,7 @@ SECTIONS
|
||||
__got_end = .;
|
||||
}
|
||||
|
||||
.sdata : { *(.sdata) }
|
||||
.sdata : { *(.sdata*) }
|
||||
|
||||
.u_boot_cmd : {
|
||||
__u_boot_cmd_start = .;
|
||||
@ -64,7 +64,7 @@ SECTIONS
|
||||
num_got_entries = (__got_end - __got_start) >> 2;
|
||||
|
||||
. = ALIGN(4);
|
||||
.sbss (NOLOAD) : { *(.sbss) }
|
||||
.bss (NOLOAD) : { *(.bss) . = ALIGN(4); }
|
||||
.sbss (NOLOAD) : { *(.sbss*) }
|
||||
.bss (NOLOAD) : { *(.bss*) . = ALIGN(4); }
|
||||
uboot_end = .;
|
||||
}
|
||||
|
||||
@ -31,14 +31,14 @@ SECTIONS
|
||||
. = ALIGN(4);
|
||||
.text :
|
||||
{
|
||||
*(.text)
|
||||
*(.text*)
|
||||
}
|
||||
|
||||
. = ALIGN(4);
|
||||
.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
|
||||
|
||||
. = ALIGN(4);
|
||||
.data : { *(.data) }
|
||||
.data : { *(.data*) }
|
||||
|
||||
. = .;
|
||||
_gp = ALIGN(16) + 0x7ff0;
|
||||
@ -50,7 +50,7 @@ SECTIONS
|
||||
}
|
||||
|
||||
. = ALIGN(4);
|
||||
.sdata : { *(.sdata) }
|
||||
.sdata : { *(.sdata*) }
|
||||
|
||||
. = ALIGN(4);
|
||||
.u_boot_cmd : {
|
||||
@ -64,8 +64,8 @@ SECTIONS
|
||||
num_got_entries = (__got_end - __got_start) >> 2;
|
||||
|
||||
. = ALIGN(4);
|
||||
.sbss (NOLOAD) : { *(.sbss) }
|
||||
.sbss (NOLOAD) : { *(.sbss*) }
|
||||
. = ALIGN(4);
|
||||
.bss (NOLOAD) : { *(.bss) }
|
||||
.bss (NOLOAD) : { *(.bss*) }
|
||||
uboot_end = .;
|
||||
}
|
||||
|
||||
@ -34,14 +34,14 @@ SECTIONS
|
||||
. = ALIGN(4);
|
||||
.text :
|
||||
{
|
||||
*(.text)
|
||||
*(.text*)
|
||||
}
|
||||
|
||||
. = ALIGN(4);
|
||||
.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
|
||||
|
||||
. = ALIGN(4);
|
||||
.data : { *(.data) }
|
||||
.data : { *(.data*) }
|
||||
|
||||
. = .;
|
||||
_gp = ALIGN(16) + 0x7ff0;
|
||||
@ -52,7 +52,7 @@ SECTIONS
|
||||
__got_end = .;
|
||||
}
|
||||
|
||||
.sdata : { *(.sdata) }
|
||||
.sdata : { *(.sdata*) }
|
||||
|
||||
.u_boot_cmd : {
|
||||
__u_boot_cmd_start = .;
|
||||
@ -64,7 +64,7 @@ SECTIONS
|
||||
num_got_entries = (__got_end - __got_start) >> 2;
|
||||
|
||||
. = ALIGN(4);
|
||||
.sbss (NOLOAD) : { *(.sbss) }
|
||||
.bss (NOLOAD) : { *(.bss) . = ALIGN(4); }
|
||||
.sbss (NOLOAD) : { *(.sbss*) }
|
||||
.bss (NOLOAD) : { *(.bss*) . = ALIGN(4); }
|
||||
uboot_end = .;
|
||||
}
|
||||
|
||||
@ -34,14 +34,14 @@ SECTIONS
|
||||
. = ALIGN(4);
|
||||
.text :
|
||||
{
|
||||
*(.text)
|
||||
*(.text*)
|
||||
}
|
||||
|
||||
. = ALIGN(4);
|
||||
.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
|
||||
|
||||
. = ALIGN(4);
|
||||
.data : { *(.data) }
|
||||
.data : { *(.data*) }
|
||||
|
||||
. = .;
|
||||
_gp = ALIGN(16) +0x7ff0;
|
||||
@ -53,7 +53,7 @@ SECTIONS
|
||||
}
|
||||
|
||||
. = ALIGN(4);
|
||||
.sdata : { *(.sdata) }
|
||||
.sdata : { *(.sdata*) }
|
||||
|
||||
. = .;
|
||||
.u_boot_cmd : {
|
||||
@ -66,7 +66,7 @@ SECTIONS
|
||||
num_got_entries = (__got_end - __got_start) >> 2;
|
||||
|
||||
. = ALIGN(4);
|
||||
.sbss : { *(.sbss) }
|
||||
.bss : { *(.bss) . = ALIGN(4); }
|
||||
.sbss : { *(.sbss*) }
|
||||
.bss : { *(.bss*) . = ALIGN(4); }
|
||||
uboot_end = .;
|
||||
}
|
||||
|
||||
@ -34,14 +34,14 @@ SECTIONS
|
||||
. = ALIGN(4);
|
||||
.text :
|
||||
{
|
||||
*(.text)
|
||||
*(.text*)
|
||||
}
|
||||
|
||||
. = ALIGN(4);
|
||||
.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
|
||||
|
||||
. = ALIGN(4);
|
||||
.data : { *(.data) }
|
||||
.data : { *(.data*) }
|
||||
|
||||
. = .;
|
||||
_gp = ALIGN(16) + 0x7ff0;
|
||||
@ -52,7 +52,7 @@ SECTIONS
|
||||
__got_end = .;
|
||||
}
|
||||
|
||||
.sdata : { *(.sdata) }
|
||||
.sdata : { *(.sdata*) }
|
||||
|
||||
.u_boot_cmd : {
|
||||
__u_boot_cmd_start = .;
|
||||
@ -64,7 +64,7 @@ SECTIONS
|
||||
num_got_entries = (__got_end - __got_start) >> 2;
|
||||
|
||||
. = ALIGN(4);
|
||||
.sbss (NOLOAD) : { *(.sbss) }
|
||||
.bss (NOLOAD) : { *(.bss) . = ALIGN(4); }
|
||||
.sbss (NOLOAD) : { *(.sbss*) }
|
||||
.bss (NOLOAD) : { *(.bss*) . = ALIGN(4); }
|
||||
uboot_end = .;
|
||||
}
|
||||
|
||||
@ -30,14 +30,14 @@ SECTIONS
|
||||
{
|
||||
.text :
|
||||
{
|
||||
*(.text)
|
||||
*(.text*)
|
||||
}
|
||||
|
||||
. = ALIGN(4);
|
||||
.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
|
||||
|
||||
. = ALIGN(4);
|
||||
.data : { *(.data) }
|
||||
.data : { *(.data*) }
|
||||
|
||||
. = .;
|
||||
_gp = ALIGN(16) + 0x7ff0;
|
||||
@ -48,12 +48,12 @@ SECTIONS
|
||||
__got_end = .;
|
||||
}
|
||||
|
||||
.sdata : { *(.sdata) }
|
||||
.sdata : { *(.sdata*) }
|
||||
|
||||
. = ALIGN(4);
|
||||
__bss_start = .;
|
||||
.sbss (NOLOAD) : { *(.sbss) }
|
||||
.bss (NOLOAD) : { *(.bss) . = ALIGN(4); }
|
||||
.sbss (NOLOAD) : { *(.sbss*) }
|
||||
.bss (NOLOAD) : { *(.bss*) . = ALIGN(4); }
|
||||
|
||||
_end = .;
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user