cm_t3517: remove board
This board still doesn't select CONFIG_DM and seems to be umaintained. As it makes progress on modernizing several DaVinci drivers more difficult and the maintainer has not expressed interest in updating it, this patch proposes to remove it. Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
This commit is contained in:
Bartosz Golaszewski
Tom Rini
parent
3b88579c64
commit
8c2644ca69
@ -2716,7 +2716,6 @@
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#define MACH_TYPE_VPNEXT_MPU 2747
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#define MACH_TYPE_BCMRING_TABLET_V1 2748
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#define MACH_TYPE_SGARM10 2749
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#define MACH_TYPE_CM_T3517 2750
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#define MACH_TYPE_OMAP3_CPS 2751
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#define MACH_TYPE_AXAR1500_RECEIVER 2752
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#define MACH_TYPE_WBD222 2753
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@ -54,12 +54,6 @@ config TARGET_CM_T35
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select OMAP3_GPIO_5
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select OMAP3_GPIO_6 if LED_STATUS
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config TARGET_CM_T3517
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bool "CompuLab CM-T3517 boards"
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select OMAP3_GPIO_2
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select OMAP3_GPIO_5
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select OMAP3_GPIO_6 if LED_STATUS
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config TARGET_DEVKIT8000
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bool "TimLL OMAP3 Devkit8000"
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select DM
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@ -198,7 +192,6 @@ source "board/logicpd/am3517evm/Kconfig"
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source "board/teejet/mt_ventoux/Kconfig"
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source "board/ti/beagle/Kconfig"
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source "board/compulab/cm_t35/Kconfig"
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source "board/compulab/cm_t3517/Kconfig"
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source "board/timll/devkit8000/Kconfig"
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source "board/ti/evm/Kconfig"
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source "board/isee/igep00x0/Kconfig"
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@ -1,12 +0,0 @@
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if TARGET_CM_T3517
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config SYS_BOARD
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default "cm_t3517"
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config SYS_VENDOR
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default "compulab"
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config SYS_CONFIG_NAME
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default "cm_t3517"
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endif
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@ -1,6 +0,0 @@
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CM_T3517 BOARD
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M: Igor Grinberg <grinberg@compulab.co.il>
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S: Maintained
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F: board/compulab/cm_t3517/
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F: include/configs/cm_t3517.h
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F: configs/cm_t3517_defconfig
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@ -1,7 +0,0 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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# (C) Copyright 2014 CompuLab, Ltd. <www.compulab.co.il>
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#
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# Authors: Igor Grinberg <grinberg@compulab.co.il>
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obj-y += cm_t3517.o mux.o
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@ -1,240 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2014 CompuLab, Ltd. <www.compulab.co.il>
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*
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* Authors: Igor Grinberg <grinberg@compulab.co.il>
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*/
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#include <common.h>
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#include <environment.h>
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#include <status_led.h>
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#include <net.h>
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#include <netdev.h>
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#include <usb.h>
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#include <mmc.h>
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#include <linux/compiler.h>
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#include <linux/usb/musb.h>
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#include <asm/io.h>
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#include <asm/arch/mem.h>
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#include <asm/arch/am35x_def.h>
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#include <asm/arch/mmc_host_def.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/musb.h>
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#include <asm/omap_musb.h>
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#include <asm/ehci-omap.h>
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#include "../common/common.h"
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#include "../common/eeprom.h"
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DECLARE_GLOBAL_DATA_PTR;
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const omap3_sysinfo sysinfo = {
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DDR_DISCRETE,
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"CM-T3517 board",
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"NAND 128/512M",
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};
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#ifdef CONFIG_USB_MUSB_AM35X
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static struct musb_hdrc_config cm_t3517_musb_config = {
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.multipoint = 1,
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.dyn_fifo = 1,
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.num_eps = 16,
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.ram_bits = 12,
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};
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static struct omap_musb_board_data cm_t3517_musb_board_data = {
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.set_phy_power = am35x_musb_phy_power,
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.clear_irq = am35x_musb_clear_irq,
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.reset = am35x_musb_reset,
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};
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static struct musb_hdrc_platform_data cm_t3517_musb_pdata = {
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#if defined(CONFIG_USB_MUSB_HOST)
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.mode = MUSB_HOST,
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#elif defined(CONFIG_USB_MUSB_GADGET)
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.mode = MUSB_PERIPHERAL,
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#else
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#error "Please define either CONFIG_USB_MUSB_HOST or CONFIG_USB_MUSB_GADGET"
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#endif
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.config = &cm_t3517_musb_config,
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.power = 250,
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.platform_ops = &am35x_ops,
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.board_data = &cm_t3517_musb_board_data,
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};
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static void cm_t3517_musb_init(void)
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{
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/*
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* Set up USB clock/mode in the DEVCONF2 register.
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* USB2.0 PHY reference clock is 13 MHz
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*/
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clrsetbits_le32(&am35x_scm_general_regs->devconf2,
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CONF2_REFFREQ | CONF2_OTGMODE | CONF2_PHY_GPIOMODE,
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CONF2_REFFREQ_13MHZ | CONF2_SESENDEN |
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CONF2_VBDTCTEN | CONF2_DATPOL);
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if (!musb_register(&cm_t3517_musb_pdata, &cm_t3517_musb_board_data,
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(void *)AM35XX_IPSS_USBOTGSS_BASE))
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printf("Failed initializing AM35x MUSB!\n");
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}
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#else
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static inline void am3517_evm_musb_init(void) {}
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#endif
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int board_init(void)
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{
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gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
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/* boot param addr */
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gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
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#if defined(CONFIG_LED_STATUS) && defined(CONFIG_LED_STATUS_BOOT_ENABLE)
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status_led_set(CONFIG_LED_STATUS_BOOT, CONFIG_LED_STATUS_ON);
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#endif
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cm_t3517_musb_init();
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return 0;
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}
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/*
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* Routine: get_board_rev
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* Description: read system revision
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*/
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u32 get_board_rev(void)
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{
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return cl_eeprom_get_board_rev(CONFIG_SYS_I2C_EEPROM_BUS);
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};
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int misc_init_r(void)
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{
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cl_print_pcb_info();
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omap_die_id_display();
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return 0;
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}
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#if defined(CONFIG_MMC)
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#define SB_T35_CD_GPIO 144
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#define SB_T35_WP_GPIO 59
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int board_mmc_init(bd_t *bis)
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{
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return omap_mmc_init(0, 0, 0, SB_T35_CD_GPIO, SB_T35_WP_GPIO);
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}
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#endif
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#ifdef CONFIG_DRIVER_TI_EMAC
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#define CONTROL_EFUSE_EMAC_LSB 0x48002380
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#define CONTROL_EFUSE_EMAC_MSB 0x48002384
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static int am3517_get_efuse_enetaddr(u8 *enetaddr)
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{
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u32 lsb = __raw_readl(CONTROL_EFUSE_EMAC_LSB);
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u32 msb = __raw_readl(CONTROL_EFUSE_EMAC_MSB);
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enetaddr[0] = (u8)((msb >> 16) & 0xff);
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enetaddr[1] = (u8)((msb >> 8) & 0xff);
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enetaddr[2] = (u8)(msb & 0xff);
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enetaddr[3] = (u8)((lsb >> 16) & 0xff);
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enetaddr[4] = (u8)((lsb >> 8) & 0xff);
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enetaddr[5] = (u8)(lsb & 0xff);
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return is_valid_ethaddr(enetaddr);
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}
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static inline int cm_t3517_init_emac(bd_t *bis)
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{
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int ret = cpu_eth_init(bis);
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if (ret > 0)
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return ret;
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printf("Failed initializing EMAC! ");
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return 0;
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}
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#else /* !CONFIG_DRIVER_TI_EMAC */
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static inline int am3517_get_efuse_enetaddr(u8 *enetaddr) { return 1; }
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static inline int cm_t3517_init_emac(bd_t *bis) { return 0; }
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#endif /* CONFIG_DRIVER_TI_EMAC */
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/*
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* Routine: handle_mac_address
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* Description: prepare MAC address for on-board Ethernet.
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*/
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static int cm_t3517_handle_mac_address(void)
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{
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unsigned char enetaddr[6];
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int ret;
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ret = eth_env_get_enetaddr("ethaddr", enetaddr);
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if (ret)
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return 0;
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ret = cl_eeprom_read_mac_addr(enetaddr, CONFIG_SYS_I2C_EEPROM_BUS);
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if (ret) {
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ret = am3517_get_efuse_enetaddr(enetaddr);
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if (ret)
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return ret;
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}
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if (!is_valid_ethaddr(enetaddr))
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return -1;
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return eth_env_set_enetaddr("ethaddr", enetaddr);
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}
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#define SB_T35_ETH_RST_GPIO 164
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/*
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* Routine: board_eth_init
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* Description: initialize module and base-board Ethernet chips
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*/
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int board_eth_init(bd_t *bis)
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{
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int rc = 0, rc1 = 0;
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rc1 = cm_t3517_handle_mac_address();
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if (rc1)
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printf("No MAC address found! ");
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rc1 = cm_t3517_init_emac(bis);
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if (rc1 > 0)
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rc++;
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rc1 = cl_omap3_smc911x_init(0, 4, CONFIG_SMC911X_BASE,
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NULL, SB_T35_ETH_RST_GPIO);
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if (rc1 > 0)
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rc++;
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return rc;
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}
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#ifdef CONFIG_USB_EHCI_OMAP
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static struct omap_usbhs_board_data cm_t3517_usbhs_bdata = {
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.port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
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.port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
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.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
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};
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#define CM_T3517_USB_HUB_RESET_GPIO 152
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#define SB_T35_USB_HUB_RESET_GPIO 98
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int ehci_hcd_init(int index, enum usb_init_type init,
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struct ehci_hccr **hccr, struct ehci_hcor **hcor)
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{
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cl_usb_hub_init(CM_T3517_USB_HUB_RESET_GPIO, "cm-t3517 hub rst");
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cl_usb_hub_init(SB_T35_USB_HUB_RESET_GPIO, "sb-t35 hub rst");
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return omap_ehci_hcd_init(index, &cm_t3517_usbhs_bdata, hccr, hcor);
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}
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int ehci_hcd_stop(void)
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{
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cl_usb_hub_deinit(CM_T3517_USB_HUB_RESET_GPIO);
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cl_usb_hub_deinit(SB_T35_USB_HUB_RESET_GPIO);
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return omap_ehci_hcd_stop();
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}
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#endif /* CONFIG_USB_EHCI_OMAP */
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@ -1,235 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2014 CompuLab, Ltd. <www.compulab.co.il>
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*
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* Authors: Igor Grinberg <grinberg@compulab.co.il>
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*/
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#include <common.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/mux.h>
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#include <asm/io.h>
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void set_muxconf_regs(void)
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{
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/* SDRC */
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MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0));
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MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M7));
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/* GPMC */
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MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0));
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MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0));
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MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0));
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MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0));
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MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0));
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MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0));
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MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0));
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MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0));
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MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0));
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MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0));
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MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0));
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MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0));
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MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0));
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MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0));
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MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0));
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MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0));
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MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0));
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MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0));
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MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0));
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MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0));
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MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0));
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MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0));
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MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0));
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MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0));
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MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0));
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MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0));
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MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0));
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/* SB-T35 Ethernet */
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MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M0));
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/* DVI enable */
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MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | DIS | M4));/*GPIO_54*/
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/* DataImage backlight */
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MUX_VAL(CP(GPMC_NCS7), (IDIS | PTU | DIS | M4));/*GPIO_58*/
|
||||
|
||||
/* SB-T35 SD/MMC WP GPIO59 */
|
||||
MUX_VAL(CP(GPMC_CLK), (IEN | PTU | EN | M4)); /*GPIO_59*/
|
||||
MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0));
|
||||
MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0));
|
||||
MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0));
|
||||
MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0));
|
||||
/* SB-T35 Audio Enable GPIO61 */
|
||||
MUX_VAL(CP(GPMC_NBE1), (IDIS | PTU | EN | M4)); /*GPIO_61*/
|
||||
MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0));
|
||||
MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0));
|
||||
/* SB-T35 Ethernet IRQ GPIO65 */
|
||||
MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M4)); /*GPIO_65*/
|
||||
|
||||
/* UART3 Console */
|
||||
MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0));
|
||||
MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0));
|
||||
/* RTC V3020 nCS GPIO163 */
|
||||
MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTU | EN | M4)); /*GPIO_163*/
|
||||
/* SB-T35 Ethernet nRESET GPIO164 */
|
||||
MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTU | EN | M4)); /*GPIO_164*/
|
||||
|
||||
/* SB-T35 SD/MMC CD GPIO144 */
|
||||
MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M4)); /*GPIO_144*/
|
||||
/* WIFI nRESET GPIO145 */
|
||||
MUX_VAL(CP(UART2_RTS), (IEN | PTD | EN | M4)); /*GPIO_145*/
|
||||
/* USB1 PHY Reset GPIO 146 */
|
||||
MUX_VAL(CP(UART2_TX), (IEN | PTD | EN | M4)); /*GPIO_146*/
|
||||
/* USB2 PHY Reset GPIO 147 */
|
||||
MUX_VAL(CP(UART2_RX), (IEN | PTD | EN | M4)); /*GPIO_147*/
|
||||
|
||||
/* MMC1 */
|
||||
MUX_VAL(CP(MMC1_CLK), (IEN | PTU | EN | M0));
|
||||
MUX_VAL(CP(MMC1_CMD), (IEN | PTU | DIS | M0));
|
||||
MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | DIS | M0));
|
||||
MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | DIS | M0));
|
||||
MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | DIS | M0));
|
||||
MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | DIS | M0));
|
||||
|
||||
/* DSS */
|
||||
MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0));
|
||||
MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0));
|
||||
MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0));
|
||||
MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0));
|
||||
MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0));
|
||||
MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0));
|
||||
MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0));
|
||||
MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0));
|
||||
MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0));
|
||||
MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0));
|
||||
MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0));
|
||||
MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0));
|
||||
MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0));
|
||||
MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0));
|
||||
MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0));
|
||||
MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0));
|
||||
MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0));
|
||||
MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0));
|
||||
MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0));
|
||||
MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0));
|
||||
MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0));
|
||||
MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0));
|
||||
MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0));
|
||||
MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0));
|
||||
MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0));
|
||||
MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0));
|
||||
MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0));
|
||||
MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0));
|
||||
|
||||
/* I2C */
|
||||
MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0));
|
||||
MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0));
|
||||
MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0));
|
||||
MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0));
|
||||
|
||||
/* SB-T35 USB HUB Reset GPIO98 */
|
||||
MUX_VAL(CP(CCDC_WEN), (IDIS | PTU | EN | M4)); /*GPIO_98*/
|
||||
/* CM-T3517 USB HUB Reset GPIO152 */
|
||||
MUX_VAL(CP(MCBSP4_CLKX), (IDIS | PTD | DIS | M4)); /*GPIO_152*/
|
||||
|
||||
/* RMII */
|
||||
MUX_VAL(CP(RMII_MDIO_DATA), (IEN | PTU | EN | M0));
|
||||
MUX_VAL(CP(RMII_MDIO_CLK), (M0));
|
||||
MUX_VAL(CP(RMII_RXD0), (IEN | PTD | DIS | M0));
|
||||
MUX_VAL(CP(RMII_RXD1), (IEN | PTD | DIS | M0));
|
||||
MUX_VAL(CP(RMII_CRS_DV), (IEN | PTD | DIS | M0));
|
||||
MUX_VAL(CP(RMII_RXER), (IEN | PTD | DIS | M0));
|
||||
MUX_VAL(CP(RMII_TXD0), (IDIS | M0));
|
||||
MUX_VAL(CP(RMII_TXD1), (IDIS | M0));
|
||||
MUX_VAL(CP(RMII_TXEN), (IDIS | M0));
|
||||
MUX_VAL(CP(RMII_50MHZ_CLK), (IEN | PTU | DIS | M0));
|
||||
|
||||
/* Green LED GPIO186 */
|
||||
MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTU | DIS | M4)); /*GPIO_186*/
|
||||
|
||||
/* SPI */
|
||||
MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M1)); /*MCSPI4_CLK*/
|
||||
MUX_VAL(CP(MCBSP1_DX), (IEN | PTD | DIS | M1)); /*MCSPI4_SIMO*/
|
||||
MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M1)); /*MCSPI4_SOMI*/
|
||||
MUX_VAL(CP(MCBSP1_FSX), (IEN | PTU | EN | M1)); /*MCSPI4_CS0*/
|
||||
/* LCD reset GPIO157 */
|
||||
MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | DIS | M4)); /*GPIO_157*/
|
||||
|
||||
/* RTC V3020 CS Enable GPIO160 */
|
||||
MUX_VAL(CP(MCBSP_CLKS), (IEN | PTD | EN | M4)); /*GPIO_160*/
|
||||
/* SB-T35 LVDS Transmitter SHDN GPIO162 */
|
||||
MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTU | DIS | M4)); /*GPIO_162*/
|
||||
|
||||
/* USB0 - mUSB */
|
||||
MUX_VAL(CP(USB0_DRVBUS), (IEN | PTD | EN | M0));
|
||||
/* USB1 EHCI */
|
||||
MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT0*/
|
||||
MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT1*/
|
||||
MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT2*/
|
||||
MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT3*/
|
||||
MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT4*/
|
||||
MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT5*/
|
||||
MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT6*/
|
||||
MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT7*/
|
||||
MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DIR*/
|
||||
MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_NXT*/
|
||||
MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M3)); /*HSUSB1_CLK*/
|
||||
MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | DIS | M3)); /*HSUSB1_STP*/
|
||||
/* USB2 EHCI */
|
||||
MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DT0*/
|
||||
MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DT1*/
|
||||
MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M3)); /*HSUSB2_DT2*/
|
||||
MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M3)); /*HSUSB2_DT3*/
|
||||
MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | EN | M3)); /*HSUSB2_DT4*/
|
||||
MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | EN | M3)); /*HSUSB2_DT5*/
|
||||
MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M3)); /*HSUSB2_DT6*/
|
||||
MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | EN | M3)); /*HSUSB2_DT7*/
|
||||
MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DIR*/
|
||||
MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_NXT*/
|
||||
MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTD | DIS | M3)); /*HSUSB2_CLK*/
|
||||
MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTU | DIS | M3)); /*HSUSB2_STP*/
|
||||
|
||||
/* SYS_BOOT */
|
||||
MUX_VAL(CP(SYS_BOOT0), (IEN | PTU | DIS | M4)); /*GPIO_2*/
|
||||
MUX_VAL(CP(SYS_BOOT1), (IEN | PTU | DIS | M4)); /*GPIO_3*/
|
||||
MUX_VAL(CP(SYS_BOOT2), (IEN | PTU | DIS | M4)); /*GPIO_4*/
|
||||
MUX_VAL(CP(SYS_BOOT3), (IEN | PTU | DIS | M4)); /*GPIO_5*/
|
||||
MUX_VAL(CP(SYS_BOOT4), (IEN | PTU | DIS | M4)); /*GPIO_6*/
|
||||
MUX_VAL(CP(SYS_BOOT5), (IEN | PTU | DIS | M4)); /*GPIO_7*/
|
||||
}
|
||||
@ -410,7 +410,7 @@ struct eeprom_field layout_legacy[5] = {
|
||||
#define layout_legacy layout_unknown
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_CM_T3X) || defined(CONFIG_CM_T3517)
|
||||
#if defined(CONFIG_CM_T3X)
|
||||
struct eeprom_field layout_v1[12] = {
|
||||
{ "Major Revision", 2, NULL, DEFINE_PRINT_UPDATE(bin_ver) },
|
||||
{ "Minor Revision", 2, NULL, DEFINE_PRINT_UPDATE(bin_ver) },
|
||||
|
||||
@ -1,60 +0,0 @@
|
||||
CONFIG_ARM=y
|
||||
# CONFIG_SYS_THUMB_BUILD is not set
|
||||
CONFIG_ARCH_OMAP2PLUS=y
|
||||
CONFIG_SYS_TEXT_BASE=0x80008000
|
||||
CONFIG_TARGET_CM_T3517=y
|
||||
CONFIG_EMIF4=y
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
CONFIG_BOOTDELAY=3
|
||||
# CONFIG_CONSOLE_MUX is not set
|
||||
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
|
||||
CONFIG_HUSH_PARSER=y
|
||||
CONFIG_SYS_PROMPT="CM-T3517 # "
|
||||
CONFIG_CMD_BOOTZ=y
|
||||
CONFIG_CMD_EEPROM=y
|
||||
CONFIG_CMD_EEPROM_LAYOUT=y
|
||||
CONFIG_EEPROM_LAYOUT_HELP_STRING="v1, v2, v3"
|
||||
# CONFIG_CMD_FLASH is not set
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_NAND=y
|
||||
CONFIG_CMD_USB=y
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_CMD_DHCP=y
|
||||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_BMP=y
|
||||
CONFIG_CMD_CACHE=y
|
||||
CONFIG_CMD_EXT2=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_CMD_MTDPARTS=y
|
||||
CONFIG_MTDIDS_DEFAULT="nand0=nand"
|
||||
CONFIG_MTDPARTS_DEFAULT="mtdparts=nand:512k(x-loader),1920k(u-boot),256k(u-boot-env),4m(kernel),-(fs)"
|
||||
CONFIG_ENV_IS_IN_NAND=y
|
||||
CONFIG_SYS_OMAP24_I2C_SPEED=400000
|
||||
CONFIG_LED_STATUS=y
|
||||
CONFIG_LED_STATUS_GPIO=y
|
||||
CONFIG_LED_STATUS0=y
|
||||
CONFIG_LED_STATUS_BIT=186
|
||||
CONFIG_LED_STATUS_STATE=2
|
||||
CONFIG_LED_STATUS_BOOT_ENABLE=y
|
||||
CONFIG_LED_STATUS_BOOT=0
|
||||
CONFIG_MMC_OMAP_HS=y
|
||||
CONFIG_NAND=y
|
||||
CONFIG_MII=y
|
||||
CONFIG_SMC911X=y
|
||||
CONFIG_SMC911X_BASE=0x2D000000
|
||||
CONFIG_SMC911X_32_BIT=y
|
||||
CONFIG_DRIVER_TI_EMAC=y
|
||||
CONFIG_CONS_INDEX=3
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_OMAP3_SPI=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_MUSB_HOST=y
|
||||
CONFIG_USB_MUSB_AM35X=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_USB_GADGET=y
|
||||
CONFIG_VIDEO_OMAP3=y
|
||||
CONFIG_LCD=y
|
||||
CONFIG_OF_LIBFDT=y
|
||||
@ -1,219 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* (C) Copyright 2013 CompuLab, Ltd.
|
||||
* Author: Igor Grinberg <grinberg@compulab.co.il>
|
||||
*
|
||||
* Configuration settings for the CompuLab CM-T3517 board
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/*
|
||||
* High Level Configuration Options
|
||||
*/
|
||||
#define CONFIG_CM_T3517 /* working with CM-T3517 */
|
||||
|
||||
/*
|
||||
* This is needed for the DMA stuff.
|
||||
* Although the default iss 64, we still define it
|
||||
* to be on the safe side once the default is changed.
|
||||
*/
|
||||
|
||||
#include <asm/arch/cpu.h> /* get chip and board defs */
|
||||
#include <asm/arch/omap.h>
|
||||
|
||||
#define CONFIG_MACH_TYPE MACH_TYPE_CM_T3517
|
||||
|
||||
/* Clock Defines */
|
||||
#define V_OSCK 26000000 /* Clock output from T2 */
|
||||
#define V_SCLK (V_OSCK >> 1)
|
||||
|
||||
/*
|
||||
* The early kernel mapping on ARM currently only maps from the base of DRAM
|
||||
* to the end of the kernel image. The kernel is loaded at DRAM base + 0x8000.
|
||||
* The early kernel pagetable uses DRAM base + 0x4000 to DRAM base + 0x8000,
|
||||
* so that leaves DRAM base to DRAM base + 0x4000 available.
|
||||
*/
|
||||
#define CONFIG_SYS_BOOTMAPSZ 0x4000
|
||||
|
||||
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
|
||||
#define CONFIG_SETUP_MEMORY_TAGS
|
||||
#define CONFIG_INITRD_TAG
|
||||
#define CONFIG_REVISION_TAG
|
||||
#define CONFIG_SERIAL_TAG
|
||||
|
||||
/*
|
||||
* Size of malloc() pool
|
||||
*/
|
||||
#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
|
||||
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
|
||||
|
||||
/*
|
||||
* Hardware drivers
|
||||
*/
|
||||
|
||||
/*
|
||||
* NS16550 Configuration
|
||||
*/
|
||||
#define CONFIG_SYS_NS16550_SERIAL
|
||||
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
|
||||
#define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
|
||||
|
||||
/*
|
||||
* select serial console configuration
|
||||
*/
|
||||
#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
|
||||
|
||||
/* allow to overwrite serial and ethaddr */
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
|
||||
115200}
|
||||
|
||||
/* USB */
|
||||
|
||||
#ifndef CONFIG_USB_MUSB_AM35X
|
||||
#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 146
|
||||
#define CONFIG_OMAP_EHCI_PHY2_RESET_GPIO 147
|
||||
#endif /* CONFIG_USB_MUSB_AM35X */
|
||||
|
||||
/* commands to include */
|
||||
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
|
||||
#define CONFIG_SYS_I2C_EEPROM_BUS 0
|
||||
#define CONFIG_I2C_MULTI_BUS
|
||||
|
||||
/*
|
||||
* Board NAND Info.
|
||||
*/
|
||||
#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
|
||||
/* to access nand at */
|
||||
/* CS0 */
|
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
|
||||
/* devices */
|
||||
|
||||
/* Environment information */
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"loadaddr=0x82000000\0" \
|
||||
"baudrate=115200\0" \
|
||||
"console=ttyO2,115200n8\0" \
|
||||
"netretry=yes\0" \
|
||||
"mpurate=auto\0" \
|
||||
"vram=12M\0" \
|
||||
"dvimode=1024x768MR-16@60\0" \
|
||||
"defaultdisplay=dvi\0" \
|
||||
"mmcdev=0\0" \
|
||||
"mmcroot=/dev/mmcblk0p2 rw rootwait\0" \
|
||||
"mmcrootfstype=ext4\0" \
|
||||
"nandroot=/dev/mtdblock4 rw\0" \
|
||||
"nandrootfstype=ubifs\0" \
|
||||
"mmcargs=setenv bootargs console=${console} " \
|
||||
"mpurate=${mpurate} " \
|
||||
"vram=${vram} " \
|
||||
"omapfb.mode=dvi:${dvimode} " \
|
||||
"omapdss.def_disp=${defaultdisplay} " \
|
||||
"root=${mmcroot} " \
|
||||
"rootfstype=${mmcrootfstype}\0" \
|
||||
"nandargs=setenv bootargs console=${console} " \
|
||||
"mpurate=${mpurate} " \
|
||||
"vram=${vram} " \
|
||||
"omapfb.mode=dvi:${dvimode} " \
|
||||
"omapdss.def_disp=${defaultdisplay} " \
|
||||
"root=${nandroot} " \
|
||||
"rootfstype=${nandrootfstype}\0" \
|
||||
"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
|
||||
"bootscript=echo Running bootscript from mmc ...; " \
|
||||
"source ${loadaddr}\0" \
|
||||
"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
|
||||
"mmcboot=echo Booting from mmc ...; " \
|
||||
"run mmcargs; " \
|
||||
"bootm ${loadaddr}\0" \
|
||||
"nandboot=echo Booting from nand ...; " \
|
||||
"run nandargs; " \
|
||||
"nand read ${loadaddr} 2a0000 400000; " \
|
||||
"bootm ${loadaddr}\0" \
|
||||
|
||||
#define CONFIG_BOOTCOMMAND \
|
||||
"mmc dev ${mmcdev}; if mmc rescan; then " \
|
||||
"if run loadbootscript; then " \
|
||||
"run bootscript; " \
|
||||
"else " \
|
||||
"if run loaduimage; then " \
|
||||
"run mmcboot; " \
|
||||
"else run nandboot; " \
|
||||
"fi; " \
|
||||
"fi; " \
|
||||
"else run nandboot; fi"
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CONFIG_TIMESTAMP
|
||||
#define CONFIG_SYS_AUTOLOAD "no"
|
||||
#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
|
||||
#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
|
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0 + 0x02000000)
|
||||
|
||||
/*
|
||||
* AM3517 has 12 GP timers, they can be driven by the system clock
|
||||
* (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
|
||||
* This rate is divided by a local divisor.
|
||||
*/
|
||||
#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
|
||||
#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
|
||||
#define CONFIG_SYS_HZ 1000
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Physical Memory Map
|
||||
*/
|
||||
#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
|
||||
#define CONFIG_SYS_CS0_SIZE (256 << 20)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH and environment organization
|
||||
*/
|
||||
|
||||
/* **** PISMO SUPPORT *** */
|
||||
/* Monitor at start of flash */
|
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
|
||||
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
|
||||
|
||||
#define CONFIG_ENV_OFFSET 0x260000
|
||||
#define CONFIG_ENV_ADDR 0x260000
|
||||
|
||||
#if defined(CONFIG_CMD_NET)
|
||||
#define CONFIG_DRIVER_TI_EMAC_USE_RMII
|
||||
#define CONFIG_ARP_TIMEOUT 200UL
|
||||
#define CONFIG_NET_RETRY_COUNT 5
|
||||
#endif /* CONFIG_CMD_NET */
|
||||
|
||||
/* additions for new relocation code, must be added to all boards */
|
||||
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x800
|
||||
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
|
||||
CONFIG_SYS_INIT_RAM_SIZE - \
|
||||
GENERATED_GBL_DATA_SIZE)
|
||||
|
||||
/* Status LED */
|
||||
#define GREEN_LED_GPIO 186 /* CM-T3517 Green LED is GPIO186 */
|
||||
|
||||
/* Display Configuration */
|
||||
#define LCD_BPP LCD_COLOR16
|
||||
|
||||
#define CONFIG_SPLASH_SCREEN
|
||||
#define CONFIG_SPLASHIMAGE_GUARD
|
||||
#define CONFIG_BMP_16BPP
|
||||
#define CONFIG_SCF0403_LCD
|
||||
|
||||
/* EEPROM */
|
||||
#define CONFIG_ENV_EEPROM_IS_ON_I2C
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
|
||||
#define CONFIG_SYS_EEPROM_SIZE 256
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
@ -218,7 +218,6 @@ CONFIG_CM_MULTIPLE_SSRAM
|
||||
CONFIG_CM_REMAP
|
||||
CONFIG_CM_SPD_DETECT
|
||||
CONFIG_CM_T335
|
||||
CONFIG_CM_T3517
|
||||
CONFIG_CM_T3X
|
||||
CONFIG_CM_T43
|
||||
CONFIG_CM_T54
|
||||
|
||||
Loading…
Reference in New Issue
Block a user