arm64: a37xx: dts: Fix the number of GPIO on south bridge
The number of pins in South Bridge is 30 and not 29. There is a fix for the driver for the pinctrl, but a fix is also need at device tree level for the GPIO. Reviewed-on: http://vgitil04.il.marvell.com:8080/43286 Reviewed-by: Hua Jing <jinghua@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Signed-off-by: Ken Ma <make@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
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@ -168,7 +168,7 @@
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reg = <0x18800 0x100>, <0x18C00 0x20>;
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gpiosb: gpiosb {
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#gpio-cells = <2>;
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gpio-ranges = <&pinctrl_sb 0 0 29>;
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gpio-ranges = <&pinctrl_sb 0 0 30>;
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gpio-controller;
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interrupts =
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<GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
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