cmd: ti: Generalize cmd_ddr3 command
Keystone and DRA7 based TI platforms uses same EMIF memory controller. cmd_ddr3 command is customized for keystone platforms, make it generic so that it can be re used for DRA7 platforms. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
This commit is contained in:
Lokesh Vutla
Tom Rini
parent
5cd9661dc6
commit
8a8af8a2fd
@ -17,7 +17,9 @@
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#include <asm/io.h>
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/* Base address */
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#ifndef EMIF1_BASE
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#define EMIF1_BASE 0x4c000000
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#endif
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#define EMIF2_BASE 0x4d000000
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#define EMIF_4D 0x4
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@ -78,6 +78,7 @@ typedef volatile unsigned int *dv_reg_p;
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#define KS2_DDR3A_EMIF_CTRL_BASE 0x21010000
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#define KS2_DDR3A_EMIF_DATA_BASE 0x80000000
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#define KS2_DDR3A_DDRPHYC 0x02329000
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#define EMIF1_BASE KS2_DDR3A_EMIF_CTRL_BASE
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#define KS2_DDR3_MIDR_OFFSET 0x00
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#define KS2_DDR3_STATUS_OFFSET 0x04
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150
cmd/ti/ddr3.c
150
cmd/ti/ddr3.c
@ -7,12 +7,15 @@
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*/
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#include <asm/arch/hardware.h>
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#include <asm/arch/ddr3.h>
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#include <asm/cache.h>
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#include <asm/emif.h>
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#include <common.h>
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#include <command.h>
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DECLARE_GLOBAL_DATA_PTR;
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#ifdef CONFIG_ARCH_KEYSTONE
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#include <asm/arch/ddr3.h>
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#define DDR_MIN_ADDR CONFIG_SYS_SDRAM_BASE
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#define STACKSIZE (512 << 10) /* 512 KiB */
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@ -21,6 +24,7 @@ DECLARE_GLOBAL_DATA_PTR;
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#define ECC_END_ADDR1 (((gd->start_addr_sp - DDR_REMAP_ADDR - \
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STACKSIZE) >> 17) - 2)
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#endif
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#define DDR_TEST_BURST_SIZE 1024
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@ -153,57 +157,143 @@ static int ddr_memory_compare(u32 address1, u32 address2, u32 size)
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return 0;
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}
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static int ddr_memory_ecc_err(u32 base, u32 address, u32 ecc_err)
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static void ddr_check_ecc_status(void)
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{
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u32 value1, value2, value3;
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struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE;
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u32 err_1b = readl(&emif->emif_1b_ecc_err_cnt);
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u32 int_status = readl(&emif->emif_irqstatus_raw_sys);
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int ecc_test = 0;
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char *env;
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puts("Disabling DDR ECC ...\n");
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ddr3_disable_ecc(base);
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env = env_get("ecc_test");
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if (env)
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ecc_test = simple_strtol(env, NULL, 0);
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value1 = __raw_readl(address);
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value2 = value1 ^ ecc_err;
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__raw_writel(value2, address);
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puts("ECC test Status:\n");
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if (int_status & EMIF_INT_WR_ECC_ERR_SYS_MASK)
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puts("\tECC test: DDR ECC write error interrupted\n");
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value3 = __raw_readl(address);
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printf("ECC err test, addr 0x%x, read data 0x%x, wrote data 0x%x, err pattern: 0x%x, read after write data 0x%x\n",
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address, value1, value2, ecc_err, value3);
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if (int_status & EMIF_INT_TWOBIT_ECC_ERR_SYS_MASK)
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if (!ecc_test)
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panic("\tECC test: DDR ECC 2-bit error interrupted");
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__raw_writel(ECC_START_ADDR1 | (ECC_END_ADDR1 << 16),
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base + KS2_DDR3_ECC_ADDR_RANGE1_OFFSET);
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if (int_status & EMIF_INT_ONEBIT_ECC_ERR_SYS_MASK)
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puts("\tECC test: DDR ECC 1-bit error interrupted\n");
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puts("Enabling DDR ECC ...\n");
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ddr3_enable_ecc(base, 1);
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if (err_1b)
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printf("\tECC test: 1-bit ECC err count: 0x%x\n", err_1b);
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}
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value1 = __raw_readl(address);
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printf("ECC err test, addr 0x%x, read data 0x%x\n", address, value1);
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static int ddr_memory_ecc_err(u32 addr, u32 ecc_err)
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{
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struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE;
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u32 ecc_ctrl = readl(&emif->emif_ecc_ctrl_reg);
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u32 val1, val2, val3;
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debug("Disabling D-Cache before ECC test\n");
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dcache_disable();
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invalidate_dcache_all();
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puts("Testing DDR ECC:\n");
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puts("\tECC test: Disabling DDR ECC ...\n");
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writel(0, &emif->emif_ecc_ctrl_reg);
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val1 = readl(addr);
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val2 = val1 ^ ecc_err;
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writel(val2, addr);
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val3 = readl(addr);
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printf("\tECC test: addr 0x%x, read data 0x%x, written data 0x%x, err pattern: 0x%x, read after write data 0x%x\n",
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addr, val1, val2, ecc_err, val3);
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puts("\tECC test: Enabling DDR ECC ...\n");
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#ifdef CONFIG_ARCH_KEYSTONE
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ecc_ctrl = ECC_START_ADDR1 | (ECC_END_ADDR1 << 16);
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writel(ecc_ctrl, EMIF1_BASE + KS2_DDR3_ECC_ADDR_RANGE1_OFFSET);
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ddr3_enable_ecc(EMIF1_BASE, 1);
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#else
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writel(ecc_ctrl, &emif->emif_ecc_ctrl_reg);
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#endif
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val1 = readl(addr);
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printf("\tECC test: addr 0x%x, read data 0x%x\n", addr, val1);
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ddr_check_ecc_status();
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debug("Enabling D-cache back after ECC test\n");
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enable_caches();
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ddr3_check_ecc_int(base);
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return 0;
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}
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static int is_addr_valid(u32 addr)
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{
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struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE;
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u32 start_addr, end_addr, range, ecc_ctrl;
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#ifdef CONFIG_ARCH_KEYSTONE
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ecc_ctrl = EMIF_ECC_REG_ECC_ADDR_RGN_1_EN_MASK;
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range = ECC_START_ADDR1 | (ECC_END_ADDR1 << 16);
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#else
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ecc_ctrl = readl(&emif->emif_ecc_ctrl_reg);
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range = readl(&emif->emif_ecc_address_range_1);
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#endif
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/* Check in ecc address range 1 */
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if (ecc_ctrl & EMIF_ECC_REG_ECC_ADDR_RGN_1_EN_MASK) {
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start_addr = ((range & EMIF_ECC_REG_ECC_START_ADDR_MASK) << 16)
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+ CONFIG_SYS_SDRAM_BASE;
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end_addr = start_addr + (range & EMIF_ECC_REG_ECC_END_ADDR_MASK)
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+ 0xFFFF;
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if ((addr >= start_addr) && (addr <= end_addr))
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/* addr within ecc address range 1 */
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return 1;
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}
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/* Check in ecc address range 2 */
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if (ecc_ctrl & EMIF_ECC_REG_ECC_ADDR_RGN_2_EN_MASK) {
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range = readl(&emif->emif_ecc_address_range_2);
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start_addr = ((range & EMIF_ECC_REG_ECC_START_ADDR_MASK) << 16)
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+ CONFIG_SYS_SDRAM_BASE;
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end_addr = start_addr + (range & EMIF_ECC_REG_ECC_END_ADDR_MASK)
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+ 0xFFFF;
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if ((addr >= start_addr) && (addr <= end_addr))
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/* addr within ecc address range 2 */
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return 1;
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}
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return 0;
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}
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static int is_ecc_enabled(void)
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{
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struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE;
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u32 ecc_ctrl = readl(&emif->emif_ecc_ctrl_reg);
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return (ecc_ctrl & EMIF_ECC_CTRL_REG_ECC_EN_MASK) &&
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(ecc_ctrl & EMIF_ECC_REG_RMW_EN_MASK);
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}
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static int do_ddr_test(cmd_tbl_t *cmdtp,
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int flag, int argc, char * const argv[])
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{
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u32 start_addr, end_addr, size, ecc_err;
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if ((argc == 4) && (strncmp(argv[1], "ecc_err", 8) == 0)) {
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if (!ddr3_ecc_support_rmw(KS2_DDR3A_EMIF_CTRL_BASE)) {
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puts("ECC RMW isn't supported for this SOC\n");
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return 1;
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if (!is_ecc_enabled()) {
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puts("ECC not enabled. Please Enable ECC any try again\n");
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return CMD_RET_FAILURE;
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}
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start_addr = simple_strtoul(argv[2], NULL, 16);
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ecc_err = simple_strtoul(argv[3], NULL, 16);
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if ((start_addr < CONFIG_SYS_SDRAM_BASE) ||
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(start_addr > (CONFIG_SYS_SDRAM_BASE +
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CONFIG_MAX_RAM_BANK_SIZE - 1))) {
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puts("Invalid address!\n");
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return cmd_usage(cmdtp);
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if (!is_addr_valid(start_addr)) {
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puts("Invalid address. Please enter ECC supported address!\n");
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return CMD_RET_FAILURE;
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}
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ddr_memory_ecc_err(KS2_DDR3A_EMIF_CTRL_BASE,
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start_addr, ecc_err);
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ddr_memory_ecc_err(start_addr, ecc_err);
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return 0;
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}
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@ -216,10 +306,10 @@ static int do_ddr_test(cmd_tbl_t *cmdtp,
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if ((start_addr < CONFIG_SYS_SDRAM_BASE) ||
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(start_addr > (CONFIG_SYS_SDRAM_BASE +
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CONFIG_MAX_RAM_BANK_SIZE - 1)) ||
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get_effective_memsize() - 1)) ||
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(end_addr < CONFIG_SYS_SDRAM_BASE) ||
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(end_addr > (CONFIG_SYS_SDRAM_BASE +
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CONFIG_MAX_RAM_BANK_SIZE - 1)) || (start_addr >= end_addr)) {
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get_effective_memsize() - 1)) || (start_addr >= end_addr)) {
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puts("Invalid start or end address!\n");
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return cmd_usage(cmdtp);
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}
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