Add initial support for the ALPR board from Prodrive
NAND needs some additional testing Patch by Heiko Schocher, 15 Aug 2006
This commit is contained in:
Stefan Roese
parent
f0ff4692ff
commit
899620c2d6
@ -2,6 +2,10 @@
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Changes since U-Boot 1.1.4:
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======================================================================
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* Add initial support for the ALPR board from Prodrive
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NAND needs some additional testing
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Patch by Heiko Schocher, 15 Aug 2006
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* Add FPGA Altera Cyclone 2 support
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Patch by Heiko Schocher, 15 Aug 2006
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3
Makefile
3
Makefile
@ -818,6 +818,9 @@ xtract_4xx = $(subst _25,,$(subst _33,,$(subst _BA,,$(subst _ME,,$(subst _HI,,$(
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ADCIOP_config: unconfig
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@./mkconfig $(@:_config=) ppc ppc4xx adciop esd
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alpr_config: unconfig
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@./mkconfig $(@:_config=) ppc ppc4xx alpr prodrive
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AP1000_config:unconfig
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@./mkconfig $(@:_config=) ppc ppc4xx ap1000 amirix
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47
board/prodrive/alpr/Makefile
Normal file
47
board/prodrive/alpr/Makefile
Normal file
@ -0,0 +1,47 @@
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#
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# (C) Copyright 2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk
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LIB = lib$(BOARD).a
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OBJS = $(BOARD).o fpga.o nand.o
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SOBJS = init.o
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$(LIB): $(OBJS) $(SOBJS)
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$(AR) crv $@ $(OBJS)
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clean:
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rm -f $(SOBJS) $(OBJS)
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distclean: clean
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rm -f $(LIB) core *.bak .depend *~
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#########################################################################
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.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
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$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
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sinclude .depend
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#########################################################################
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283
board/prodrive/alpr/alpr.c
Normal file
283
board/prodrive/alpr/alpr.c
Normal file
@ -0,0 +1,283 @@
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/*
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* (C) Copyright 2006
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/processor.h>
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#include <spd_sdram.h>
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#include <ppc4xx_enet.h>
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DECLARE_GLOBAL_DATA_PTR;
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extern int alpr_fpga_init(void);
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int board_early_init_f (void)
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{
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unsigned long mfr;
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/*-------------------------------------------------------------------------+
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| Initialize EBC CONFIG
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+-------------------------------------------------------------------------*/
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mtebc(xbcfg, EBC_CFG_LE_UNLOCK |
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EBC_CFG_PTD_ENABLE | EBC_CFG_RTC_64PERCLK |
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EBC_CFG_ATC_PREVIOUS | EBC_CFG_DTC_PREVIOUS |
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EBC_CFG_CTC_PREVIOUS | EBC_CFG_EMC_NONDEFAULT |
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EBC_CFG_PME_DISABLE | EBC_CFG_PR_32);
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/*--------------------------------------------------------------------
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* Setup the interrupt controller polarities, triggers, etc.
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*-------------------------------------------------------------------*/
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mtdcr (uic0sr, 0xffffffff); /* clear all */
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mtdcr (uic0er, 0x00000000); /* disable all */
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mtdcr (uic0cr, 0x00000009); /* SMI & UIC1 crit are critical */
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mtdcr (uic0pr, 0xfffffe13); /* per ref-board manual */
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mtdcr (uic0tr, 0x01c00008); /* per ref-board manual */
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mtdcr (uic0vr, 0x00000001); /* int31 highest, base=0x000 */
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mtdcr (uic0sr, 0xffffffff); /* clear all */
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mtdcr (uic1sr, 0xffffffff); /* clear all */
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mtdcr (uic1er, 0x00000000); /* disable all */
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mtdcr (uic1cr, 0x00000000); /* all non-critical */
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mtdcr (uic1pr, 0xffffe0ff); /* per ref-board manual */
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mtdcr (uic1tr, 0x00ffc000); /* per ref-board manual */
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mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */
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mtdcr (uic1sr, 0xffffffff); /* clear all */
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mtdcr (uic2sr, 0xffffffff); /* clear all */
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mtdcr (uic2er, 0x00000000); /* disable all */
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mtdcr (uic2cr, 0x00000000); /* all non-critical */
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mtdcr (uic2pr, 0xffffffff); /* per ref-board manual */
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mtdcr (uic2tr, 0x00ff8c0f); /* per ref-board manual */
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mtdcr (uic2vr, 0x00000001); /* int31 highest, base=0x000 */
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mtdcr (uic2sr, 0xffffffff); /* clear all */
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mtdcr (uicb0sr, 0xfc000000); /* clear all */
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mtdcr (uicb0er, 0x00000000); /* disable all */
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mtdcr (uicb0cr, 0x00000000); /* all non-critical */
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mtdcr (uicb0pr, 0xfc000000); /* */
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mtdcr (uicb0tr, 0x00000000); /* */
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mtdcr (uicb0vr, 0x00000001); /* */
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mfsdr (sdr_mfr, mfr);
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mfr &= ~SDR0_MFR_ECS_MASK;
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return 0;
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}
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int checkboard (void)
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{
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char *s = getenv ("serial#");
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printf ("Board: ALPR");
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if (s != NULL) {
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puts (", serial# ");
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puts (s);
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}
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putc ('\n');
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return (0);
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}
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#if defined(CFG_DRAM_TEST)
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int testdram (void)
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{
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uint *pstart = (uint *) 0x00000000;
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uint *pend = (uint *) 0x08000000;
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uint *p;
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for (p = pstart; p < pend; p++)
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*p = 0xaaaaaaaa;
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for (p = pstart; p < pend; p++) {
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if (*p != 0xaaaaaaaa) {
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printf ("SDRAM test fails at: %08x\n", (uint) p);
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return 1;
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}
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}
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for (p = pstart; p < pend; p++)
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*p = 0x55555555;
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for (p = pstart; p < pend; p++) {
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if (*p != 0x55555555) {
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printf ("SDRAM test fails at: %08x\n", (uint) p);
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return 1;
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}
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}
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return 0;
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}
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#endif
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/*************************************************************************
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* pci_pre_init
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*
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* This routine is called just prior to registering the hose and gives
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* the board the opportunity to check things. Returning a value of zero
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* indicates that things are bad & PCI initialization should be aborted.
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*
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* Different boards may wish to customize the pci controller structure
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* (add regions, override default access routines, etc) or perform
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* certain pre-initialization actions.
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*
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************************************************************************/
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#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
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int pci_pre_init(struct pci_controller * hose )
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{
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unsigned long strap;
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/*--------------------------------------------------------------------------+
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* The ocotea board is always configured as the host & requires the
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* PCI arbiter to be enabled.
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*--------------------------------------------------------------------------*/
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mfsdr(sdr_sdstp1, strap);
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if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ){
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printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap);
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return 0;
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}
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/* FPGA Init */
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alpr_fpga_init ();
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return 1;
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}
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#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
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/*************************************************************************
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* pci_target_init
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*
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* The bootstrap configuration provides default settings for the pci
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* inbound map (PIM). But the bootstrap config choices are limited and
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* may not be sufficient for a given board.
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*
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************************************************************************/
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#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
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void pci_target_init(struct pci_controller * hose )
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{
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/*--------------------------------------------------------------------------+
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* Disable everything
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*--------------------------------------------------------------------------*/
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out32r( PCIX0_PIM0SA, 0 ); /* disable */
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out32r( PCIX0_PIM1SA, 0 ); /* disable */
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out32r( PCIX0_PIM2SA, 0 ); /* disable */
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out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
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/*--------------------------------------------------------------------------+
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* Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
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* options to not support sizes such as 128/256 MB.
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*--------------------------------------------------------------------------*/
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out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE );
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out32r( PCIX0_PIM0LAH, 0 );
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out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
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out32r( PCIX0_BAR0, 0 );
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/*--------------------------------------------------------------------------+
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* Program the board's subsystem id/vendor id
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*--------------------------------------------------------------------------*/
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out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
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out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID );
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out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
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}
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#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
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/*************************************************************************
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* is_pci_host
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*
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* This routine is called to determine if a pci scan should be
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* performed. With various hardware environments (especially cPCI and
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* PPMC) it's insufficient to depend on the state of the arbiter enable
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* bit in the strap register, or generic host/adapter assumptions.
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*
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* Rather than hard-code a bad assumption in the general 440 code, the
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* 440 pci code requires the board to decide at runtime.
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*
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* Return 0 for adapter mode, non-zero for host (monarch) mode.
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*
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*
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************************************************************************/
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#if defined(CONFIG_PCI)
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int is_pci_host(struct pci_controller *hose)
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{
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/* The ocotea board is always configured as host. */
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return(1);
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}
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#endif /* defined(CONFIG_PCI) */
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/*************************************************************************
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* pci_master_init
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*
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************************************************************************/
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#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
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void pci_master_init(struct pci_controller *hose)
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{
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unsigned short temp_short;
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#if 0
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/*--------------------------------------------------------------------------+
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| Write the PowerPC440 PCI Configuration regs.
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| Enable PowerPC440 to be a master on the PCI bus (PMM).
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| Enable PowerPC440 to act as a PCI memory target (PTM).
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+--------------------------------------------------------------------------*/
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pci_read_config_word(0, PCI_COMMAND, &temp_short);
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pci_write_config_word(0, PCI_COMMAND,
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temp_short | PCI_COMMAND_MASTER |
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PCI_COMMAND_MEMORY);
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#endif
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#if 1
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/*--------------------------------------------------------------------------+
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| PowerPC440 PCI Master configuration.
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| Map PLB/processor addresses to PCI memory space.
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| PLB address 0xA0000000-0xCFFFFFFF ==> PCI address 0x80000000-0xCFFFFFFF
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| Use byte reversed out routines to handle endianess.
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| Make this region non-prefetchable.
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+--------------------------------------------------------------------------*/
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out32r( PCIX0_POM0SA, 0 ); /* disable */
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out32r( PCIX0_POM1SA, 0 ); /* disable */
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out32r( PCIX0_POM2SA, 0 ); /* disable */
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out32r(PCIX0_POM0LAL, CFG_PCI_MEMBASE); /* PMM0 Local Address */
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out32r(PCIX0_POM0LAH, 0x00000003); /* PMM0 Local Address */
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out32r(PCIX0_POM0PCIAL, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */
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out32r(PCIX0_POM0PCIAH, 0x00000000); /* PMM0 PCI High Address */
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out32r(PCIX0_POM0SA, ~(0x10000000 - 1) | 1); /* 256MB + enable region */
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out32r(PCIX0_POM1LAL, CFG_PCI_MEMBASE2); /* PMM0 Local Address */
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out32r(PCIX0_POM1LAH, 0x00000003); /* PMM0 Local Address */
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out32r(PCIX0_POM1PCIAL, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */
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out32r(PCIX0_POM1PCIAH, 0x00000000); /* PMM0 PCI High Address */
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out32r(PCIX0_POM1SA, ~(0x10000000 - 1) | 1); /* 256MB + enable region */
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#endif
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}
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#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
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#ifdef CONFIG_POST
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/*
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* Returns 1 if keys pressed to start the power-on long-running tests
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* Called from board_init_f().
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*/
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int post_hotkeys_pressed(void)
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{
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return (ctrlc());
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}
|
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#endif
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44
board/prodrive/alpr/config.mk
Normal file
44
board/prodrive/alpr/config.mk
Normal file
@ -0,0 +1,44 @@
|
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#
|
||||
# (C) Copyright 2004
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
#
|
||||
# AMCC 440GX Reference Platform (Ocotea) board
|
||||
#
|
||||
|
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#TEXT_BASE = 0xFFFE0000
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|
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ifeq ($(ramsym),1)
|
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TEXT_BASE = 0x07FD0000
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||||
else
|
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TEXT_BASE = 0xFFFC0000
|
||||
endif
|
||||
|
||||
PLATFORM_CPPFLAGS += -DCONFIG_440=1
|
||||
|
||||
ifeq ($(debug),1)
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||||
PLATFORM_CPPFLAGS += -DDEBUG
|
||||
endif
|
||||
|
||||
ifeq ($(dbcr),1)
|
||||
PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
|
||||
endif
|
||||
264
board/prodrive/alpr/fpga.c
Normal file
264
board/prodrive/alpr/fpga.c
Normal file
@ -0,0 +1,264 @@
|
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/*
|
||||
* (C) Copyright 2006
|
||||
* Heiko Schocher, DENX Software Engineering, hs@denx.de
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*
|
||||
*/
|
||||
|
||||
/*
|
||||
* Altera FPGA configuration support for the ALPR computer from prodrive
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <altera.h>
|
||||
#include <ACEX1K.h>
|
||||
#include <command.h>
|
||||
#include <asm-ppc/processor.h>
|
||||
#include <ppc440.h>
|
||||
#include "fpga.h"
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#if (CONFIG_FPGA)
|
||||
|
||||
#ifdef FPGA_DEBUG
|
||||
#define PRINTF(fmt,args...) printf (fmt ,##args)
|
||||
#else
|
||||
#define PRINTF(fmt,args...)
|
||||
#endif
|
||||
|
||||
static unsigned long regval;
|
||||
|
||||
#define SET_GPIO_REG_0(reg, bit) {\
|
||||
regval = in32(reg);\
|
||||
regval &= ~(0x80000000 >> bit);\
|
||||
out32(reg, regval);\
|
||||
}
|
||||
|
||||
#define SET_GPIO_REG_1(reg, bit) {\
|
||||
regval = in32(reg);\
|
||||
regval |= (0x80000000 >> bit);\
|
||||
out32(reg, regval);\
|
||||
}
|
||||
|
||||
#define GPIO_CLK_PIN 0x00002000
|
||||
#define GPIO_CLK_PIN_I 0xffffdfff
|
||||
#define GPIO_DAT_PIN 0x00001000
|
||||
#define GPIO_DAT_PIN_I 0xffffefff
|
||||
#define GPIO_CLKDAT_PIN_I 0xffffcfff
|
||||
|
||||
#define SET_GPIO_CLK_0 out32(GPIO0_OR, in32(GPIO0_OR) & GPIO_CLK_PIN_I);
|
||||
#define SET_GPIO_CLK_1 out32(GPIO0_OR, in32(GPIO0_OR) | GPIO_CLK_PIN);
|
||||
#define SET_GPIO_DAT_0 out32(GPIO0_OR, in32(GPIO0_OR) & GPIO_DAT_PIN_I);
|
||||
#define SET_GPIO_DAT_1 out32(GPIO0_OR, in32(GPIO0_OR) | GPIO_DAT_PIN);
|
||||
|
||||
#define SET_GPIO_0(bit) SET_GPIO_REG_0(GPIO0_OR, bit)
|
||||
#define SET_GPIO_1(bit) SET_GPIO_REG_1(GPIO0_OR, bit)
|
||||
|
||||
#define SET_GPIO_CLK_0_Z1 out32(GPIO0_OR, (in32(GPIO0_OR) & GPIO_CLK_PIN_I) | GPIO_DAT_PIN);
|
||||
#define SET_GPIO_CLK_0_Z0 out32(GPIO0_OR, in32(GPIO0_OR) & GPIO_CLKDAT_PIN_I);
|
||||
|
||||
#define FPGA_WRITE_1 { \
|
||||
SET_GPIO_CLK_0_Z1\
|
||||
SET_GPIO_CLK_1}
|
||||
|
||||
#define FPGA_WRITE_0 { \
|
||||
SET_GPIO_CLK_0_Z0\
|
||||
SET_GPIO_CLK_1}
|
||||
|
||||
#define P_GP(reg) (reg & 0x00023f00)
|
||||
|
||||
/* Plattforminitializations */
|
||||
/* Here we have to set the FPGA Chain */
|
||||
/* PROGRAM_PROG_EN = HIGH */
|
||||
/* PROGRAM_SEL_DPR = LOW */
|
||||
int fpga_pre_fn (int cookie)
|
||||
{
|
||||
unsigned long reg;
|
||||
|
||||
reg = in32(GPIO0_IR);
|
||||
/* Enable the FPGA Chain */
|
||||
SET_GPIO_REG_1(GPIO0_TCR, CFG_GPIO_PROG_EN);
|
||||
SET_GPIO_REG_0(GPIO0_ODR, CFG_GPIO_PROG_EN);
|
||||
SET_GPIO_1(CFG_GPIO_PROG_EN);
|
||||
SET_GPIO_REG_1(GPIO0_TCR, CFG_GPIO_SEL_DPR);
|
||||
SET_GPIO_REG_0(GPIO0_ODR, CFG_GPIO_SEL_DPR);
|
||||
SET_GPIO_0((CFG_GPIO_SEL_DPR));
|
||||
|
||||
/* initialize the GPIO Pins */
|
||||
/* output */
|
||||
SET_GPIO_0(CFG_GPIO_CLK);
|
||||
SET_GPIO_REG_1(GPIO0_TCR, CFG_GPIO_CLK);
|
||||
SET_GPIO_REG_0(GPIO0_ODR, CFG_GPIO_CLK);
|
||||
|
||||
/* output */
|
||||
SET_GPIO_0(CFG_GPIO_DATA);
|
||||
SET_GPIO_REG_1(GPIO0_TCR, CFG_GPIO_DATA);
|
||||
SET_GPIO_REG_0(GPIO0_ODR, CFG_GPIO_DATA);
|
||||
|
||||
/* First we set STATUS to 0 then as an input */
|
||||
SET_GPIO_REG_1(GPIO0_TCR, CFG_GPIO_STATUS);
|
||||
SET_GPIO_REG_0(GPIO0_ODR, CFG_GPIO_STATUS);
|
||||
SET_GPIO_0(CFG_GPIO_STATUS);
|
||||
SET_GPIO_REG_0(GPIO0_TCR, CFG_GPIO_STATUS);
|
||||
SET_GPIO_REG_0(GPIO0_ODR, CFG_GPIO_STATUS);
|
||||
|
||||
/* output */
|
||||
SET_GPIO_REG_1(GPIO0_TCR, CFG_GPIO_CONFIG);
|
||||
SET_GPIO_REG_0(GPIO0_ODR, CFG_GPIO_CONFIG);
|
||||
SET_GPIO_0(CFG_GPIO_CONFIG);
|
||||
|
||||
/* input */
|
||||
SET_GPIO_0(CFG_GPIO_CON_DON);
|
||||
SET_GPIO_REG_0(GPIO0_TCR, CFG_GPIO_CON_DON);
|
||||
SET_GPIO_REG_0(GPIO0_ODR, CFG_GPIO_CON_DON);
|
||||
|
||||
/* CONFIG = 0 STATUS = 0 -> FPGA in reset state */
|
||||
SET_GPIO_0(CFG_GPIO_CONFIG);
|
||||
return FPGA_SUCCESS;
|
||||
}
|
||||
|
||||
/* Set the state of CONFIG Pin */
|
||||
int fpga_config_fn (int assert_config, int flush, int cookie)
|
||||
{
|
||||
if (assert_config) {
|
||||
SET_GPIO_1(CFG_GPIO_CONFIG);
|
||||
} else {
|
||||
SET_GPIO_0(CFG_GPIO_CONFIG);
|
||||
}
|
||||
return FPGA_SUCCESS;
|
||||
}
|
||||
|
||||
/* Returns the state of STATUS Pin */
|
||||
int fpga_status_fn (int cookie)
|
||||
{
|
||||
unsigned long reg;
|
||||
|
||||
reg = in32(GPIO0_IR);
|
||||
if (reg &= (0x80000000 >> CFG_GPIO_STATUS)) {
|
||||
PRINTF("STATUS = HIGH\n");
|
||||
return FPGA_FAIL;
|
||||
}
|
||||
PRINTF("STATUS = LOW\n");
|
||||
return FPGA_SUCCESS;
|
||||
}
|
||||
|
||||
/* Returns the state of CONF_DONE Pin */
|
||||
int fpga_done_fn (int cookie)
|
||||
{
|
||||
unsigned long reg;
|
||||
reg = in32(GPIO0_IR);
|
||||
if (reg &= (0x80000000 >> CFG_GPIO_CON_DON)) {
|
||||
PRINTF("CONF_DON = HIGH\n");
|
||||
return FPGA_FAIL;
|
||||
}
|
||||
PRINTF("CONF_DON = LOW\n");
|
||||
return FPGA_SUCCESS;
|
||||
}
|
||||
|
||||
/* writes the complete buffer to the FPGA
|
||||
writing the complete buffer in one function is very faster,
|
||||
then calling it for every bit */
|
||||
int fpga_write_fn (void *buf, size_t len, int flush, int cookie)
|
||||
{
|
||||
size_t bytecount = 0;
|
||||
unsigned char *data = (unsigned char *) buf;
|
||||
unsigned char val=0;
|
||||
int i;
|
||||
|
||||
while (bytecount < len) {
|
||||
#ifdef CFG_FPGA_CHECK_CTRLC
|
||||
if (ctrlc ()) {
|
||||
return FPGA_FAIL;
|
||||
}
|
||||
#endif
|
||||
val = data[bytecount ++ ];
|
||||
i = 8;
|
||||
do {
|
||||
if (val & 0x01) {
|
||||
FPGA_WRITE_1;
|
||||
} else {
|
||||
FPGA_WRITE_0;
|
||||
}
|
||||
val >>= 1;
|
||||
i --;
|
||||
} while (i > 0);
|
||||
|
||||
#ifdef CFG_FPGA_PROG_FEEDBACK
|
||||
if (bytecount % (len / 40) == 0)
|
||||
putc ('.'); /* let them know we are alive */
|
||||
#endif
|
||||
}
|
||||
return FPGA_SUCCESS;
|
||||
}
|
||||
|
||||
/* called, when programming is aborted */
|
||||
int fpga_abort_fn (int cookie)
|
||||
{
|
||||
SET_GPIO_1((CFG_GPIO_SEL_DPR));
|
||||
return FPGA_SUCCESS;
|
||||
}
|
||||
|
||||
/* called, when programming was succesful */
|
||||
int fpga_post_fn (int cookie)
|
||||
{
|
||||
return fpga_abort_fn (cookie);
|
||||
}
|
||||
|
||||
/* Note that these are pointers to code that is in Flash. They will be
|
||||
* relocated at runtime.
|
||||
*/
|
||||
Altera_CYC2_Passive_Serial_fns fpga_fns = {
|
||||
fpga_pre_fn,
|
||||
fpga_config_fn,
|
||||
fpga_status_fn,
|
||||
fpga_done_fn,
|
||||
fpga_write_fn,
|
||||
fpga_abort_fn,
|
||||
fpga_post_fn
|
||||
};
|
||||
|
||||
Altera_desc fpga[CONFIG_FPGA_COUNT] = {
|
||||
{Altera_CYC2,
|
||||
passive_serial,
|
||||
Altera_EP2C35_SIZE,
|
||||
(void *) &fpga_fns,
|
||||
NULL,
|
||||
0}
|
||||
};
|
||||
|
||||
/*
|
||||
* Initialize the fpga. Return 1 on success, 0 on failure.
|
||||
*/
|
||||
int alpr_fpga_init (void)
|
||||
{
|
||||
int i;
|
||||
|
||||
PRINTF ("%s:%d: Initialize FPGA interface (relocation offset = 0x%.8lx)\n", __FUNCTION__, __LINE__, gd->reloc_off);
|
||||
fpga_init (gd->reloc_off);
|
||||
|
||||
for (i = 0; i < CONFIG_FPGA_COUNT; i++) {
|
||||
PRINTF ("%s:%d: Adding fpga %d\n", __FUNCTION__, __LINE__, i);
|
||||
fpga_add (fpga_altera, &fpga[i]);
|
||||
}
|
||||
return 1;
|
||||
}
|
||||
|
||||
#endif
|
||||
109
board/prodrive/alpr/init.S
Normal file
109
board/prodrive/alpr/init.S
Normal file
@ -0,0 +1,109 @@
|
||||
/*
|
||||
* Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <ppc_asm.tmpl>
|
||||
#include <config.h>
|
||||
|
||||
/* General */
|
||||
#define TLB_VALID 0x00000200
|
||||
|
||||
/* Supported page sizes */
|
||||
|
||||
#define SZ_1K 0x00000000
|
||||
#define SZ_4K 0x00000010
|
||||
#define SZ_16K 0x00000020
|
||||
#define SZ_64K 0x00000030
|
||||
#define SZ_256K 0x00000040
|
||||
#define SZ_1M 0x00000050
|
||||
#define SZ_16M 0x00000070
|
||||
#define SZ_256M 0x00000090
|
||||
|
||||
/* Storage attributes */
|
||||
#define SA_W 0x00000800 /* Write-through */
|
||||
#define SA_I 0x00000400 /* Caching inhibited */
|
||||
#define SA_M 0x00000200 /* Memory coherence */
|
||||
#define SA_G 0x00000100 /* Guarded */
|
||||
#define SA_E 0x00000080 /* Endian */
|
||||
|
||||
/* Access control */
|
||||
#define AC_X 0x00000024 /* Execute */
|
||||
#define AC_W 0x00000012 /* Write */
|
||||
#define AC_R 0x00000009 /* Read */
|
||||
|
||||
/* Some handy macros */
|
||||
|
||||
#define EPN(e) ((e) & 0xfffffc00)
|
||||
#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) )
|
||||
#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) )
|
||||
#define TLB2(a) ( (a)&0x00000fbf )
|
||||
|
||||
#define tlbtab_start\
|
||||
mflr r1 ;\
|
||||
bl 0f ;
|
||||
|
||||
#define tlbtab_end\
|
||||
.long 0, 0, 0 ; \
|
||||
0: mflr r0 ; \
|
||||
mtlr r1 ; \
|
||||
blr ;
|
||||
|
||||
#define tlbentry(epn,sz,rpn,erpn,attr)\
|
||||
.long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
|
||||
|
||||
|
||||
/**************************************************************************
|
||||
* TLB TABLE
|
||||
*
|
||||
* This table is used by the cpu boot code to setup the initial tlb
|
||||
* entries. Rather than make broad assumptions in the cpu source tree,
|
||||
* this table lets each board set things up however they like.
|
||||
*
|
||||
* Pointer to the table is returned in r1
|
||||
*
|
||||
*************************************************************************/
|
||||
|
||||
.section .bootpg,"ax"
|
||||
.globl tlbtab
|
||||
|
||||
tlbtab:
|
||||
tlbtab_start
|
||||
tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
|
||||
tlbentry( CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I)
|
||||
tlbentry( CFG_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_R|AC_W|AC_X )
|
||||
tlbentry( CFG_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_R|AC_W|AC_X )
|
||||
tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
|
||||
tlbentry( CFG_SDRAM_BASE+0x10000000, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
|
||||
tlbentry( CFG_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I )
|
||||
|
||||
/* PCI */
|
||||
tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 3, AC_R|AC_W|SA_G|SA_I )
|
||||
#if 1
|
||||
tlbentry( CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 3, AC_R|AC_W|SA_G|SA_I )
|
||||
tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 3, AC_R|AC_W|SA_G|SA_I )
|
||||
#endif
|
||||
#if 0
|
||||
tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 3, AC_R|AC_W|SA_G|SA_I )
|
||||
#endif
|
||||
|
||||
/* NAND */
|
||||
tlbentry( CFG_NAND_BASE, SZ_16M, CFG_NAND_BASE, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
|
||||
tlbtab_end
|
||||
271
board/prodrive/alpr/nand.c
Normal file
271
board/prodrive/alpr/nand.c
Normal file
@ -0,0 +1,271 @@
|
||||
/*
|
||||
* (C) Copyright 2006
|
||||
* Heiko Schocher, DENX Software Engineering, hs@denx.de
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_NAND)
|
||||
|
||||
#include <nand.h>
|
||||
|
||||
#if 0
|
||||
#define HS_printf(fmt,arg...) \
|
||||
printf("HS %s %s: " fmt,__FILE__, __FUNCTION__, ##arg)
|
||||
#else
|
||||
#define HS_printf(fmt,arg...) \
|
||||
do { } while (0)
|
||||
#endif
|
||||
|
||||
#if 0
|
||||
#define CPLD_REG uchar
|
||||
#else
|
||||
#define CPLD_REG u16
|
||||
#endif
|
||||
|
||||
struct alpr_ndfc_regs {
|
||||
CPLD_REG cmd[4];
|
||||
CPLD_REG addr_wait;
|
||||
CPLD_REG term;
|
||||
CPLD_REG dummy;
|
||||
uchar dum2[2];
|
||||
CPLD_REG data;
|
||||
};
|
||||
|
||||
static u8 hwctl;
|
||||
static struct alpr_ndfc_regs *alpr_ndfc;
|
||||
static int alpr_chip = 0;
|
||||
|
||||
#if 1
|
||||
static int pdnb3_nand_dev_ready(struct mtd_info *mtd);
|
||||
|
||||
#if 1
|
||||
static u_char alpr_read (void *padr) {
|
||||
return (u_char )*((u16 *)(padr));
|
||||
}
|
||||
#else
|
||||
static u_char alpr_read (void *padr) {
|
||||
u16 hilf;
|
||||
u_char ret = 0;
|
||||
hilf = *((u16 *)(padr));
|
||||
ret = hilf;
|
||||
printf("%p hilf: %x ret: %x\n", padr, hilf, ret);
|
||||
return ret;
|
||||
}
|
||||
#endif
|
||||
|
||||
static void alpr_write (u_char byte, void *padr) {
|
||||
HS_printf("%p Byte: %x\n", padr, byte);
|
||||
*(volatile u16 *)padr = (u16)(byte);
|
||||
}
|
||||
|
||||
#elif 0
|
||||
#define alpr_read(a) (*(volatile u16 *) (a))
|
||||
#define alpr_write(a, b) ((*(volatile u16 *) (a)) = (b))
|
||||
#else
|
||||
#define alpr_read(a) readw(a)
|
||||
#define alpr_write(a, b) writew(a, b)
|
||||
#endif
|
||||
/*
|
||||
* The ALPR has a NAND Flash Controller (NDFC) that handles all accesses to
|
||||
* the NAND devices. The NDFC has command, address and data registers that
|
||||
* when accessed will set up the NAND flash pins appropriately. We'll use the
|
||||
* hwcontrol function to save the configuration in a global variable.
|
||||
* We can then use this information in the read and write functions to
|
||||
* determine which NDFC register to access.
|
||||
*
|
||||
* There are 2 NAND devices on the board, a Hynix HY27US08561A (32 MByte).
|
||||
*/
|
||||
static void pdnb3_nand_hwcontrol(struct mtd_info *mtd, int cmd)
|
||||
{
|
||||
HS_printf("cmd: %x\n", cmd);
|
||||
switch (cmd) {
|
||||
case NAND_CTL_SETCLE:
|
||||
hwctl |= 0x1;
|
||||
break;
|
||||
case NAND_CTL_CLRCLE:
|
||||
hwctl &= ~0x1;
|
||||
break;
|
||||
case NAND_CTL_SETALE:
|
||||
hwctl |= 0x2;
|
||||
break;
|
||||
case NAND_CTL_CLRALE:
|
||||
hwctl &= ~0x2;
|
||||
break;
|
||||
case NAND_CTL_SETNCE:
|
||||
break;
|
||||
case NAND_CTL_CLRNCE:
|
||||
alpr_write(0x00, &(alpr_ndfc->term));
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
static void pdnb3_nand_write_byte(struct mtd_info *mtd, u_char byte)
|
||||
{
|
||||
HS_printf("hwctl: %x %x %x %x\n", hwctl, byte, &(alpr_ndfc->cmd[alpr_chip]), &(alpr_ndfc->addr_wait));
|
||||
if (hwctl & 0x1)
|
||||
alpr_write(byte, &(alpr_ndfc->cmd[alpr_chip]));
|
||||
else if (hwctl & 0x2) {
|
||||
alpr_write(byte, &(alpr_ndfc->addr_wait));
|
||||
} else
|
||||
alpr_write(byte, &(alpr_ndfc->data));
|
||||
}
|
||||
|
||||
static u_char pdnb3_nand_read_byte(struct mtd_info *mtd)
|
||||
{
|
||||
return alpr_read(&(alpr_ndfc->data));
|
||||
}
|
||||
|
||||
static void pdnb3_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
|
||||
{
|
||||
int i;
|
||||
|
||||
/*printf("%s chip:%d hwctl:%x size:%d\n", __FUNCTION__, alpr_chip, hwctl, len);*/
|
||||
for (i = 0; i < len; i++) {
|
||||
if (hwctl & 0x1)
|
||||
alpr_write(buf[i], &(alpr_ndfc->cmd[alpr_chip]));
|
||||
else if (hwctl & 0x2) {
|
||||
alpr_write(buf[i], &(alpr_ndfc->addr_wait));
|
||||
} else {
|
||||
alpr_write(buf[i], &(alpr_ndfc->data));
|
||||
/*printf("i: %d\n", i);*/
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static void pdnb3_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < len; i++) {
|
||||
buf[i] = alpr_read(&(alpr_ndfc->data));
|
||||
}
|
||||
}
|
||||
|
||||
static int pdnb3_nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < len; i++)
|
||||
if (buf[i] != alpr_read(&(alpr_ndfc->data)))
|
||||
return i;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int pdnb3_nand_dev_ready(struct mtd_info *mtd)
|
||||
{
|
||||
#if 1
|
||||
volatile u_char val;
|
||||
|
||||
/*printf("%s aufruf\n", __FUNCTION__);*/
|
||||
/*
|
||||
* Blocking read to wait for NAND to be ready
|
||||
*/
|
||||
val = alpr_read(&(alpr_ndfc->addr_wait));
|
||||
|
||||
/*
|
||||
* Return always true
|
||||
*/
|
||||
return 1;
|
||||
#else
|
||||
u8 hwctl_org = hwctl;
|
||||
unsigned long timeo;
|
||||
u8 val;
|
||||
|
||||
hwctl = 0x01;
|
||||
pdnb3_nand_write_byte (mtd, NAND_CMD_STATUS);
|
||||
hwctl = hwctl_org;
|
||||
|
||||
reset_timer();
|
||||
while (1) {
|
||||
if (get_timer(0) > timeo) {
|
||||
printf("Timeout!");
|
||||
return 0;
|
||||
}
|
||||
|
||||
val = pdnb3_nand_read_byte(mtd);
|
||||
/*printf("%s val: %x\n", __FUNCTION__, val);*/
|
||||
if (val & NAND_STATUS_READY)
|
||||
break;
|
||||
}
|
||||
return 1;
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
static void alpr_select_chip(struct mtd_info *mtd, int chip)
|
||||
{
|
||||
alpr_chip = chip;
|
||||
}
|
||||
|
||||
static int alpr_nand_wait(struct mtd_info *mtd, struct nand_chip *this, int state)
|
||||
{
|
||||
unsigned long timeo;
|
||||
|
||||
if (state == FL_ERASING)
|
||||
timeo = CFG_HZ * 400;
|
||||
else
|
||||
timeo = CFG_HZ * 20;
|
||||
|
||||
if ((state == FL_ERASING) && (this->options & NAND_IS_AND))
|
||||
this->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1);
|
||||
else
|
||||
this->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
|
||||
|
||||
reset_timer();
|
||||
|
||||
while (1) {
|
||||
if (get_timer(0) > timeo) {
|
||||
printf("Timeout!");
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (this->read_byte(mtd) & NAND_STATUS_READY)
|
||||
break;
|
||||
}
|
||||
return this->read_byte(mtd);
|
||||
}
|
||||
|
||||
void board_nand_init(struct nand_chip *nand)
|
||||
{
|
||||
alpr_ndfc = (struct alpr_ndfc_regs *)CFG_NAND_BASE;
|
||||
|
||||
nand->eccmode = NAND_ECC_SOFT;
|
||||
|
||||
/* Set address of NAND IO lines (Using Linear Data Access Region) */
|
||||
nand->IO_ADDR_R = (void __iomem *) ((ulong) alpr_ndfc + 0x10);
|
||||
nand->IO_ADDR_W = (void __iomem *) ((ulong) alpr_ndfc + 0x10);
|
||||
/* Reference hardware control function */
|
||||
nand->hwcontrol = pdnb3_nand_hwcontrol;
|
||||
/* Set command delay time */
|
||||
nand->hwcontrol = pdnb3_nand_hwcontrol;
|
||||
nand->write_byte = pdnb3_nand_write_byte;
|
||||
nand->read_byte = pdnb3_nand_read_byte;
|
||||
nand->write_buf = pdnb3_nand_write_buf;
|
||||
nand->read_buf = pdnb3_nand_read_buf;
|
||||
nand->verify_buf = pdnb3_nand_verify_buf;
|
||||
nand->dev_ready = pdnb3_nand_dev_ready;
|
||||
nand->select_chip = alpr_select_chip;
|
||||
nand->waitfunc = alpr_nand_wait;
|
||||
}
|
||||
#endif
|
||||
157
board/prodrive/alpr/u-boot.lds
Normal file
157
board/prodrive/alpr/u-boot.lds
Normal file
@ -0,0 +1,157 @@
|
||||
/*
|
||||
* (C) Copyright 2004
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
OUTPUT_ARCH(powerpc)
|
||||
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
|
||||
/* Do we need any of these for elf?
|
||||
__DYNAMIC = 0; */
|
||||
SECTIONS
|
||||
{
|
||||
.resetvec 0xFFFFFFFC :
|
||||
{
|
||||
*(.resetvec)
|
||||
} = 0xffff
|
||||
|
||||
.bootpg 0xFFFFF000 :
|
||||
{
|
||||
cpu/ppc4xx/start.o (.bootpg)
|
||||
} = 0xffff
|
||||
|
||||
/* Read-only sections, merged into text segment: */
|
||||
. = + SIZEOF_HEADERS;
|
||||
.interp : { *(.interp) }
|
||||
.hash : { *(.hash) }
|
||||
.dynsym : { *(.dynsym) }
|
||||
.dynstr : { *(.dynstr) }
|
||||
.rel.text : { *(.rel.text) }
|
||||
.rela.text : { *(.rela.text) }
|
||||
.rel.data : { *(.rel.data) }
|
||||
.rela.data : { *(.rela.data) }
|
||||
.rel.rodata : { *(.rel.rodata) }
|
||||
.rela.rodata : { *(.rela.rodata) }
|
||||
.rel.got : { *(.rel.got) }
|
||||
.rela.got : { *(.rela.got) }
|
||||
.rel.ctors : { *(.rel.ctors) }
|
||||
.rela.ctors : { *(.rela.ctors) }
|
||||
.rel.dtors : { *(.rel.dtors) }
|
||||
.rela.dtors : { *(.rela.dtors) }
|
||||
.rel.bss : { *(.rel.bss) }
|
||||
.rela.bss : { *(.rela.bss) }
|
||||
.rel.plt : { *(.rel.plt) }
|
||||
.rela.plt : { *(.rela.plt) }
|
||||
.init : { *(.init) }
|
||||
.plt : { *(.plt) }
|
||||
.text :
|
||||
{
|
||||
/* WARNING - the following is hand-optimized to fit within */
|
||||
/* the sector layout of our flash chips! XXX FIXME XXX */
|
||||
|
||||
cpu/ppc4xx/start.o (.text)
|
||||
board/prodrive/alpr/init.o (.text)
|
||||
cpu/ppc4xx/kgdb.o (.text)
|
||||
cpu/ppc4xx/traps.o (.text)
|
||||
cpu/ppc4xx/interrupts.o (.text)
|
||||
cpu/ppc4xx/serial.o (.text)
|
||||
cpu/ppc4xx/cpu_init.o (.text)
|
||||
cpu/ppc4xx/speed.o (.text)
|
||||
common/dlmalloc.o (.text)
|
||||
lib_generic/crc32.o (.text)
|
||||
lib_ppc/extable.o (.text)
|
||||
lib_generic/zlib.o (.text)
|
||||
|
||||
/* . = env_offset;*/
|
||||
/* common/environment.o(.text)*/
|
||||
|
||||
*(.text)
|
||||
*(.fixup)
|
||||
*(.got1)
|
||||
}
|
||||
_etext = .;
|
||||
PROVIDE (etext = .);
|
||||
.rodata :
|
||||
{
|
||||
*(.rodata)
|
||||
*(.rodata1)
|
||||
*(.rodata.str1.4)
|
||||
*(.eh_frame)
|
||||
}
|
||||
.fini : { *(.fini) } =0
|
||||
.ctors : { *(.ctors) }
|
||||
.dtors : { *(.dtors) }
|
||||
|
||||
/* Read-write section, merged into data segment: */
|
||||
. = (. + 0x00FF) & 0xFFFFFF00;
|
||||
_erotext = .;
|
||||
PROVIDE (erotext = .);
|
||||
.reloc :
|
||||
{
|
||||
*(.got)
|
||||
_GOT2_TABLE_ = .;
|
||||
*(.got2)
|
||||
_FIXUP_TABLE_ = .;
|
||||
*(.fixup)
|
||||
}
|
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
|
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.data)
|
||||
*(.data1)
|
||||
*(.sdata)
|
||||
*(.sdata2)
|
||||
*(.dynamic)
|
||||
CONSTRUCTORS
|
||||
}
|
||||
_edata = .;
|
||||
PROVIDE (edata = .);
|
||||
|
||||
. = .;
|
||||
__u_boot_cmd_start = .;
|
||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||
__u_boot_cmd_end = .;
|
||||
|
||||
|
||||
. = .;
|
||||
__start___ex_table = .;
|
||||
__ex_table : { *(__ex_table) }
|
||||
__stop___ex_table = .;
|
||||
|
||||
. = ALIGN(256);
|
||||
__init_begin = .;
|
||||
.text.init : { *(.text.init) }
|
||||
.data.init : { *(.data.init) }
|
||||
. = ALIGN(256);
|
||||
__init_end = .;
|
||||
|
||||
__bss_start = .;
|
||||
.bss :
|
||||
{
|
||||
*(.sbss) *(.scommon)
|
||||
*(.dynbss)
|
||||
*(.bss)
|
||||
*(COMMON)
|
||||
}
|
||||
_end = . ;
|
||||
PROVIDE (end = .);
|
||||
}
|
||||
@ -475,7 +475,11 @@ void pci_440_init (struct pci_controller *hose)
|
||||
pci_set_region(hose->regions + reg_num++,
|
||||
CFG_PCI_TARGBASE,
|
||||
CFG_PCI_MEMBASE,
|
||||
#ifdef CFG_PCI_MEMSIZE
|
||||
CFG_PCI_MEMSIZE,
|
||||
#else
|
||||
0x10000000,
|
||||
#endif
|
||||
PCI_REGION_MEM );
|
||||
|
||||
#if defined(CONFIG_PCI_SYS_MEM_BUS) && defined(CONFIG_PCI_SYS_MEM_PHYS) && \
|
||||
|
||||
@ -502,6 +502,21 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
|
||||
* otherwise, just check the speeds & feeds
|
||||
*/
|
||||
if (hw_p->first_init == 0) {
|
||||
#if defined(CONFIG_88E1111_CLK_DELAY)
|
||||
/*
|
||||
* On some boards (e.g. ALPR) the Marvell 88E1111 PHY needs
|
||||
* the "RGMII transmit timing control" and "RGMII receive
|
||||
* timing control" bits set, so that Gbit communication works
|
||||
* without problems.
|
||||
* Also set the "Transmitter disable" to 1 to enable the
|
||||
* transmitter.
|
||||
* After setting these bits a soft-reset must occur for this
|
||||
* change to become active.
|
||||
*/
|
||||
miiphy_read (dev->name, reg, 0x14, ®_short);
|
||||
reg_short |= (1 << 7) | (1 << 1) | (1 << 0);
|
||||
miiphy_write (dev->name, reg, 0x14, reg_short);
|
||||
#endif
|
||||
miiphy_reset (dev->name, reg);
|
||||
|
||||
#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
|
||||
|
||||
@ -351,6 +351,14 @@ long int initdram(int board_type)
|
||||
int i;
|
||||
int tr1_bank1;
|
||||
|
||||
#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP)
|
||||
/*
|
||||
* Soft-reset SDRAM controller.
|
||||
*/
|
||||
mtsdr(sdr_srst, SDR0_SRST_DMC);
|
||||
mtsdr(sdr_srst, 0x00000000);
|
||||
#endif
|
||||
|
||||
for (i=0; i<N_MB0CF; i++) {
|
||||
/*
|
||||
* Disable memory controller.
|
||||
|
||||
393
include/configs/alpr.h
Normal file
393
include/configs/alpr.h
Normal file
@ -0,0 +1,393 @@
|
||||
/*
|
||||
* (C) Copyright 2006
|
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* High Level Configuration Options
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CONFIG_ALPR 1 /* Board is ebony */
|
||||
#define CONFIG_440GX 1 /* Specifc GX support */
|
||||
#define CONFIG_4xx 1 /* ... PPC4xx family */
|
||||
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
|
||||
#undef CFG_DRAM_TEST /* Disable-takes long time! */
|
||||
#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Base addresses -- Note these are effective addresses where the
|
||||
* actual resources get mapped (not physical addresses)
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
|
||||
#define CFG_FLASH_BASE 0xffe00000 /* start of FLASH */
|
||||
#define CFG_MONITOR_BASE 0xfffc0000 /* start of monitor */
|
||||
#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */
|
||||
#define CFG_PCI_MEMSIZE 0x40000000 /* size of mapped pci memory */
|
||||
#define CFG_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */
|
||||
#define CFG_ISRAM_BASE 0xc0000000 /* internal SRAM */
|
||||
#define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */
|
||||
#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000
|
||||
#define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000
|
||||
#define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000
|
||||
|
||||
|
||||
#define CFG_FPGA_BASE (CFG_PERIPHERAL_BASE + 0x08300000)
|
||||
#define CFG_NVRAM_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x08000000)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Initial RAM & stack pointer (placed in internal SRAM)
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CFG_TEMP_STACK_OCM 1
|
||||
#define CFG_OCM_DATA_ADDR CFG_ISRAM_BASE
|
||||
#define CFG_INIT_RAM_ADDR CFG_ISRAM_BASE /* Initial RAM address */
|
||||
#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */
|
||||
#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
|
||||
|
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
|
||||
#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4)
|
||||
#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR
|
||||
|
||||
#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
|
||||
#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc*/
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Serial Port
|
||||
*----------------------------------------------------------------------*/
|
||||
#undef CFG_EXT_SERIAL_CLOCK
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
#define CONFIG_UART1_CONSOLE /* define for uart1 as console */
|
||||
|
||||
#define CFG_BAUDRATE_TABLE \
|
||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Environment
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
|
||||
|
||||
#if 0 /* test-only */
|
||||
/*-----------------------------------------------------------------------
|
||||
* NVRAM/RTC
|
||||
*
|
||||
* NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located.
|
||||
* The DS1743 code assumes this condition (i.e. -- it assumes the base
|
||||
* address for the RTC registers is:
|
||||
*
|
||||
* CFG_NVRAM_BASE_ADDR + CFG_NVRAM_SIZE
|
||||
*
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CFG_NVRAM_SIZE (0x2000 - 8) /* NVRAM size(8k)- RTC regs */
|
||||
#define CONFIG_RTC_DS174x 1 /* DS1743 RTC */
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH related
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CFG_FLASH_CFI /* The flash is CFI compatible */
|
||||
#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
|
||||
|
||||
#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
|
||||
|
||||
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
|
||||
#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
|
||||
|
||||
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
|
||||
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
|
||||
|
||||
#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
|
||||
#define CFG_FLASH_PROTECTION 1 /* use hardware flash protection */
|
||||
|
||||
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
|
||||
#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
|
||||
|
||||
#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
|
||||
|
||||
#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
|
||||
#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
|
||||
#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
|
||||
|
||||
/* Address and size of Redundant Environment Sector */
|
||||
#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
|
||||
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* DDR SDRAM
|
||||
*----------------------------------------------------------------------*/
|
||||
#undef CONFIG_SPD_EEPROM /* Don't use SPD EEPROM for setup */
|
||||
#define CONFIG_SDRAM_BANK0 1 /* init onboard DDR SDRAM bank 0 */
|
||||
#undef CONFIG_SDRAM_ECC /* enable ECC support */
|
||||
#define CFG_SDRAM_TABLE { \
|
||||
{(256 << 20), 13, 0x000C4001}, /* 256MB mode 3, 13x10(4)*/ \
|
||||
{(64 << 20), 12, 0x00082001}} /* 64MB mode 2, 12x9(4) */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* I2C
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
|
||||
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
|
||||
#define CFG_I2C_SPEED 100000 /* I2C speed and slave address */
|
||||
#define CFG_I2C_SLAVE 0x7F
|
||||
#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* I2C EEPROM (PCF8594C)
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CFG_I2C_EEPROM_ADDR 0x54 /* EEPROM PCF8594C */
|
||||
#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
|
||||
/* mask of address bits that overflow into the "EEPROM chip address" */
|
||||
#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
|
||||
#define CFG_EEPROM_PAGE_WRITE_BITS 3 /* The Philips PCF8594C has */
|
||||
/* 8 byte page write mode using */
|
||||
/* last 3 bits of the address */
|
||||
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 40 /* and takes up to 40 msec */
|
||||
#define CFG_EEPROM_PAGE_WRITE_ENABLE
|
||||
|
||||
#define CONFIG_PREBOOT "echo;" \
|
||||
"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
|
||||
"echo"
|
||||
|
||||
#undef CONFIG_BOOTARGS
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"netdev=eth0\0" \
|
||||
"hostname=alpr\0" \
|
||||
"nfsargs=setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=${serverip}:${rootpath}\0" \
|
||||
"ramargs=setenv bootargs root=/dev/ram rw\0" \
|
||||
"addip=setenv bootargs ${bootargs} " \
|
||||
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
|
||||
":${hostname}:${netdev}:off panic=1\0" \
|
||||
"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
|
||||
"flash_nfs=run nfsargs addip addtty;" \
|
||||
"bootm ${kernel_addr}\0" \
|
||||
"flash_self=run ramargs addip addtty;" \
|
||||
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
|
||||
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
|
||||
"bootm\0" \
|
||||
"rootpath=/opt/eldk/ppc_4xx\0" \
|
||||
"bootfile=/tftpboot/alpr/uImage\0" \
|
||||
"kernel_addr=fff00000\0" \
|
||||
"ramdisk_addr=fff10000\0" \
|
||||
"load=tftp 100000 /tftpboot/alpr/u-boot.bin\0" \
|
||||
"update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
|
||||
"cp.b 100000 fffc0000 40000;" \
|
||||
"setenv filesize;saveenv\0" \
|
||||
"upd=run load;run update\0" \
|
||||
""
|
||||
#define CONFIG_BOOTCOMMAND "run flash_self"
|
||||
|
||||
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
|
||||
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
|
||||
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
|
||||
|
||||
#define CONFIG_MII 1 /* MII PHY management */
|
||||
#define CONFIG_NET_MULTI 1
|
||||
#define CONFIG_PHY_ADDR 0x02 /* dummy setting, no EMAC0 used */
|
||||
#define CONFIG_PHY1_ADDR 0x03 /* dummy setting, no EMAC1 used */
|
||||
#define CONFIG_PHY2_ADDR 0x00 /* test-only: will be changed */
|
||||
#define CONFIG_PHY3_ADDR 0x01 /* PHY address for EMAC3 */
|
||||
#define CONFIG_HAS_ETH0
|
||||
#define CONFIG_HAS_ETH1
|
||||
#define CONFIG_HAS_ETH2
|
||||
#define CONFIG_HAS_ETH3
|
||||
#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
|
||||
#define CONFIG_88E1111_CLK_DELAY 1 /* set CLK delay on ALPR */
|
||||
#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
|
||||
|
||||
#if 0 /* test-only */
|
||||
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
|
||||
CFG_CMD_ASKENV | \
|
||||
CFG_CMD_DATE | \
|
||||
CFG_CMD_DHCP | \
|
||||
CFG_CMD_DIAG | \
|
||||
CFG_CMD_ELF | \
|
||||
CFG_CMD_I2C | \
|
||||
CFG_CMD_IRQ | \
|
||||
CFG_CMD_MII | \
|
||||
CFG_CMD_NET | \
|
||||
CFG_CMD_NFS | \
|
||||
CFG_CMD_PCI | \
|
||||
CFG_CMD_PING | \
|
||||
CFG_CMD_REGINFO | \
|
||||
CFG_CMD_SNTP )
|
||||
#else
|
||||
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
|
||||
CFG_CMD_ASKENV | \
|
||||
CFG_CMD_DHCP | \
|
||||
CFG_CMD_DIAG | \
|
||||
CFG_CMD_EEPROM | \
|
||||
CFG_CMD_ELF | \
|
||||
CFG_CMD_I2C | \
|
||||
CFG_CMD_IRQ | \
|
||||
CFG_CMD_MII | \
|
||||
CFG_CMD_NET | \
|
||||
CFG_CMD_NFS | \
|
||||
CFG_CMD_PCI | \
|
||||
CFG_CMD_PING | \
|
||||
CFG_CMD_FPGA | \
|
||||
CFG_CMD_NAND | \
|
||||
CFG_CMD_REGINFO)
|
||||
#endif
|
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
|
||||
#include <cmd_confdefs.h>
|
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CFG_LONGHELP /* undef to save memory */
|
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
|
||||
#else
|
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#endif
|
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
|
||||
#define CFG_MAXARGS 16 /* max number of command args */
|
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
|
||||
|
||||
#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
|
||||
#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
|
||||
|
||||
#define CFG_LOAD_ADDR 0x100000 /* default load address */
|
||||
#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
|
||||
|
||||
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
|
||||
|
||||
#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
|
||||
#define CONFIG_LOOPW 1 /* enable loopw command */
|
||||
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
|
||||
#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
|
||||
|
||||
#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
|
||||
|
||||
#define CONFIG_NETCONSOLE /* include NetConsole support */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PCI stuff
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
/* General PCI */
|
||||
#define CONFIG_PCI /* include pci support */
|
||||
#define CONFIG_PCI_PNP /* do pci plug-and-play */
|
||||
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
|
||||
#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */
|
||||
#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/
|
||||
|
||||
/* Board-specific PCI */
|
||||
#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
|
||||
#define CFG_PCI_TARGET_INIT /* let board init pci target */
|
||||
#define CFG_PCI_MASTER_INIT
|
||||
|
||||
#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
|
||||
#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FPGA stuff
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
#define CONFIG_FPGA CFG_ALTERA_CYCLON2
|
||||
#undef CFG_FPGA_CHECK_CTRLC
|
||||
#undef CFG_FPGA_PROG_FEEDBACK
|
||||
#define CONFIG_FPGA_COUNT 1 /* Ich habe 2 ... aber in
|
||||
Reihe geschaltet -> sollte gehen,
|
||||
aufpassen mit Datasize ist jetzt
|
||||
halt doppelt so gross ... Seite 306
|
||||
ist das mit den multiple Device in PS
|
||||
Mode erklaert ...*/
|
||||
|
||||
|
||||
/* FPGA program pin configuration */
|
||||
#define CFG_GPIO_CLK 18 /* FPGA clk pin (cpu output) */
|
||||
#define CFG_GPIO_DATA 19 /* FPGA data pin (cpu output) */
|
||||
#define CFG_GPIO_STATUS 20 /* FPGA status pin (cpu input) */
|
||||
#define CFG_GPIO_CONFIG 21 /* FPGA CONFIG pin (cpu output) */
|
||||
#define CFG_GPIO_CON_DON 22 /* FPGA CONFIG_DONE pin (cpu input) */
|
||||
|
||||
#define CFG_GPIO_SEL_DPR 14 /* cpu output */
|
||||
#define CFG_GPIO_SEL_AVR 15 /* cpu output */
|
||||
#define CFG_GPIO_PROG_EN 23 /* cpu output */
|
||||
|
||||
/*
|
||||
* NAND-FLASH stuff
|
||||
*/
|
||||
#define CFG_MAX_NAND_DEVICE 2
|
||||
#define NAND_MAX_CHIPS 2
|
||||
#define CFG_NAND_BASE 0x50000000 /* NAND FLASH Base Address */
|
||||
|
||||
#if 0
|
||||
#define CONFIG_MTD_DEBUG
|
||||
#define CONFIG_MTD_DEBUG_VERBOSE 4
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* External Bus Controller (EBC) Setup
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CFG_FLASH CFG_FLASH_BASE
|
||||
|
||||
/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
|
||||
#define CFG_EBC_PB0AP 0x92015480
|
||||
#define CFG_EBC_PB0CR (CFG_FLASH | 0x3A000) /* BS=2MB,BU=R/W,BW=16bit */
|
||||
/* Memory Bank 1 (NAND-FLASH) initialization */
|
||||
/*#define CFG_EBC_PB1AP 0x108f4380 */ /* TODO */
|
||||
/*#define CFG_EBC_PB1AP 0x7f854380 */ /* TODO */
|
||||
/*#define CFG_EBC_PB1AP 0x108553c0 */
|
||||
/*#define CFG_EBC_PB1AP 0x108053c0 */
|
||||
#define CFG_EBC_PB1AP 0x10810180
|
||||
|
||||
/*#define CFG_EBC_PB1CR (CFG_NAND_BASE | 0x18000) *//* BS=1MB,BU=R/W,BW=8bit */
|
||||
#define CFG_EBC_PB1CR (CFG_NAND_BASE | 0x1A000) /* BS=1MB,BU=R/W,BW=16bit */
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 8 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization.
|
||||
*/
|
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration
|
||||
*/
|
||||
#define CFG_DCACHE_SIZE 32768 /* For AMCC 440 CPUs */
|
||||
#define CFG_CACHELINE_SIZE 32 /* ... */
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||||
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Internal Definitions
|
||||
*
|
||||
* Boot Flags
|
||||
*/
|
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
|
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */
|
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||||
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
|
||||
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
|
||||
#endif
|
||||
#endif /* __CONFIG_H */
|
||||
@ -2631,7 +2631,7 @@
|
||||
#define GPIO0 0
|
||||
#define GPIO1 1
|
||||
|
||||
#if defined(CONFIG_440GP)
|
||||
#if defined(CONFIG_440GP) || defined(CONFIG_440GX)
|
||||
#define GPIO0_BASE (CFG_PERIPHERAL_BASE+0x00000700)
|
||||
|
||||
#define GPIO0_OR (GPIO0_BASE+0x0)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user