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Layerscape: Enable Job ring driver model.

Browse Source 
LS(1021/1012/1028/1043/1046/1088/2088), LX2160, LX2162
platforms are enabled with JR driver model.

removed sec_init() call from board files.
sec is initialized based on job ring information processed
from device tree.

Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: Michael Walle <michael@walle.cc>
This commit is contained in:
Gaurav Jain 2022-03-24 11:50:35 +05:30 committed by Stefano Babic
parent 88071ca2bb
commit 8976556a8a
62 changed files with 88 additions and 89 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
arch/arm/cpu/armv7/ls102xa/cpu.c
View File

@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2014 Freescale Semiconductor, Inc.
* Copyright 2021 NXP
*/
#include <common.h>
@ -20,6 +21,7 @@
#include <config.h>
#include <fsl_wdog.h>
#include <linux/delay.h>
#include <dm.h>
#include "fsl_epu.h"
@ -397,3 +399,19 @@ void arch_preboot_os(void)
ctrl &= ~ARCH_TIMER_CTRL_ENABLE;
asm("mcr p15, 0, %0, c14, c2, 1" : : "r" (ctrl));
}
#ifdef CONFIG_ARCH_MISC_INIT
int arch_misc_init(void)
{
if (IS_ENABLED(CONFIG_FSL_CAAM)) {
struct udevice *dev;
int ret;
ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
if (ret)
printf("Failed to initialize %s: %d\n", dev->name, ret);
}
return 0;
}
#endif

11
arch/arm/cpu/armv8/fsl-layerscape/cpu.c
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2017-2020 NXP
* Copyright 2017-2021 NXP
* Copyright 2014-2015 Freescale Semiconductor, Inc.
*/
@ -49,6 +49,7 @@
#endif
#endif
#include <linux/mii.h>
#include <dm.h>
DECLARE_GLOBAL_DATA_PTR;
@ -1652,6 +1653,14 @@ __weak int serdes_misc_init(void)
int arch_misc_init(void)
{
if (IS_ENABLED(CONFIG_FSL_CAAM)) {
struct udevice *dev;
int ret;
ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
if (ret)
printf("Failed to initialize %s: %d\n", dev->name, ret);
}
serdes_misc_init();
return 0;

7
board/freescale/ls1012afrdm/ls1012afrdm.c
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2017-2018 NXP
* Copyright 2017-2018, 2021 NXP
*/
#include <common.h>
@ -22,7 +22,6 @@
#include <env_internal.h>
#include <fsl_mmdc.h>
#include <netdev.h>
#include <fsl_sec.h>
#include <net/pfe_eth/pfe/pfe_hw.h>
DECLARE_GLOBAL_DATA_PTR;
@ -172,10 +171,6 @@ int board_init(void)
if (current_el() == 3)
out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
#ifdef CONFIG_FSL_CAAM
sec_init();
#endif
#ifdef CONFIG_FSL_LS_PPA
ppa_init();
#endif

6
board/freescale/ls1012aqds/ls1012aqds.c
View File

@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2016 Freescale Semiconductor, Inc.
* Copyright 2021 NXP
*/
#include <common.h>
@ -28,7 +29,6 @@
#include <fsl_mmdc.h>
#include <spl.h>
#include <netdev.h>
#include <fsl_sec.h>
#include "../common/qixis.h"
#include "ls1012aqds_qixis.h"
#include "ls1012aqds_pfe.h"
@ -150,10 +150,6 @@ int board_init(void)
erratum_a010315();
#endif
#ifdef CONFIG_FSL_CAAM
sec_init();
#endif
#ifdef CONFIG_FSL_LS_PPA
ppa_init();
#endif

6
board/freescale/ls1012ardb/ls1012ardb.c
View File

@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2016 Freescale Semiconductor, Inc.
* Copyright 2021 NXP
*/
#include <common.h>
@ -27,7 +28,6 @@
#include <env_internal.h>
#include <fsl_mmdc.h>
#include <netdev.h>
#include <fsl_sec.h>
#include <net/pfe_eth/pfe/pfe_hw.h>
DECLARE_GLOBAL_DATA_PTR;
@ -173,10 +173,6 @@ int board_init(void)
erratum_a010315();
#endif
#ifdef CONFIG_FSL_CAAM
sec_init();
#endif
#ifdef CONFIG_FSL_LS_PPA
ppa_init();
#endif

6
board/freescale/ls1021aiot/ls1021aiot.c
View File

@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2016 Freescale Semiconductor, Inc.
* Copyright 2021 NXP
*/
#include <common.h>
@ -209,10 +210,7 @@ int misc_init_r(void)
device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
#endif
#ifdef CONFIG_FSL_CAAM
return sec_init();
#endif
return 0;
}
#endif

6
board/freescale/ls1021aqds/ls1021aqds.c
View File

@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2014 Freescale Semiconductor, Inc.
* Copyright 2019 NXP
* Copyright 2019, 2021 NXP
*/
#include <common.h>
@ -20,7 +20,6 @@
#include <mmc.h>
#include <fsl_csu.h>
#include <fsl_ifc.h>
#include <fsl_sec.h>
#include <spl.h>
#include <fsl_devdis.h>
#include <fsl_validate.h>
@ -388,9 +387,6 @@ int misc_init_r(void)
#ifdef CONFIG_FSL_DEVICE_DISABLE
device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
#endif
#ifdef CONFIG_FSL_CAAM
return sec_init();
#endif
return 0;
}

7
board/freescale/ls1021atsn/ls1021atsn.c
View File

@ -1,5 +1,5 @@
// SPDX-License-Identifier: GPL-2.0
/* Copyright 2016-2019 NXP
/* Copyright 2016-2019, 2021 NXP
*/
#include <common.h>
#include <clock_legacy.h>
@ -238,10 +238,7 @@ int misc_init_r(void)
#ifdef CONFIG_FSL_DEVICE_DISABLE
device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
#endif
#ifdef CONFIG_FSL_CAAM
return sec_init();
#endif
return 0;
}
#endif

8
board/freescale/ls1021atwr/ls1021atwr.c
View File

@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2014 Freescale Semiconductor, Inc.
* Copyright 2019 NXP
* Copyright 2019, 2021 NXP
*/
#include <common.h>
@ -26,7 +26,6 @@
#include <netdev.h>
#include <fsl_mdio.h>
#include <tsec.h>
#include <fsl_sec.h>
#include <fsl_devdis.h>
#include <spl.h>
#include <linux/delay.h>
@ -555,10 +554,7 @@ int misc_init_r(void)
#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
config_board_mux();
#endif
#ifdef CONFIG_FSL_CAAM
return sec_init();
#endif
return 0;
}
#endif

6
board/freescale/ls1028a/ls1028a.c
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2019 NXP
* Copyright 2019, 2021 NXP
*/
#include <common.h>
@ -73,10 +73,6 @@ u32 get_lpuart_clk(void)
int board_init(void)
{
#ifdef CONFIG_FSL_CAAM
sec_init();
#endif
#ifdef CONFIG_FSL_LS_PPA
ppa_init();
#endif

6
board/freescale/ls1043ardb/ls1043ardb.c
View File

@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2015 Freescale Semiconductor, Inc.
* Copyright 2021 NXP
*/
#include <common.h>
@ -20,7 +21,6 @@
#include <fm_eth.h>
#include <fsl_esdhc.h>
#include <fsl_ifc.h>
#include <fsl_sec.h>
#include "cpld.h"
#ifdef CONFIG_U_QE
#include <fsl_qe.h>
@ -211,10 +211,6 @@ int board_init(void)
out_le32(SMMU_NSCR0, val);
#endif
#ifdef CONFIG_FSL_CAAM
sec_init();
#endif
#ifdef CONFIG_FSL_LS_PPA
ppa_init();
#endif

7
board/freescale/ls1046afrwy/ls1046afrwy.c
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2019 NXP
* Copyright 2019, 2021 NXP
*/
#include <common.h>
@ -20,7 +20,6 @@
#include <fm_eth.h>
#include <fsl_csu.h>
#include <fsl_esdhc.h>
#include <fsl_sec.h>
#include <fsl_dspi.h>
#include "../common/i2c_mux.h"
@ -135,10 +134,6 @@ val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
out_le32(SMMU_NSCR0, val);
#endif
#ifdef CONFIG_FSL_CAAM
sec_init();
#endif
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
return 0;
}

7
board/freescale/ls1046aqds/ls1046aqds.c
View File

@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2016 Freescale Semiconductor, Inc.
* Copyright 2019-2020 NXP
* Copyright 2019-2021 NXP
*/
#include <common.h>
@ -28,7 +28,6 @@
#include <fsl_csu.h>
#include <fsl_esdhc.h>
#include <fsl_ifc.h>
#include <fsl_sec.h>
#include <spl.h>
#include "../common/i2c_mux.h"
@ -421,10 +420,6 @@ int board_init(void)
out_le32(SMMU_NSCR0, val);
#endif
#ifdef CONFIG_FSL_CAAM
sec_init();
#endif
return 0;
}

6
board/freescale/ls1046ardb/ls1046ardb.c
View File

@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2016 Freescale Semiconductor, Inc.
* Copyright 2021 NXP
*/
#include <common.h>
@ -25,7 +26,6 @@
#include <fsl_esdhc.h>
#include <power/mc34vr500_pmic.h>
#include "cpld.h"
#include <fsl_sec.h>
DECLARE_GLOBAL_DATA_PTR;
@ -96,10 +96,6 @@ int board_init(void)
out_le32(SMMU_NSCR0, val);
#endif
#ifdef CONFIG_FSL_CAAM
sec_init();
#endif
#ifdef CONFIG_FSL_LS_PPA
ppa_init();
#endif

4
board/freescale/ls1088a/ls1088a.c
View File

@ -13,7 +13,6 @@
#include <netdev.h>
#include <fsl_ifc.h>
#include <fsl_ddr.h>
#include <fsl_sec.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <fdt_support.h>
@ -820,9 +819,6 @@ int board_init(void)
out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR105_IRQ_MASK);
#endif
#ifdef CONFIG_FSL_CAAM
sec_init();
#endif
#ifdef CONFIG_FSL_LS_PPA
ppa_init();
#endif

6
board/freescale/ls2080aqds/ls2080aqds.c
View File

@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2015 Freescale Semiconductor
* Copyright 2021 NXP
*/
#include <common.h>
#include <clock_legacy.h>
@ -21,7 +22,6 @@
#include <rtc.h>
#include <asm/arch/soc.h>
#include <hwconfig.h>
#include <fsl_sec.h>
#include <asm/arch/ppa.h>
#include <asm/arch-fsl-layerscape/fsl_icid.h>
#include "../common/i2c_mux.h"
@ -222,10 +222,6 @@ int board_init(void)
#endif
#endif
#ifdef CONFIG_FSL_CAAM
sec_init();
#endif
#ifdef CONFIG_FSL_LS_PPA
ppa_init();
#endif

9
board/freescale/ls2080ardb/ls2080ardb.c
View File

@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2015 Freescale Semiconductor
* Copyright 2017 NXP
* Copyright 2017, 2021 NXP
*/
#include <common.h>
#include <clock_legacy.h>
@ -24,7 +24,6 @@
#include <asm/arch/mmu.h>
#include <asm/arch/soc.h>
#include <asm/arch/ppa.h>
#include <fsl_sec.h>
#include <asm/arch-fsl-layerscape/fsl_icid.h>
#include "../common/i2c_mux.h"
@ -288,9 +287,6 @@ int board_init(void)
QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN);
#endif
#ifdef CONFIG_FSL_CAAM
sec_init();
#endif
#ifdef CONFIG_FSL_LS_PPA
ppa_init();
#endif
@ -299,9 +295,6 @@ int board_init(void)
/* invert AQR405 IRQ pins polarity */
out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR405_IRQ_MASK);
#endif
#ifdef CONFIG_FSL_CAAM
sec_init();
#endif
#if !defined(CONFIG_SYS_EARLY_PCI_INIT) && defined(CONFIG_DM_ETH)
pci_init();

5
board/freescale/lx2160a/lx2160a.c
View File

@ -14,7 +14,6 @@
#include <errno.h>
#include <netdev.h>
#include <fsl_ddr.h>
#include <fsl_sec.h>
#include <asm/io.h>
#include <fdt_support.h>
#include <linux/bitops.h>
@ -593,10 +592,6 @@ int board_init(void)
out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR107_IRQ_MASK);
#endif
#ifdef CONFIG_FSL_CAAM
sec_init();
#endif
#if !defined(CONFIG_SYS_EARLY_PCI_INIT) && defined(CONFIG_DM_ETH)
pci_init();
#endif

3
board/kontron/sl28/sl28.c
View File

@ -31,9 +31,6 @@ int board_early_init_f(void)
int board_init(void)
{
if (CONFIG_IS_ENABLED(FSL_CAAM))
sec_init();
return 0;
}

1
configs/ls1021aiot_qspi_defconfig
View File

@ -43,6 +43,7 @@ CONFIG_DM=y
CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y

1
configs/ls1021aiot_sdcard_defconfig
View File

@ -60,6 +60,7 @@ CONFIG_DM=y
CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y

1
configs/ls1021aqds_ddr4_nor_defconfig
View File

@ -57,6 +57,7 @@ CONFIG_DM=y
CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y

1
configs/ls1021aqds_ddr4_nor_lpuart_defconfig
View File

@ -57,6 +57,7 @@ CONFIG_DM=y
CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y

1
configs/ls1021aqds_nand_defconfig
View File

@ -77,6 +77,7 @@ CONFIG_DM=y
CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_DDR_ECC=y

1
configs/ls1021aqds_nor_defconfig
View File

@ -57,6 +57,7 @@ CONFIG_DM=y
CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_DDR_ECC=y

1
configs/ls1021aqds_nor_lpuart_defconfig
View File

@ -57,6 +57,7 @@ CONFIG_DM=y
CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_DDR_ECC=y

1
configs/ls1021aqds_qspi_defconfig
View File

@ -55,6 +55,7 @@ CONFIG_DM=y
CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y

1
configs/ls1021aqds_sdcard_ifc_defconfig
View File

@ -75,6 +75,7 @@ CONFIG_DM=y
CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_DDR_ECC=y

1
configs/ls1021aqds_sdcard_qspi_defconfig
View File

@ -72,6 +72,7 @@ CONFIG_DM=y
CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y

1
configs/ls1021atsn_qspi_defconfig
View File

@ -38,6 +38,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y

1
configs/ls1021atsn_sdcard_defconfig
View File

@ -54,6 +54,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y

1
configs/ls1021atwr_nor_defconfig
View File

@ -49,6 +49,7 @@ CONFIG_DM=y
CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y

1
configs/ls1021atwr_nor_lpuart_defconfig
View File

@ -49,6 +49,7 @@ CONFIG_DM=y
CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y

1
configs/ls1021atwr_qspi_defconfig
View File

@ -50,6 +50,7 @@ CONFIG_DM=y
CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y

1
configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig
View File

@ -64,6 +64,7 @@ CONFIG_USE_ETHPRIME=y
CONFIG_ETHPRIME="ethernet@2d10000"
CONFIG_DM=y
CONFIG_SPL_DM=y
CONFIG_SPL_OF_CONTROL=y
# CONFIG_SPL_BLK is not set
CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y

1
configs/ls1021atwr_sdcard_ifc_defconfig
View File

@ -67,6 +67,7 @@ CONFIG_DM=y
CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y

1
configs/ls1021atwr_sdcard_qspi_defconfig
View File

@ -67,6 +67,7 @@ CONFIG_DM=y
CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y

1
configs/ls1043aqds_defconfig
View File

@ -55,6 +55,7 @@ CONFIG_DM=y
CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y

1
configs/ls1043aqds_lpuart_defconfig
View File

@ -55,6 +55,7 @@ CONFIG_DM=y
CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y

1
configs/ls1043aqds_nand_defconfig
View File

@ -74,6 +74,7 @@ CONFIG_DM=y
CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y

1
configs/ls1043aqds_nor_ddr3_defconfig
View File

@ -55,6 +55,7 @@ CONFIG_DM=y
CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_DDR_ECC=y

1
configs/ls1043aqds_qspi_defconfig
View File

@ -55,6 +55,7 @@ CONFIG_DM=y
CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y

1
configs/ls1043aqds_sdcard_ifc_defconfig
View File

@ -74,6 +74,7 @@ CONFIG_DM=y
CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y

1
configs/ls1043aqds_sdcard_qspi_defconfig
View File

@ -72,6 +72,7 @@ CONFIG_DM=y
CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y

1
configs/ls1043aqds_tfa_defconfig
View File

@ -62,6 +62,7 @@ CONFIG_DM=y
CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y

1
configs/ls1043ardb_defconfig
View File

@ -41,6 +41,7 @@ CONFIG_USE_ETHPRIME=y
CONFIG_ETHPRIME="FM1@DTSEC3"
CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_ARCH_MISC_INIT=y
# CONFIG_DDR_SPD is not set
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_MPC8XXX_GPIO=y

1
configs/ls1043ardb_nand_defconfig
View File

@ -61,6 +61,7 @@ CONFIG_USE_ETHPRIME=y
CONFIG_ETHPRIME="FM1@DTSEC3"
CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y

1
configs/ls1043ardb_sdcard_defconfig
View File

@ -61,6 +61,7 @@ CONFIG_USE_ETHPRIME=y
CONFIG_ETHPRIME="FM1@DTSEC3"
CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y

1
configs/ls1043ardb_tfa_defconfig
View File

@ -45,6 +45,7 @@ CONFIG_USE_ETHPRIME=y
CONFIG_ETHPRIME="FM1@DTSEC3"
CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_ARCH_MISC_INIT=y
# CONFIG_DDR_SPD is not set
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_MPC8XXX_GPIO=y

1
configs/ls1046afrwy_tfa_defconfig
View File

@ -44,6 +44,7 @@ CONFIG_DM=y
CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_ARCH_MISC_INIT=y
# CONFIG_DDR_SPD is not set
CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y

1
configs/ls1046aqds_defconfig
View File

@ -56,6 +56,7 @@ CONFIG_DM=y
CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y

1
configs/ls1046aqds_lpuart_defconfig
View File

@ -56,6 +56,7 @@ CONFIG_DM=y
CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y

1
configs/ls1046aqds_nand_defconfig
View File

@ -75,6 +75,7 @@ CONFIG_DM=y
CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y

1
configs/ls1046aqds_qspi_defconfig
View File

@ -56,6 +56,7 @@ CONFIG_DM=y
CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y

1
configs/ls1046aqds_sdcard_ifc_defconfig
View File

@ -76,6 +76,7 @@ CONFIG_DM=y
CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y

1
configs/ls1046aqds_sdcard_qspi_defconfig
View File

@ -74,6 +74,7 @@ CONFIG_DM=y
CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y

1
configs/ls1046aqds_tfa_defconfig
View File

@ -63,6 +63,7 @@ CONFIG_DM=y
CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y

1
configs/ls1046ardb_emmc_defconfig
View File

@ -64,6 +64,7 @@ CONFIG_DM=y
CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_MPC8XXX_GPIO=y

1
configs/ls1046ardb_qspi_defconfig
View File

@ -51,6 +51,7 @@ CONFIG_DM=y
CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_MPC8XXX_GPIO=y

1
configs/ls1046ardb_qspi_spl_defconfig
View File

@ -70,6 +70,7 @@ CONFIG_DM=y
CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_MPC8XXX_GPIO=y

1
configs/ls1046ardb_sdcard_defconfig
View File

@ -64,6 +64,7 @@ CONFIG_DM=y
CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_MPC8XXX_GPIO=y

1
configs/ls1046ardb_tfa_defconfig
View File

@ -49,6 +49,7 @@ CONFIG_DM=y
CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_MPC8XXX_GPIO=y