tegra: usb: Add support for Tegra USB peripheral
This adds basic support for the Tegra2 USB controller. Board files should
call board_usb_init() to set things up.
Configuration is performed through the FDT, with aliases used to set the
order of the ports, like this fragment:
aliases {
/* This defines the order of our USB ports */
usb0 = "/usb@0xc5008000";
usb1 = "/usb@0xc5000000";
};
drivers/usb/host files ONLY: Acked-by: Remy Bohmer <linux@bohmer.net>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This commit is contained in:
Simon Glass
Albert ARIBAUD
parent
ed2974493e
commit
87f938c9f7
@ -33,8 +33,10 @@ include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(SOC).o
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SOBJS := lowlevel_init.o
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COBJS := ap20.o board.o clock.o funcmux.o pinmux.o sys_info.o timer.o
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COBJS-y := ap20.o board.o clock.o funcmux.o pinmux.o sys_info.o timer.o
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COBJS-$(CONFIG_USB_EHCI_TEGRA) += usb.o
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COBJS := $(COBJS-y)
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
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460
arch/arm/cpu/armv7/tegra2/usb.c
Normal file
460
arch/arm/cpu/armv7/tegra2/usb.c
Normal file
@ -0,0 +1,460 @@
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/*
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* Copyright (c) 2011 The Chromium OS Authors.
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* (C) Copyright 2010,2011 NVIDIA Corporation <www.nvidia.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm-generic/gpio.h>
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#include <asm/arch/tegra2.h>
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#include <asm/arch/clk_rst.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/pinmux.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/uart.h>
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#include <asm/arch/usb.h>
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#include <libfdt.h>
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#include <fdtdec.h>
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enum {
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USB_PORTS_MAX = 4, /* Maximum ports we allow */
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};
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/* Parameters we need for USB */
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enum {
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PARAM_DIVN, /* PLL FEEDBACK DIVIDer */
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PARAM_DIVM, /* PLL INPUT DIVIDER */
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PARAM_DIVP, /* POST DIVIDER (2^N) */
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PARAM_CPCON, /* BASE PLLC CHARGE Pump setup ctrl */
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PARAM_LFCON, /* BASE PLLC LOOP FILter setup ctrl */
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PARAM_ENABLE_DELAY_COUNT, /* PLL-U Enable Delay Count */
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PARAM_STABLE_COUNT, /* PLL-U STABLE count */
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PARAM_ACTIVE_DELAY_COUNT, /* PLL-U Active delay count */
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PARAM_XTAL_FREQ_COUNT, /* PLL-U XTAL frequency count */
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PARAM_DEBOUNCE_A_TIME, /* 10MS DELAY for BIAS_DEBOUNCE_A */
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PARAM_BIAS_TIME, /* 20US DELAY AFter bias cell op */
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PARAM_COUNT
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};
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/* Possible port types (dual role mode) */
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enum dr_mode {
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DR_MODE_NONE = 0,
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DR_MODE_HOST, /* supports host operation */
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DR_MODE_DEVICE, /* supports device operation */
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DR_MODE_OTG, /* supports both */
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};
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/* Information about a USB port */
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struct fdt_usb {
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struct usb_ctlr *reg; /* address of registers in physical memory */
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unsigned utmi:1; /* 1 if port has external tranceiver, else 0 */
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unsigned enabled:1; /* 1 to enable, 0 to disable */
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unsigned has_legacy_mode:1; /* 1 if this port has legacy mode */
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enum dr_mode dr_mode; /* dual role mode */
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enum periph_id periph_id;/* peripheral id */
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struct fdt_gpio_state vbus_gpio; /* GPIO for vbus enable */
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};
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static struct fdt_usb port[USB_PORTS_MAX]; /* List of valid USB ports */
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static unsigned port_count; /* Number of available ports */
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static int port_current; /* Current port (-1 = none) */
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/*
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* This table has USB timing parameters for each Oscillator frequency we
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* support. There are four sets of values:
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*
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* 1. PLLU configuration information (reference clock is osc/clk_m and
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* PLLU-FOs are fixed at 12MHz/60MHz/480MHz).
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*
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* Reference frequency 13.0MHz 19.2MHz 12.0MHz 26.0MHz
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* ----------------------------------------------------------------------
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* DIVN 960 (0x3c0) 200 (0c8) 960 (3c0h) 960 (3c0)
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* DIVM 13 (0d) 4 (04) 12 (0c) 26 (1a)
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* Filter frequency (MHz) 1 4.8 6 2
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* CPCON 1100b 0011b 1100b 1100b
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* LFCON0 0 0 0 0
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*
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* 2. PLL CONFIGURATION & PARAMETERS for different clock generators:
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*
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* Reference frequency 13.0MHz 19.2MHz 12.0MHz 26.0MHz
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* ---------------------------------------------------------------------------
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* PLLU_ENABLE_DLY_COUNT 02 (0x02) 03 (03) 02 (02) 04 (04)
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* PLLU_STABLE_COUNT 51 (33) 75 (4B) 47 (2F) 102 (66)
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* PLL_ACTIVE_DLY_COUNT 05 (05) 06 (06) 04 (04) 09 (09)
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* XTAL_FREQ_COUNT 127 (7F) 187 (BB) 118 (76) 254 (FE)
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*
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* 3. Debounce values IdDig, Avalid, Bvalid, VbusValid, VbusWakeUp, and
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* SessEnd. Each of these signals have their own debouncer and for each of
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* those one out of two debouncing times can be chosen (BIAS_DEBOUNCE_A or
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* BIAS_DEBOUNCE_B).
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*
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* The values of DEBOUNCE_A and DEBOUNCE_B are calculated as follows:
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* 0xffff -> No debouncing at all
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* <n> ms = <n> *1000 / (1/19.2MHz) / 4
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*
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* So to program a 1 ms debounce for BIAS_DEBOUNCE_A, we have:
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* BIAS_DEBOUNCE_A[15:0] = 1000 * 19.2 / 4 = 4800 = 0x12c0
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*
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* We need to use only DebounceA for BOOTROM. We don't need the DebounceB
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* values, so we can keep those to default.
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*
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* 4. The 20 microsecond delay after bias cell operation.
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*/
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static const unsigned usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = {
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/* DivN, DivM, DivP, CPCON, LFCON, Delays Debounce, Bias */
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{ 0x3C0, 0x0D, 0x00, 0xC, 0, 0x02, 0x33, 0x05, 0x7F, 0x7EF4, 5 },
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{ 0x0C8, 0x04, 0x00, 0x3, 0, 0x03, 0x4B, 0x06, 0xBB, 0xBB80, 7 },
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{ 0x3C0, 0x0C, 0x00, 0xC, 0, 0x02, 0x2F, 0x04, 0x76, 0x7530, 5 },
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{ 0x3C0, 0x1A, 0x00, 0xC, 0, 0x04, 0x66, 0x09, 0xFE, 0xFDE8, 9 }
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};
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/* UTMIP Idle Wait Delay */
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static const u8 utmip_idle_wait_delay = 17;
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/* UTMIP Elastic limit */
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static const u8 utmip_elastic_limit = 16;
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/* UTMIP High Speed Sync Start Delay */
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static const u8 utmip_hs_sync_start_delay = 9;
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/* Put the port into host mode (this only works for OTG ports) */
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static void set_host_mode(struct fdt_usb *config)
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{
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if (config->dr_mode == DR_MODE_OTG) {
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/* Check whether remote host from USB1 is driving VBus */
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if (readl(&config->reg->phy_vbus_sensors) & VBUS_VLD_STS)
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return;
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/*
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* If not driving, we set the GPIO to enable VBUS. We assume
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* that the pinmux is set up correctly for this.
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*/
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if (fdt_gpio_isvalid(&config->vbus_gpio)) {
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fdtdec_setup_gpio(&config->vbus_gpio);
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gpio_direction_output(config->vbus_gpio.gpio, 1);
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debug("set_host_mode: GPIO %d high\n",
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config->vbus_gpio.gpio);
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}
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}
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}
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void usbf_reset_controller(struct fdt_usb *config, struct usb_ctlr *usbctlr)
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{
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/* Reset the USB controller with 2us delay */
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reset_periph(config->periph_id, 2);
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/*
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* Set USB1_NO_LEGACY_MODE to 1, Registers are accessible under
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* base address
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*/
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if (config->has_legacy_mode)
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setbits_le32(&usbctlr->usb1_legacy_ctrl, USB1_NO_LEGACY_MODE);
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/* Put UTMIP1/3 in reset */
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setbits_le32(&usbctlr->susp_ctrl, UTMIP_RESET);
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/* Enable the UTMIP PHY */
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if (config->utmi)
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setbits_le32(&usbctlr->susp_ctrl, UTMIP_PHY_ENB);
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/*
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* TODO: where do we take the USB1 out of reset? The old code would
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* take USB3 out of reset, but not USB1. This code doesn't do either.
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*/
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}
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/* set up the USB controller with the parameters provided */
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static int init_usb_controller(struct fdt_usb *config,
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struct usb_ctlr *usbctlr, const u32 timing[])
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{
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u32 val;
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int loop_count;
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clock_enable(config->periph_id);
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/* Reset the usb controller */
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usbf_reset_controller(config, usbctlr);
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/* Stop crystal clock by setting UTMIP_PHY_XTAL_CLOCKEN low */
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clrbits_le32(&usbctlr->utmip_misc_cfg1, UTMIP_PHY_XTAL_CLOCKEN);
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/* Follow the crystal clock disable by >100ns delay */
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udelay(1);
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/*
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* To Use the A Session Valid for cable detection logic, VBUS_WAKEUP
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* mux must be switched to actually use a_sess_vld threshold.
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*/
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if (fdt_gpio_isvalid(&config->vbus_gpio)) {
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clrsetbits_le32(&usbctlr->usb1_legacy_ctrl,
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VBUS_SENSE_CTL_MASK,
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VBUS_SENSE_CTL_A_SESS_VLD << VBUS_SENSE_CTL_SHIFT);
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}
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/*
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* PLL Delay CONFIGURATION settings. The following parameters control
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* the bring up of the plls.
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*/
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val = readl(&usbctlr->utmip_misc_cfg1);
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clrsetbits_le32(&val, UTMIP_PLLU_STABLE_COUNT_MASK,
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timing[PARAM_STABLE_COUNT] << UTMIP_PLLU_STABLE_COUNT_SHIFT);
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clrsetbits_le32(&val, UTMIP_PLL_ACTIVE_DLY_COUNT_MASK,
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timing[PARAM_ACTIVE_DELAY_COUNT] <<
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UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT);
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writel(val, &usbctlr->utmip_misc_cfg1);
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/* Set PLL enable delay count and crystal frequency count */
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val = readl(&usbctlr->utmip_pll_cfg1);
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clrsetbits_le32(&val, UTMIP_PLLU_ENABLE_DLY_COUNT_MASK,
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timing[PARAM_ENABLE_DELAY_COUNT] <<
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UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT);
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clrsetbits_le32(&val, UTMIP_XTAL_FREQ_COUNT_MASK,
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timing[PARAM_XTAL_FREQ_COUNT] <<
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UTMIP_XTAL_FREQ_COUNT_SHIFT);
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writel(val, &usbctlr->utmip_pll_cfg1);
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/* Setting the tracking length time */
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clrsetbits_le32(&usbctlr->utmip_bias_cfg1,
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UTMIP_BIAS_PDTRK_COUNT_MASK,
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timing[PARAM_BIAS_TIME] << UTMIP_BIAS_PDTRK_COUNT_SHIFT);
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/* Program debounce time for VBUS to become valid */
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clrsetbits_le32(&usbctlr->utmip_debounce_cfg0,
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UTMIP_DEBOUNCE_CFG0_MASK,
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timing[PARAM_DEBOUNCE_A_TIME] << UTMIP_DEBOUNCE_CFG0_SHIFT);
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setbits_le32(&usbctlr->utmip_tx_cfg0, UTMIP_FS_PREAMBLE_J);
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/* Disable battery charge enabling bit */
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setbits_le32(&usbctlr->utmip_bat_chrg_cfg0, UTMIP_PD_CHRG);
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clrbits_le32(&usbctlr->utmip_xcvr_cfg0, UTMIP_XCVR_LSBIAS_SE);
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setbits_le32(&usbctlr->utmip_spare_cfg0, FUSE_SETUP_SEL);
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/*
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* Configure the UTMIP_IDLE_WAIT and UTMIP_ELASTIC_LIMIT
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* Setting these fields, together with default values of the
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* other fields, results in programming the registers below as
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* follows:
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* UTMIP_HSRX_CFG0 = 0x9168c000
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* UTMIP_HSRX_CFG1 = 0x13
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*/
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/* Set PLL enable delay count and Crystal frequency count */
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val = readl(&usbctlr->utmip_hsrx_cfg0);
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clrsetbits_le32(&val, UTMIP_IDLE_WAIT_MASK,
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utmip_idle_wait_delay << UTMIP_IDLE_WAIT_SHIFT);
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clrsetbits_le32(&val, UTMIP_ELASTIC_LIMIT_MASK,
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utmip_elastic_limit << UTMIP_ELASTIC_LIMIT_SHIFT);
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writel(val, &usbctlr->utmip_hsrx_cfg0);
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/* Configure the UTMIP_HS_SYNC_START_DLY */
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clrsetbits_le32(&usbctlr->utmip_hsrx_cfg1,
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UTMIP_HS_SYNC_START_DLY_MASK,
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utmip_hs_sync_start_delay << UTMIP_HS_SYNC_START_DLY_SHIFT);
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/* Preceed the crystal clock disable by >100ns delay. */
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udelay(1);
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/* Resuscitate crystal clock by setting UTMIP_PHY_XTAL_CLOCKEN */
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setbits_le32(&usbctlr->utmip_misc_cfg1, UTMIP_PHY_XTAL_CLOCKEN);
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/* Finished the per-controller init. */
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/* De-assert UTMIP_RESET to bring out of reset. */
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clrbits_le32(&usbctlr->susp_ctrl, UTMIP_RESET);
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/* Wait for the phy clock to become valid in 100 ms */
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for (loop_count = 100000; loop_count != 0; loop_count--) {
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if (readl(&usbctlr->susp_ctrl) & USB_PHY_CLK_VALID)
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break;
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udelay(1);
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}
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if (loop_count == 100000)
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return -1;
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return 0;
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}
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static void power_up_port(struct usb_ctlr *usbctlr)
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{
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/* Deassert power down state */
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clrbits_le32(&usbctlr->utmip_xcvr_cfg0, UTMIP_FORCE_PD_POWERDOWN |
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UTMIP_FORCE_PD2_POWERDOWN | UTMIP_FORCE_PDZI_POWERDOWN);
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clrbits_le32(&usbctlr->utmip_xcvr_cfg1, UTMIP_FORCE_PDDISC_POWERDOWN |
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UTMIP_FORCE_PDCHRP_POWERDOWN | UTMIP_FORCE_PDDR_POWERDOWN);
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}
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static void config_clock(const u32 timing[])
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{
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clock_start_pll(CLOCK_ID_USB,
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timing[PARAM_DIVM], timing[PARAM_DIVN], timing[PARAM_DIVP],
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timing[PARAM_CPCON], timing[PARAM_LFCON]);
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}
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/**
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* Add a new USB port to the list of available ports.
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*
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* @param config USB port configuration
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* @return 0 if ok, -1 if error (too many ports)
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*/
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static int add_port(struct fdt_usb *config, const u32 timing[])
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{
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struct usb_ctlr *usbctlr = config->reg;
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if (port_count == USB_PORTS_MAX) {
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debug("tegrausb: Cannot register more than %d ports\n",
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USB_PORTS_MAX);
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return -1;
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}
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if (init_usb_controller(config, usbctlr, timing)) {
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debug("tegrausb: Cannot init port\n");
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return -1;
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}
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if (config->utmi) {
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/* Disable ICUSB FS/LS transceiver */
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clrbits_le32(&usbctlr->icusb_ctrl, IC_ENB1);
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/* Select UTMI parallel interface */
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clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK,
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PTS_UTMI << PTS_SHIFT);
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clrbits_le32(&usbctlr->port_sc1, STS);
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power_up_port(usbctlr);
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}
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port[port_count++] = *config;
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return 0;
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}
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int tegrausb_start_port(unsigned portnum, u32 *hccr, u32 *hcor)
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{
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struct usb_ctlr *usbctlr;
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if (portnum >= port_count)
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return -1;
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tegrausb_stop_port();
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set_host_mode(&port[portnum]);
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usbctlr = port[portnum].reg;
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*hccr = (u32)&usbctlr->cap_length;
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*hcor = (u32)&usbctlr->usb_cmd;
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port_current = portnum;
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return 0;
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}
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int tegrausb_stop_port(void)
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{
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struct usb_ctlr *usbctlr;
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if (port_current == -1)
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return -1;
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usbctlr = port[port_current].reg;
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/* Stop controller */
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writel(0, &usbctlr->usb_cmd);
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udelay(1000);
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/* Initiate controller reset */
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writel(2, &usbctlr->usb_cmd);
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udelay(1000);
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port_current = -1;
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return 0;
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}
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int fdt_decode_usb(const void *blob, int node, unsigned osc_frequency_mhz,
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struct fdt_usb *config)
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{
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const char *phy, *mode;
|
||||
|
||||
config->reg = (struct usb_ctlr *)fdtdec_get_addr(blob, node, "reg");
|
||||
mode = fdt_getprop(blob, node, "dr_mode", NULL);
|
||||
if (mode) {
|
||||
if (0 == strcmp(mode, "host"))
|
||||
config->dr_mode = DR_MODE_HOST;
|
||||
else if (0 == strcmp(mode, "peripheral"))
|
||||
config->dr_mode = DR_MODE_DEVICE;
|
||||
else if (0 == strcmp(mode, "otg"))
|
||||
config->dr_mode = DR_MODE_OTG;
|
||||
else {
|
||||
debug("%s: Cannot decode dr_mode '%s'\n", __func__,
|
||||
mode);
|
||||
return -FDT_ERR_NOTFOUND;
|
||||
}
|
||||
} else {
|
||||
config->dr_mode = DR_MODE_HOST;
|
||||
}
|
||||
|
||||
phy = fdt_getprop(blob, node, "phy_type", NULL);
|
||||
config->utmi = phy && 0 == strcmp("utmi", phy);
|
||||
config->enabled = fdtdec_get_is_enabled(blob, node);
|
||||
config->has_legacy_mode = fdtdec_get_bool(blob, node,
|
||||
"nvidia,has-legacy-mode");
|
||||
config->periph_id = clock_decode_periph_id(blob, node);
|
||||
if (config->periph_id == PERIPH_ID_NONE) {
|
||||
debug("%s: Missing/invalid peripheral ID\n", __func__);
|
||||
return -FDT_ERR_NOTFOUND;
|
||||
}
|
||||
fdtdec_decode_gpio(blob, node, "nvidia,vbus-gpio", &config->vbus_gpio);
|
||||
debug("enabled=%d, legacy_mode=%d, utmi=%d, periph_id=%d, vbus=%d, "
|
||||
"dr_mode=%d\n", config->enabled, config->has_legacy_mode,
|
||||
config->utmi, config->periph_id, config->vbus_gpio.gpio,
|
||||
config->dr_mode);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_usb_init(const void *blob)
|
||||
{
|
||||
struct fdt_usb config;
|
||||
unsigned osc_freq = clock_get_rate(CLOCK_ID_OSC);
|
||||
enum clock_osc_freq freq;
|
||||
int node_list[USB_PORTS_MAX];
|
||||
int node, count, i;
|
||||
|
||||
/* Set up the USB clocks correctly based on our oscillator frequency */
|
||||
freq = clock_get_osc_freq();
|
||||
config_clock(usb_pll[freq]);
|
||||
|
||||
/* count may return <0 on error */
|
||||
count = fdtdec_find_aliases_for_id(blob, "usb",
|
||||
COMPAT_NVIDIA_TEGRA20_USB, node_list, USB_PORTS_MAX);
|
||||
for (i = 0; i < count; i++) {
|
||||
debug("USB %d: ", i);
|
||||
node = node_list[i];
|
||||
if (!node)
|
||||
continue;
|
||||
if (fdt_decode_usb(blob, node, osc_freq, &config)) {
|
||||
debug("Cannot decode USB node %s\n",
|
||||
fdt_get_name(blob, node, NULL));
|
||||
return -1;
|
||||
}
|
||||
|
||||
if (add_port(&config, usb_pll[freq]))
|
||||
return -1;
|
||||
set_host_mode(&config);
|
||||
}
|
||||
port_current = -1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
@ -41,6 +41,8 @@
|
||||
#define TEGRA2_SPI_BASE (NV_PA_APB_MISC_BASE + 0xC380)
|
||||
#define NV_PA_PMC_BASE 0x7000E400
|
||||
#define NV_PA_CSITE_BASE 0x70040000
|
||||
#define TEGRA_USB1_BASE 0xC5000000
|
||||
#define TEGRA_USB3_BASE 0xC5008000
|
||||
|
||||
#define TEGRA2_SDRC_CS0 NV_PA_SDRAM_BASE
|
||||
#define LOW_LEVEL_SRAM_STACK 0x4000FFFC
|
||||
|
||||
252
arch/arm/include/asm/arch-tegra2/usb.h
Normal file
252
arch/arm/include/asm/arch-tegra2/usb.h
Normal file
@ -0,0 +1,252 @@
|
||||
/*
|
||||
* Copyright (c) 2011 The Chromium OS Authors.
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef _TEGRA_USB_H_
|
||||
#define _TEGRA_USB_H_
|
||||
|
||||
|
||||
/* USB Controller (USBx_CONTROLLER_) regs */
|
||||
struct usb_ctlr {
|
||||
/* 0x000 */
|
||||
uint id;
|
||||
uint reserved0;
|
||||
uint host;
|
||||
uint device;
|
||||
|
||||
/* 0x010 */
|
||||
uint txbuf;
|
||||
uint rxbuf;
|
||||
uint reserved1[2];
|
||||
|
||||
/* 0x020 */
|
||||
uint reserved2[56];
|
||||
|
||||
/* 0x100 */
|
||||
u16 cap_length;
|
||||
u16 hci_version;
|
||||
uint hcs_params;
|
||||
uint hcc_params;
|
||||
uint reserved3[5];
|
||||
|
||||
/* 0x120 */
|
||||
uint dci_version;
|
||||
uint dcc_params;
|
||||
uint reserved4[6];
|
||||
|
||||
/* 0x140 */
|
||||
uint usb_cmd;
|
||||
uint usb_sts;
|
||||
uint usb_intr;
|
||||
uint frindex;
|
||||
|
||||
/* 0x150 */
|
||||
uint reserved5;
|
||||
uint periodic_list_base;
|
||||
uint async_list_addr;
|
||||
uint async_tt_sts;
|
||||
|
||||
/* 0x160 */
|
||||
uint burst_size;
|
||||
uint tx_fill_tuning;
|
||||
uint reserved6; /* is this port_sc1 on some controllers? */
|
||||
uint icusb_ctrl;
|
||||
|
||||
/* 0x170 */
|
||||
uint ulpi_viewport;
|
||||
uint reserved7;
|
||||
uint endpt_nak;
|
||||
uint endpt_nak_enable;
|
||||
|
||||
/* 0x180 */
|
||||
uint reserved;
|
||||
uint port_sc1;
|
||||
uint reserved8[6];
|
||||
|
||||
/* 0x1a0 */
|
||||
uint reserved9;
|
||||
uint otgsc;
|
||||
uint usb_mode;
|
||||
uint endpt_setup_stat;
|
||||
|
||||
/* 0x1b0 */
|
||||
uint reserved10[20];
|
||||
|
||||
/* 0x200 */
|
||||
uint reserved11[0x80];
|
||||
|
||||
/* 0x400 */
|
||||
uint susp_ctrl;
|
||||
uint phy_vbus_sensors;
|
||||
uint phy_vbus_wakeup_id;
|
||||
uint phy_alt_vbus_sys;
|
||||
|
||||
/* 0x410 */
|
||||
uint usb1_legacy_ctrl;
|
||||
uint reserved12[3];
|
||||
|
||||
/* 0x420 */
|
||||
uint reserved13[56];
|
||||
|
||||
/* 0x500 */
|
||||
uint reserved14[64 * 3];
|
||||
|
||||
/* 0x800 */
|
||||
uint utmip_pll_cfg0;
|
||||
uint utmip_pll_cfg1;
|
||||
uint utmip_xcvr_cfg0;
|
||||
uint utmip_bias_cfg0;
|
||||
|
||||
/* 0x810 */
|
||||
uint utmip_hsrx_cfg0;
|
||||
uint utmip_hsrx_cfg1;
|
||||
uint utmip_fslsrx_cfg0;
|
||||
uint utmip_fslsrx_cfg1;
|
||||
|
||||
/* 0x820 */
|
||||
uint utmip_tx_cfg0;
|
||||
uint utmip_misc_cfg0;
|
||||
uint utmip_misc_cfg1;
|
||||
uint utmip_debounce_cfg0;
|
||||
|
||||
/* 0x830 */
|
||||
uint utmip_bat_chrg_cfg0;
|
||||
uint utmip_spare_cfg0;
|
||||
uint utmip_xcvr_cfg1;
|
||||
uint utmip_bias_cfg1;
|
||||
};
|
||||
|
||||
|
||||
/* USB1_LEGACY_CTRL */
|
||||
#define USB1_NO_LEGACY_MODE 1
|
||||
|
||||
#define VBUS_SENSE_CTL_SHIFT 1
|
||||
#define VBUS_SENSE_CTL_MASK (3 << VBUS_SENSE_CTL_SHIFT)
|
||||
#define VBUS_SENSE_CTL_VBUS_WAKEUP 0
|
||||
#define VBUS_SENSE_CTL_AB_SESS_VLD_OR_VBUS_WAKEUP 1
|
||||
#define VBUS_SENSE_CTL_AB_SESS_VLD 2
|
||||
#define VBUS_SENSE_CTL_A_SESS_VLD 3
|
||||
|
||||
/* USBx_IF_USB_SUSP_CTRL_0 */
|
||||
#define UTMIP_PHY_ENB (1 << 12)
|
||||
#define UTMIP_RESET (1 << 11)
|
||||
#define USB_PHY_CLK_VALID (1 << 7)
|
||||
|
||||
/* USBx_UTMIP_MISC_CFG1 */
|
||||
#define UTMIP_PLLU_STABLE_COUNT_SHIFT 6
|
||||
#define UTMIP_PLLU_STABLE_COUNT_MASK \
|
||||
(0xfff << UTMIP_PLLU_STABLE_COUNT_SHIFT)
|
||||
#define UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT 18
|
||||
#define UTMIP_PLL_ACTIVE_DLY_COUNT_MASK \
|
||||
(0x1f << UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT)
|
||||
#define UTMIP_PHY_XTAL_CLOCKEN (1 << 30)
|
||||
|
||||
/* USBx_UTMIP_PLL_CFG1_0 */
|
||||
#define UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT 27
|
||||
#define UTMIP_PLLU_ENABLE_DLY_COUNT_MASK \
|
||||
(0xf << UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT)
|
||||
#define UTMIP_XTAL_FREQ_COUNT_SHIFT 0
|
||||
#define UTMIP_XTAL_FREQ_COUNT_MASK 0xfff
|
||||
|
||||
/* USBx_UTMIP_BIAS_CFG1_0 */
|
||||
#define UTMIP_BIAS_PDTRK_COUNT_SHIFT 3
|
||||
#define UTMIP_BIAS_PDTRK_COUNT_MASK \
|
||||
(0x1f << UTMIP_BIAS_PDTRK_COUNT_SHIFT)
|
||||
|
||||
#define UTMIP_DEBOUNCE_CFG0_SHIFT 0
|
||||
#define UTMIP_DEBOUNCE_CFG0_MASK 0xffff
|
||||
|
||||
/* USBx_UTMIP_TX_CFG0_0 */
|
||||
#define UTMIP_FS_PREAMBLE_J (1 << 19)
|
||||
|
||||
/* USBx_UTMIP_BAT_CHRG_CFG0_0 */
|
||||
#define UTMIP_PD_CHRG 1
|
||||
|
||||
/* USBx_UTMIP_XCVR_CFG0_0 */
|
||||
#define UTMIP_XCVR_LSBIAS_SE (1 << 21)
|
||||
|
||||
/* USBx_UTMIP_SPARE_CFG0_0 */
|
||||
#define FUSE_SETUP_SEL (1 << 3)
|
||||
|
||||
/* USBx_UTMIP_HSRX_CFG0_0 */
|
||||
#define UTMIP_IDLE_WAIT_SHIFT 15
|
||||
#define UTMIP_IDLE_WAIT_MASK (0x1f << UTMIP_IDLE_WAIT_SHIFT)
|
||||
#define UTMIP_ELASTIC_LIMIT_SHIFT 10
|
||||
#define UTMIP_ELASTIC_LIMIT_MASK \
|
||||
(0x1f << UTMIP_ELASTIC_LIMIT_SHIFT)
|
||||
|
||||
/* USBx_UTMIP_HSRX_CFG0_1 */
|
||||
#define UTMIP_HS_SYNC_START_DLY_SHIFT 1
|
||||
#define UTMIP_HS_SYNC_START_DLY_MASK \
|
||||
(0xf << UTMIP_HS_SYNC_START_DLY_SHIFT)
|
||||
|
||||
/* USBx_CONTROLLER_2_USB2D_ICUSB_CTRL_0 */
|
||||
#define IC_ENB1 (1 << 3)
|
||||
|
||||
/* SB2_CONTROLLER_2_USB2D_PORTSC1_0 */
|
||||
#define PTS_SHIFT 30
|
||||
#define PTS_MASK (3U << PTS_SHIFT)
|
||||
#define PTS_UTMI 0
|
||||
#define PTS_RESERVED 1
|
||||
#define PTS_ULP 2
|
||||
#define PTS_ICUSB_SER 3
|
||||
|
||||
#define STS (1 << 29)
|
||||
|
||||
/* USBx_UTMIP_XCVR_CFG0_0 */
|
||||
#define UTMIP_FORCE_PD_POWERDOWN (1 << 14)
|
||||
#define UTMIP_FORCE_PD2_POWERDOWN (1 << 16)
|
||||
#define UTMIP_FORCE_PDZI_POWERDOWN (1 << 18)
|
||||
|
||||
/* USBx_UTMIP_XCVR_CFG1_0 */
|
||||
#define UTMIP_FORCE_PDDISC_POWERDOWN (1 << 0)
|
||||
#define UTMIP_FORCE_PDCHRP_POWERDOWN (1 << 2)
|
||||
#define UTMIP_FORCE_PDDR_POWERDOWN (1 << 4)
|
||||
|
||||
/* USB3_IF_USB_PHY_VBUS_SENSORS_0 */
|
||||
#define VBUS_VLD_STS (1 << 26)
|
||||
|
||||
|
||||
/* Change the USB host port into host mode */
|
||||
void usb_set_host_mode(void);
|
||||
|
||||
/* Setup USB on the board */
|
||||
int board_usb_init(const void *blob);
|
||||
|
||||
/**
|
||||
* Start up the given port number (ports are numbered from 0 on each board).
|
||||
* This returns values for the appropriate hccr and hcor addresses to use for
|
||||
* USB EHCI operations.
|
||||
*
|
||||
* @param portnum port number to start
|
||||
* @param hccr returns start address of EHCI HCCR registers
|
||||
* @param hcor returns start address of EHCI HCOR registers
|
||||
* @return 0 if ok, -1 on error (generally invalid port number)
|
||||
*/
|
||||
int tegrausb_start_port(unsigned portnum, u32 *hccr, u32 *hcor);
|
||||
|
||||
/**
|
||||
* Stop the current port
|
||||
*
|
||||
* @return 0 if ok, -1 if no port was active
|
||||
*/
|
||||
int tegrausb_stop_port(void);
|
||||
|
||||
#endif /* _TEGRA_USB_H_ */
|
||||
@ -50,6 +50,7 @@ COBJS-$(CONFIG_USB_EHCI_PPC4XX) += ehci-ppc4xx.o
|
||||
COBJS-$(CONFIG_USB_EHCI_IXP4XX) += ehci-ixp.o
|
||||
COBJS-$(CONFIG_USB_EHCI_MARVELL) += ehci-marvell.o
|
||||
COBJS-$(CONFIG_USB_EHCI_PCI) += ehci-pci.o
|
||||
COBJS-$(CONFIG_USB_EHCI_TEGRA) += ehci-tegra.o
|
||||
COBJS-$(CONFIG_USB_EHCI_VCT) += ehci-vct.o
|
||||
|
||||
COBJS := $(COBJS-y)
|
||||
|
||||
62
drivers/usb/host/ehci-tegra.c
Normal file
62
drivers/usb/host/ehci-tegra.c
Normal file
@ -0,0 +1,62 @@
|
||||
/*
|
||||
* Copyright (c) 2009 NVIDIA Corporation
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <usb.h>
|
||||
|
||||
#include "ehci.h"
|
||||
#include "ehci-core.h"
|
||||
|
||||
#include <asm/errno.h>
|
||||
#include <asm/arch/usb.h>
|
||||
|
||||
|
||||
/*
|
||||
* Create the appropriate control structures to manage
|
||||
* a new EHCI host controller.
|
||||
*/
|
||||
int ehci_hcd_init(void)
|
||||
{
|
||||
u32 our_hccr, our_hcor;
|
||||
|
||||
/*
|
||||
* Select the first port, as we don't have a way of selecting others
|
||||
* yet
|
||||
*/
|
||||
if (tegrausb_start_port(0, &our_hccr, &our_hcor))
|
||||
return -1;
|
||||
|
||||
hccr = (struct ehci_hccr *)our_hccr;
|
||||
hcor = (struct ehci_hcor *)our_hcor;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Destroy the appropriate control structures corresponding
|
||||
* the the EHCI host controller.
|
||||
*/
|
||||
int ehci_hcd_stop(void)
|
||||
{
|
||||
tegrausb_stop_port();
|
||||
return 0;
|
||||
}
|
||||
@ -57,6 +57,7 @@ struct fdt_memory {
|
||||
*/
|
||||
enum fdt_compat_id {
|
||||
COMPAT_UNKNOWN,
|
||||
COMPAT_NVIDIA_TEGRA20_USB, /* Tegra2 USB port */
|
||||
|
||||
COMPAT_COUNT,
|
||||
};
|
||||
|
||||
@ -37,6 +37,7 @@ DECLARE_GLOBAL_DATA_PTR;
|
||||
#define COMPAT(id, name) name
|
||||
static const char * const compat_names[COMPAT_COUNT] = {
|
||||
COMPAT(UNKNOWN, "<none>"),
|
||||
COMPAT(NVIDIA_TEGRA20_USB, "nvidia,tegra20-ehci"),
|
||||
};
|
||||
|
||||
const char *fdtdec_get_compatible(enum fdt_compat_id id)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user