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watchdog: omap_wdt: improve watchdog reset path

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Remove busy looping during watchdog reset.
Each polling of W_PEND_WTGR bit ("finish posted
write") after watchdog reset takes 120-140us
on BeagleBone Black board. Current U-Boot code
has watchdog resets in random places and often
there is situation when watchdog is reset
few times in a row in nested functions.
This adds extra delays and slows the whole system.

Instead of polling W_PEND_WTGR bit, we skip
watchdog reset if the bit is set. Anyway, watchdog
is in the middle of reset *right now*, so we can
just return.

This noticeably increases performance of the
system. Below are some measurements on BBB:
 - DFU upload over USB                 15% faster
 - fastboot image upload               3x times faster
 - USB ep0 transfers with 4k packets   20% faster

Signed-off-by: Ruslan Bilovol <ruslan.bilovol@gmail.com>
Tested-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Tested-by: Alex Kiernan <alex.kiernan@gmail.com>
This commit is contained in:
Ruslan Bilovol 2018-03-01 03:15:48 +02:00 committed by Tom Rini
parent fc228dc96c
commit 87c692cbc1
1 changed files with 15 additions and 6 deletions
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21
drivers/watchdog/omap_wdt.c
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@ -53,16 +53,25 @@ void hw_watchdog_reset(void)
{
struct wd_timer *wdt = (struct wd_timer *)WDT_BASE;
/* wait for posted write to complete */
while ((readl(&wdt->wdtwwps)) & WDT_WWPS_PEND_WTGR)
;
/*
* Somebody just triggered watchdog reset and write to WTGR register
* is in progress. It is resetting right now, no need to trigger it
* again
*/
if ((readl(&wdt->wdtwwps)) & WDT_WWPS_PEND_WTGR)
return;
wdt_trgr_pattern = ~wdt_trgr_pattern;
writel(wdt_trgr_pattern, &wdt->wdtwtgr);
/* wait for posted write to complete */
while ((readl(&wdt->wdtwwps) & WDT_WWPS_PEND_WTGR))
;
/*
* Don't wait for posted write to complete, i.e. don't check
* WDT_WWPS_PEND_WTGR bit in WWPS register. There is no writes to
* WTGR register outside of this func, and if entering it
* we see WDT_WWPS_PEND_WTGR bit set, it means watchdog reset
* was just triggered. This prevents us from wasting time in busy
* polling of WDT_WWPS_PEND_WTGR bit.
*/
}
static int omap_wdt_set_timeout(unsigned int timeout)