Convert CONFIG_SYS_NAND_U_BOOT_LOCATIONS et al to Kconfig
This converts the following to Kconfig: CONFIG_SYS_NAND_U_BOOT_LOCATIONS CONFIG_SYS_NAND_U_BOOT_OFFS Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
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53f06134ed
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3
README
3
README
@ -2074,9 +2074,6 @@ The following options need to be configured:
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Defines the size and behavior of the NAND that SPL uses
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to read U-Boot
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CONFIG_SYS_NAND_U_BOOT_OFFS
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Location in NAND to read U-Boot from
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CONFIG_SYS_NAND_U_BOOT_DST
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Location in memory to load U-Boot to
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@ -65,7 +65,7 @@ CONFIG_SYS_NAND_PAGE_COUNT=0x40
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CONFIG_SYS_NAND_PAGE_SIZE=0x800
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CONFIG_SYS_NAND_OOBSIZE=0x40
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CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
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CONFIG_SYS_NAND_U_BOOT_OFFS=0x00080000
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CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000
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CONFIG_PHY_ADDR_ENABLE=y
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CONFIG_PHY_ATHEROS=y
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CONFIG_PHY_SMSC=y
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@ -68,6 +68,8 @@ CONFIG_SYS_NAND_ONFI_DETECTION=y
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CONFIG_SYS_NAND_PAGE_COUNT=0x40
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CONFIG_SYS_NAND_PAGE_SIZE=0x800
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CONFIG_SYS_NAND_OOBSIZE=0x40
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CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
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CONFIG_SYS_NAND_U_BOOT_OFFS=0xc0000
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CONFIG_DM_SPI_FLASH=y
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CONFIG_SF_DEFAULT_SPEED=24000000
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CONFIG_SPI_FLASH_WINBOND=y
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@ -65,6 +65,8 @@ CONFIG_MTD_RAW_NAND=y
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CONFIG_SYS_NAND_ONFI_DETECTION=y
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CONFIG_SYS_NAND_PAGE_SIZE=0x800
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CONFIG_SYS_NAND_OOBSIZE=0x40
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CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
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CONFIG_SYS_NAND_U_BOOT_OFFS=0xc0000
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# CONFIG_SPL_NAND_AM33XX_BCH is not set
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CONFIG_DM_SPI_FLASH=y
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CONFIG_SF_DEFAULT_SPEED=24000000
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@ -59,6 +59,8 @@ CONFIG_MTD_RAW_NAND=y
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CONFIG_SYS_NAND_ONFI_DETECTION=y
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CONFIG_SYS_NAND_PAGE_SIZE=0x800
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CONFIG_SYS_NAND_OOBSIZE=0x40
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CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
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CONFIG_SYS_NAND_U_BOOT_OFFS=0xc0000
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CONFIG_DM_SPI_FLASH=y
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CONFIG_SF_DEFAULT_SPEED=24000000
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CONFIG_SPI_FLASH_WINBOND=y
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@ -61,6 +61,8 @@ CONFIG_MTD_RAW_NAND=y
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CONFIG_SYS_NAND_ONFI_DETECTION=y
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CONFIG_SYS_NAND_PAGE_SIZE=0x800
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CONFIG_SYS_NAND_OOBSIZE=0x40
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CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
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CONFIG_SYS_NAND_U_BOOT_OFFS=0xc0000
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CONFIG_DM_SPI_FLASH=y
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CONFIG_SF_DEFAULT_SPEED=24000000
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CONFIG_SPI_FLASH_WINBOND=y
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@ -65,6 +65,8 @@ CONFIG_SYS_NAND_ONFI_DETECTION=y
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CONFIG_SYS_NAND_PAGE_COUNT=0x40
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CONFIG_SYS_NAND_PAGE_SIZE=0x1000
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CONFIG_SYS_NAND_OOBSIZE=0xe0
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CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
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CONFIG_SYS_NAND_U_BOOT_OFFS=0x180000
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CONFIG_SF_DEFAULT_SPEED=48000000
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CONFIG_SPI_FLASH_MACRONIX=y
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CONFIG_PHY_GIGE=y
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@ -52,6 +52,8 @@ CONFIG_SYS_NAND_ONFI_DETECTION=y
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CONFIG_SYS_NAND_PAGE_COUNT=0x40
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CONFIG_SYS_NAND_PAGE_SIZE=0x1000
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CONFIG_SYS_NAND_OOBSIZE=0xe0
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CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
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CONFIG_SYS_NAND_U_BOOT_OFFS=0x180000
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CONFIG_SF_DEFAULT_SPEED=48000000
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CONFIG_SPI_FLASH_MACRONIX=y
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CONFIG_PHY_GIGE=y
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@ -68,6 +68,8 @@ CONFIG_SYS_NAND_ONFI_DETECTION=y
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CONFIG_SYS_NAND_PAGE_COUNT=0x40
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CONFIG_SYS_NAND_PAGE_SIZE=0x1000
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CONFIG_SYS_NAND_OOBSIZE=0xe0
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CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
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CONFIG_SYS_NAND_U_BOOT_OFFS=0x180000
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CONFIG_SF_DEFAULT_SPEED=48000000
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CONFIG_SPI_FLASH_MACRONIX=y
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CONFIG_PHY_GIGE=y
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@ -70,6 +70,8 @@ CONFIG_SYS_NAND_ONFI_DETECTION=y
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CONFIG_SYS_NAND_PAGE_COUNT=0x40
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CONFIG_SYS_NAND_PAGE_SIZE=0x1000
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CONFIG_SYS_NAND_OOBSIZE=0xe0
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CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
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CONFIG_SYS_NAND_U_BOOT_OFFS=0x180000
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CONFIG_SF_DEFAULT_SPEED=48000000
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CONFIG_SPI_FLASH_MACRONIX=y
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CONFIG_PHY_GIGE=y
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@ -77,6 +77,8 @@ CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
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CONFIG_SYS_NAND_PAGE_COUNT=0x40
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CONFIG_SYS_NAND_PAGE_SIZE=0x800
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CONFIG_SYS_NAND_OOBSIZE=0x40
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CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
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CONFIG_SYS_NAND_U_BOOT_OFFS=0x20000
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CONFIG_DM_SPI_FLASH=y
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CONFIG_SPI_FLASH_STMICRO=y
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CONFIG_PHYLIB=y
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@ -58,6 +58,8 @@ CONFIG_SYS_NAND_ONFI_DETECTION=y
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CONFIG_SYS_NAND_PAGE_COUNT=0x40
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CONFIG_SYS_NAND_PAGE_SIZE=0x800
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CONFIG_SYS_NAND_OOBSIZE=0x40
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CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
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CONFIG_SYS_NAND_U_BOOT_OFFS=0xc0000
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CONFIG_PHY_SMSC=y
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CONFIG_DM_ETH=y
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CONFIG_MII=y
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@ -66,6 +66,8 @@ CONFIG_SYS_NAND_ONFI_DETECTION=y
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CONFIG_SYS_NAND_PAGE_COUNT=0x40
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CONFIG_SYS_NAND_PAGE_SIZE=0x800
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CONFIG_SYS_NAND_OOBSIZE=0x40
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CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
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CONFIG_SYS_NAND_U_BOOT_OFFS=0x200000
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CONFIG_PHY_ATHEROS=y
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CONFIG_MII=y
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CONFIG_DRIVER_TI_CPSW=y
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@ -65,6 +65,8 @@ CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
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CONFIG_SYS_NAND_PAGE_COUNT=0x40
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CONFIG_SYS_NAND_PAGE_SIZE=0x800
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CONFIG_SYS_NAND_OOBSIZE=0x40
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CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
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CONFIG_SYS_NAND_U_BOOT_OFFS=0x20000
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CONFIG_PHYLIB=y
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CONFIG_ATMEL_USART=y
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CONFIG_USB=y
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@ -58,6 +58,8 @@ CONFIG_SYS_NAND_PAGE_COUNT=0x40
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CONFIG_SYS_NAND_PAGE_SIZE=0x800
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CONFIG_SYS_NAND_OOBSIZE=0x40
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# CONFIG_SYS_NAND_5_ADDR_CYCLE is not set
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CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
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CONFIG_SYS_NAND_U_BOOT_OFFS=0x40000
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CONFIG_PHYLIB=y
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CONFIG_PHY_ADDR_ENABLE=y
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CONFIG_PHY_ADDR=31
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@ -46,5 +46,7 @@ CONFIG_SYS_NAND_PAGE_COUNT=0x40
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CONFIG_SYS_NAND_PAGE_SIZE=0x800
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CONFIG_SYS_NAND_OOBSIZE=0x40
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CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
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CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
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CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000
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CONFIG_CONS_INDEX=3
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CONFIG_OF_LIBFDT=y
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@ -98,6 +98,8 @@ CONFIG_SYS_NAND_PAGE_COUNT=0x40
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CONFIG_SYS_NAND_PAGE_SIZE=0x800
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CONFIG_SYS_NAND_OOBSIZE=0x40
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CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
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CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
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CONFIG_SYS_NAND_U_BOOT_OFFS=0x140000
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CONFIG_DM_SPI_FLASH=y
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CONFIG_SF_DEFAULT_MODE=0
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CONFIG_SF_DEFAULT_SPEED=76800000
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@ -99,6 +99,8 @@ CONFIG_SYS_NAND_ONFI_DETECTION=y
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CONFIG_SYS_NAND_PAGE_SIZE=0x800
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CONFIG_SYS_NAND_OOBSIZE=0x40
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CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
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CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
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CONFIG_SYS_NAND_U_BOOT_OFFS=0x140000
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CONFIG_DM_SPI_FLASH=y
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CONFIG_SF_DEFAULT_MODE=0
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CONFIG_SF_DEFAULT_SPEED=76800000
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@ -89,6 +89,8 @@ CONFIG_SYS_NAND_ONFI_DETECTION=y
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CONFIG_SYS_NAND_PAGE_COUNT=0x40
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CONFIG_SYS_NAND_PAGE_SIZE=0x800
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CONFIG_SYS_NAND_OOBSIZE=0x40
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CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
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CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000
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CONFIG_DM_SPI_FLASH=y
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CONFIG_SPI_FLASH_WINBOND=y
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CONFIG_MTD_UBI_FASTMAP=y
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@ -90,6 +90,8 @@ CONFIG_SYS_NAND_ONFI_DETECTION=y
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CONFIG_SYS_NAND_PAGE_COUNT=0x80
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CONFIG_SYS_NAND_PAGE_SIZE=0x1000
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CONFIG_SYS_NAND_OOBSIZE=0xe0
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CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
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CONFIG_SYS_NAND_U_BOOT_OFFS=0x200000
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CONFIG_DM_SPI_FLASH=y
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CONFIG_SPI_FLASH_WINBOND=y
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CONFIG_MTD_UBI_FASTMAP=y
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@ -91,6 +91,8 @@ CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
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CONFIG_SYS_NAND_PAGE_COUNT=0x40
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CONFIG_SYS_NAND_PAGE_SIZE=0x800
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CONFIG_SYS_NAND_OOBSIZE=0x40
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CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
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CONFIG_SYS_NAND_U_BOOT_OFFS=0x40000
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CONFIG_DM_ETH=y
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CONFIG_MACB=y
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CONFIG_PINCTRL=y
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@ -100,6 +100,8 @@ CONFIG_DM_MTD=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_NAND_MXS=y
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CONFIG_NAND_MXS_DT=y
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CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
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CONFIG_SYS_NAND_U_BOOT_OFFS=0xe00000
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CONFIG_PHYLIB=y
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CONFIG_DM_ETH=y
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CONFIG_DM_MDIO=y
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@ -52,6 +52,8 @@ CONFIG_MTD=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_NAND_MXS=y
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CONFIG_SYS_NAND_ONFI_DETECTION=y
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CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
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CONFIG_SYS_NAND_U_BOOT_OFFS=0x200000
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CONFIG_PHYLIB=y
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CONFIG_PHY_SMSC=y
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CONFIG_FEC_MXC=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_NAND_MXS=y
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CONFIG_SYS_NAND_ONFI_DETECTION=y
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CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
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CONFIG_SYS_NAND_U_BOOT_OFFS=0x200000
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CONFIG_PHYLIB=y
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CONFIG_PHY_SMSC=y
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CONFIG_FEC_MXC=y
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@ -82,6 +82,8 @@ CONFIG_SYS_NAND_USE_FLASH_BBT=y
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CONFIG_NAND_MXS=y
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CONFIG_NAND_MXS_DT=y
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CONFIG_SYS_NAND_ONFI_DETECTION=y
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CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
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CONFIG_SYS_NAND_U_BOOT_OFFS=0x200000
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CONFIG_PHYLIB=y
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CONFIG_PHY_ATHEROS=y
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CONFIG_FEC_MXC=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_NAND_MXS=y
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CONFIG_SYS_NAND_ONFI_DETECTION=y
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CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
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CONFIG_SYS_NAND_U_BOOT_OFFS=0x200000
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CONFIG_PHYLIB=y
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CONFIG_PHY_SMSC=y
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CONFIG_FEC_MXC=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_NAND_MXS=y
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CONFIG_SYS_NAND_ONFI_DETECTION=y
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CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
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CONFIG_SYS_NAND_U_BOOT_OFFS=0x200000
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CONFIG_PHYLIB=y
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CONFIG_PHY_SMSC=y
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CONFIG_FEC_MXC=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_NAND_MXS=y
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CONFIG_SYS_NAND_ONFI_DETECTION=y
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CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
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CONFIG_SYS_NAND_U_BOOT_OFFS=0x200000
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CONFIG_PHYLIB=y
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CONFIG_PHY_SMSC=y
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CONFIG_FEC_MXC=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_NAND_MXS=y
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CONFIG_SYS_NAND_ONFI_DETECTION=y
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CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
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CONFIG_SYS_NAND_U_BOOT_OFFS=0x200000
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CONFIG_PHYLIB=y
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CONFIG_PHY_SMSC=y
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CONFIG_FEC_MXC=y
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CONFIG_NAND_FSL_IFC=y
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CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
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CONFIG_SYS_NAND_ONFI_DETECTION=y
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CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
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CONFIG_SYS_NAND_U_BOOT_OFFS=0x1c000
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CONFIG_PHY_REALTEK=y
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CONFIG_PHY_GIGE=y
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CONFIG_E1000=y
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CONFIG_NAND_FSL_IFC=y
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CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
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CONFIG_SYS_NAND_ONFI_DETECTION=y
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CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
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CONFIG_SYS_NAND_U_BOOT_OFFS=0x20000
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CONFIG_SF_DEFAULT_BUS=1
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CONFIG_PHYLIB=y
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CONFIG_PHYLIB_10G=y
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CONFIG_NAND_FSL_IFC=y
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CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
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CONFIG_SYS_NAND_ONFI_DETECTION=y
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CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
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CONFIG_SYS_NAND_U_BOOT_OFFS=0x20000
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CONFIG_SF_DEFAULT_BUS=1
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CONFIG_PHYLIB=y
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CONFIG_PHY_AQUANTIA=y
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CONFIG_NAND_FSL_IFC=y
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CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
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CONFIG_SYS_NAND_ONFI_DETECTION=y
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CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
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CONFIG_SYS_NAND_U_BOOT_OFFS=0x20000
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CONFIG_SF_DEFAULT_BUS=1
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CONFIG_PHYLIB=y
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CONFIG_PHY_AQUANTIA=y
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@ -73,6 +73,8 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
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CONFIG_SYS_FLASH_CFI=y
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CONFIG_NAND_FSL_IFC=y
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CONFIG_SYS_NAND_ONFI_DETECTION=y
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CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
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CONFIG_SYS_NAND_U_BOOT_OFFS=0x40000
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CONFIG_SF_DEFAULT_BUS=1
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CONFIG_PHYLIB=y
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CONFIG_PHYLIB_10G=y
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CONFIG_NAND_FSL_IFC=y
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CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
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CONFIG_SYS_NAND_ONFI_DETECTION=y
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CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
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CONFIG_SYS_NAND_U_BOOT_OFFS=0x40000
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CONFIG_DM_SPI_FLASH=y
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# CONFIG_SPI_FLASH_BAR is not set
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CONFIG_PHYLIB=y
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CONFIG_NAND_FSL_IFC=y
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CONFIG_SYS_NAND_BLOCK_SIZE=0x80000
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CONFIG_SYS_NAND_ONFI_DETECTION=y
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CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
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CONFIG_SYS_NAND_U_BOOT_OFFS=0x100000
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CONFIG_PHYLIB=y
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CONFIG_PHY_AQUANTIA=y
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CONFIG_PHY_CORTINA=y
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CONFIG_SYS_NAND_PAGE_COUNT=0x40
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CONFIG_SYS_NAND_PAGE_SIZE=0x800
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CONFIG_SYS_NAND_OOBSIZE=0x40
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CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
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CONFIG_SYS_NAND_U_BOOT_OFFS=0x8000
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CONFIG_PHYLIB=y
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CONFIG_PHY_MICREL=y
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CONFIG_PHY_MICREL_KSZ8XXX=y
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@ -89,6 +89,8 @@ CONFIG_SYS_NAND_ONFI_DETECTION=y
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CONFIG_SYS_NAND_PAGE_COUNT=0x40
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CONFIG_SYS_NAND_PAGE_SIZE=0x800
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CONFIG_SYS_NAND_OOBSIZE=0x40
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CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
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CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000
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CONFIG_DM_SPI_FLASH=y
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CONFIG_SPI_FLASH_WINBOND=y
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CONFIG_MTD_UBI_FASTMAP=y
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@ -89,6 +89,8 @@ CONFIG_SYS_NAND_ONFI_DETECTION=y
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CONFIG_SYS_NAND_PAGE_COUNT=0x40
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CONFIG_SYS_NAND_PAGE_SIZE=0x800
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CONFIG_SYS_NAND_OOBSIZE=0x40
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CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
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CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000
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CONFIG_DM_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
CONFIG_MTD_UBI_FASTMAP=y
|
||||
|
@ -89,6 +89,8 @@ CONFIG_SYS_NAND_ONFI_DETECTION=y
|
||||
CONFIG_SYS_NAND_PAGE_COUNT=0x40
|
||||
CONFIG_SYS_NAND_PAGE_SIZE=0x800
|
||||
CONFIG_SYS_NAND_OOBSIZE=0x40
|
||||
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
|
||||
CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000
|
||||
CONFIG_DM_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
CONFIG_MTD_UBI_FASTMAP=y
|
||||
|
@ -71,6 +71,8 @@ CONFIG_NAND_ATMEL=y
|
||||
CONFIG_ATMEL_NAND_HW_PMECC=y
|
||||
CONFIG_PMECC_CAP=4
|
||||
CONFIG_SYS_NAND_ONFI_DETECTION=y
|
||||
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
|
||||
CONFIG_SYS_NAND_U_BOOT_OFFS=0x40000
|
||||
CONFIG_DM_ETH=y
|
||||
CONFIG_MACB=y
|
||||
CONFIG_PINCTRL=y
|
||||
|
@ -74,6 +74,8 @@ CONFIG_SYS_NAND_ONFI_DETECTION=y
|
||||
CONFIG_SYS_NAND_PAGE_COUNT=0x40
|
||||
CONFIG_SYS_NAND_PAGE_SIZE=0x800
|
||||
CONFIG_SYS_NAND_OOBSIZE=0x40
|
||||
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
|
||||
CONFIG_SYS_NAND_U_BOOT_OFFS=0x40000
|
||||
CONFIG_DM_ETH=y
|
||||
CONFIG_MACB=y
|
||||
CONFIG_PINCTRL=y
|
||||
|
@ -74,6 +74,8 @@ CONFIG_NAND_ATMEL=y
|
||||
CONFIG_ATMEL_NAND_HW_PMECC=y
|
||||
CONFIG_PMECC_CAP=4
|
||||
CONFIG_SYS_NAND_ONFI_DETECTION=y
|
||||
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
|
||||
CONFIG_SYS_NAND_U_BOOT_OFFS=0x40000
|
||||
CONFIG_DM_SPI_FLASH=y
|
||||
CONFIG_SF_DEFAULT_SPEED=30000000
|
||||
CONFIG_SPI_FLASH_ATMEL=y
|
||||
|
@ -76,6 +76,8 @@ CONFIG_SYS_NAND_ONFI_DETECTION=y
|
||||
CONFIG_SYS_NAND_PAGE_COUNT=0x40
|
||||
CONFIG_SYS_NAND_PAGE_SIZE=0x800
|
||||
CONFIG_SYS_NAND_OOBSIZE=0x40
|
||||
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
|
||||
CONFIG_SYS_NAND_U_BOOT_OFFS=0x40000
|
||||
CONFIG_DM_SPI_FLASH=y
|
||||
CONFIG_SF_DEFAULT_SPEED=30000000
|
||||
CONFIG_SPI_FLASH_ATMEL=y
|
||||
|
@ -75,6 +75,8 @@ CONFIG_NAND_ATMEL=y
|
||||
CONFIG_ATMEL_NAND_HW_PMECC=y
|
||||
CONFIG_PMECC_CAP=4
|
||||
CONFIG_SYS_NAND_ONFI_DETECTION=y
|
||||
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
|
||||
CONFIG_SYS_NAND_U_BOOT_OFFS=0x40000
|
||||
CONFIG_DM_SPI_FLASH=y
|
||||
CONFIG_SF_DEFAULT_SPEED=30000000
|
||||
CONFIG_SPI_FLASH_ATMEL=y
|
||||
|
@ -67,6 +67,8 @@ CONFIG_NAND_ATMEL=y
|
||||
CONFIG_ATMEL_NAND_HW_PMECC=y
|
||||
CONFIG_PMECC_CAP=8
|
||||
CONFIG_SYS_NAND_ONFI_DETECTION=y
|
||||
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
|
||||
CONFIG_SYS_NAND_U_BOOT_OFFS=0x40000
|
||||
CONFIG_DM_SPI_FLASH=y
|
||||
CONFIG_SF_DEFAULT_SPEED=30000000
|
||||
CONFIG_SPI_FLASH_ATMEL=y
|
||||
|
@ -71,6 +71,8 @@ CONFIG_SYS_NAND_ONFI_DETECTION=y
|
||||
CONFIG_SYS_NAND_PAGE_COUNT=0x40
|
||||
CONFIG_SYS_NAND_PAGE_SIZE=0x1000
|
||||
CONFIG_SYS_NAND_OOBSIZE=0xe0
|
||||
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
|
||||
CONFIG_SYS_NAND_U_BOOT_OFFS=0x40000
|
||||
CONFIG_DM_SPI_FLASH=y
|
||||
CONFIG_SF_DEFAULT_SPEED=30000000
|
||||
CONFIG_SPI_FLASH_ATMEL=y
|
||||
|
@ -73,6 +73,8 @@ CONFIG_NAND_ATMEL=y
|
||||
CONFIG_ATMEL_NAND_HW_PMECC=y
|
||||
CONFIG_PMECC_CAP=8
|
||||
CONFIG_SYS_NAND_ONFI_DETECTION=y
|
||||
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
|
||||
CONFIG_SYS_NAND_U_BOOT_OFFS=0x40000
|
||||
CONFIG_DM_SPI_FLASH=y
|
||||
CONFIG_SF_DEFAULT_SPEED=30000000
|
||||
CONFIG_SPI_FLASH_ATMEL=y
|
||||
|
@ -65,6 +65,8 @@ CONFIG_NAND_ATMEL=y
|
||||
CONFIG_ATMEL_NAND_HW_PMECC=y
|
||||
CONFIG_PMECC_CAP=8
|
||||
CONFIG_SYS_NAND_ONFI_DETECTION=y
|
||||
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
|
||||
CONFIG_SYS_NAND_U_BOOT_OFFS=0x40000
|
||||
CONFIG_DM_SPI_FLASH=y
|
||||
CONFIG_SF_DEFAULT_SPEED=30000000
|
||||
CONFIG_SPI_FLASH_ATMEL=y
|
||||
|
@ -69,6 +69,8 @@ CONFIG_SYS_NAND_ONFI_DETECTION=y
|
||||
CONFIG_SYS_NAND_PAGE_COUNT=0x40
|
||||
CONFIG_SYS_NAND_PAGE_SIZE=0x1000
|
||||
CONFIG_SYS_NAND_OOBSIZE=0xe0
|
||||
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
|
||||
CONFIG_SYS_NAND_U_BOOT_OFFS=0x40000
|
||||
CONFIG_DM_SPI_FLASH=y
|
||||
CONFIG_SF_DEFAULT_SPEED=30000000
|
||||
CONFIG_SPI_FLASH_ATMEL=y
|
||||
|
@ -68,6 +68,8 @@ CONFIG_NAND_ATMEL=y
|
||||
CONFIG_ATMEL_NAND_HW_PMECC=y
|
||||
CONFIG_PMECC_CAP=8
|
||||
CONFIG_SYS_NAND_ONFI_DETECTION=y
|
||||
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
|
||||
CONFIG_SYS_NAND_U_BOOT_OFFS=0x40000
|
||||
CONFIG_DM_SPI_FLASH=y
|
||||
CONFIG_SF_DEFAULT_SPEED=30000000
|
||||
CONFIG_SPI_FLASH_ATMEL=y
|
||||
|
@ -67,6 +67,8 @@ CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
|
||||
CONFIG_SYS_NAND_PAGE_COUNT=0x40
|
||||
CONFIG_SYS_NAND_PAGE_SIZE=0x800
|
||||
CONFIG_SYS_NAND_OOBSIZE=0x40
|
||||
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
|
||||
CONFIG_SYS_NAND_U_BOOT_OFFS=0x20000
|
||||
CONFIG_PHYLIB=y
|
||||
CONFIG_ATMEL_USART=y
|
||||
CONFIG_USB=y
|
||||
|
@ -72,6 +72,8 @@ CONFIG_MTD_RAW_NAND=y
|
||||
CONFIG_SYS_NAND_USE_FLASH_BBT=y
|
||||
CONFIG_NAND_DENALI_DT=y
|
||||
CONFIG_SYS_NAND_ONFI_DETECTION=y
|
||||
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
|
||||
CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000
|
||||
CONFIG_SPL_NAND_DENALI=y
|
||||
CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=2
|
||||
# CONFIG_DM_SPI_FLASH is not set
|
||||
|
@ -83,6 +83,8 @@ CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
|
||||
CONFIG_SYS_NAND_PAGE_COUNT=0x40
|
||||
CONFIG_SYS_NAND_PAGE_SIZE=0x800
|
||||
CONFIG_SYS_NAND_OOBSIZE=0x40
|
||||
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
|
||||
CONFIG_SYS_NAND_U_BOOT_OFFS=0x20000
|
||||
CONFIG_DM_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
CONFIG_PHYLIB=y
|
||||
|
@ -89,6 +89,8 @@ CONFIG_SYS_NAND_ONFI_DETECTION=y
|
||||
CONFIG_SYS_NAND_PAGE_COUNT=0x40
|
||||
CONFIG_SYS_NAND_PAGE_SIZE=0x800
|
||||
CONFIG_SYS_NAND_OOBSIZE=0x40
|
||||
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
|
||||
CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000
|
||||
CONFIG_DM_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
CONFIG_MTD_UBI_FASTMAP=y
|
||||
|
@ -65,6 +65,8 @@ CONFIG_SYS_NAND_PAGE_COUNT=0x40
|
||||
CONFIG_SYS_NAND_PAGE_SIZE=0x800
|
||||
CONFIG_SYS_NAND_OOBSIZE=0x40
|
||||
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
|
||||
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
|
||||
CONFIG_SYS_NAND_U_BOOT_OFFS=0xc0000
|
||||
CONFIG_DM_ETH=y
|
||||
CONFIG_MII=y
|
||||
CONFIG_DRIVER_TI_EMAC=y
|
||||
|
@ -47,6 +47,8 @@ CONFIG_MTD=y
|
||||
CONFIG_MTD_RAW_NAND=y
|
||||
CONFIG_NAND_DENALI_DT=y
|
||||
CONFIG_SYS_NAND_ONFI_DETECTION=y
|
||||
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
|
||||
CONFIG_SYS_NAND_U_BOOT_OFFS=0x20000
|
||||
CONFIG_SPL_NAND_DENALI=y
|
||||
CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8
|
||||
CONFIG_SMC911X=y
|
||||
|
@ -48,6 +48,8 @@ CONFIG_MTD=y
|
||||
CONFIG_MTD_RAW_NAND=y
|
||||
CONFIG_NAND_DENALI_DT=y
|
||||
CONFIG_SYS_NAND_ONFI_DETECTION=y
|
||||
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
|
||||
CONFIG_SYS_NAND_U_BOOT_OFFS=0x20000
|
||||
CONFIG_SPL_NAND_DENALI=y
|
||||
CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8
|
||||
CONFIG_SNI_AVE=y
|
||||
|
@ -55,6 +55,8 @@ CONFIG_SYS_I2C_EEPROM_ADDR=0x56
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_RAW_NAND=y
|
||||
CONFIG_NAND_LPC32XX_MLC=y
|
||||
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
|
||||
CONFIG_SYS_NAND_U_BOOT_OFFS=0x40000
|
||||
CONFIG_PHYLIB=y
|
||||
CONFIG_PHY_ADDR_ENABLE=y
|
||||
CONFIG_PHY_SMSC=y
|
||||
|
@ -192,7 +192,6 @@
|
||||
#define CONFIG_SYS_NAND_ECCSIZE 512
|
||||
#define CONFIG_SYS_NAND_ECCBYTES 14
|
||||
#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW
|
||||
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x000c0000
|
||||
/* NAND: SPL related configs */
|
||||
#ifdef CONFIG_SPL_OS_BOOT
|
||||
#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00200000 /* kernel offset */
|
||||
|
@ -32,7 +32,6 @@
|
||||
#define CONFIG_SYS_NAND_MAX_OOBFREE 2
|
||||
#define CONFIG_SYS_NAND_MAX_ECCPOS 56
|
||||
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
|
||||
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
|
||||
#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x2a0000
|
||||
/* NAND block size is 128 KiB. Synchronize these values with
|
||||
* corresponding Device Tree entries in Linux:
|
||||
|
@ -183,7 +183,6 @@
|
||||
}
|
||||
#define CONFIG_SYS_NAND_ECCSIZE 512
|
||||
#define CONFIG_SYS_NAND_ECCBYTES 26
|
||||
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x00180000
|
||||
/* NAND: SPL related configs */
|
||||
/* NAND: SPL falcon mode configs */
|
||||
#ifdef CONFIG_SPL_OS_BOOT
|
||||
|
@ -93,7 +93,6 @@
|
||||
|
||||
#elif CONFIG_NAND_BOOT
|
||||
#define CONFIG_SPL_NAND_SOFTECC
|
||||
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
|
||||
#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000
|
||||
|
||||
#define CONFIG_SYS_NAND_ECCSIZE 256
|
||||
|
@ -114,6 +114,5 @@
|
||||
#ifdef CONFIG_SD_BOOT
|
||||
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
|
||||
#endif
|
||||
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
|
||||
|
||||
#endif
|
||||
|
@ -97,6 +97,5 @@
|
||||
#ifdef CONFIG_SD_BOOT
|
||||
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
|
||||
#endif
|
||||
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
|
||||
|
||||
#endif
|
||||
|
@ -46,7 +46,6 @@
|
||||
|
||||
#ifdef CONFIG_MTD_RAW_NAND
|
||||
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
|
||||
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
|
||||
#endif /* CONFIG_MTD_RAW_NAND */
|
||||
|
||||
#ifdef CONFIG_MTD_RAW_NAND
|
||||
|
@ -135,7 +135,6 @@
|
||||
#define CONFIG_SYS_NAND_ECCSIZE 512
|
||||
#define CONFIG_SYS_NAND_ECCBYTES 14
|
||||
#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW
|
||||
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x000c0000
|
||||
/* NAND: SPL related configs */
|
||||
|
||||
/* USB configuration */
|
||||
|
@ -98,9 +98,6 @@
|
||||
|
||||
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
|
||||
|
||||
#undef CONFIG_SYS_NAND_U_BOOT_OFFS
|
||||
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x200000
|
||||
|
||||
#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
|
||||
#ifdef CONFIG_SPL_OS_BOOT
|
||||
#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x500000
|
||||
|
@ -93,7 +93,6 @@
|
||||
|
||||
#define CONFIG_SPL_NAND_RAW_ONLY
|
||||
#define CONFIG_SPL_NAND_SOFTECC
|
||||
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000
|
||||
#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000
|
||||
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
|
||||
#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
|
||||
|
@ -127,7 +127,6 @@
|
||||
#define CONFIG_SPL_PAD_TO CONFIG_SPL_MAX_SIZE
|
||||
|
||||
/* U-Boot will be 0x60000 bytes, loaded and run at CONFIG_SYS_TEXT_BASE */
|
||||
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
|
||||
#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x60000
|
||||
|
||||
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
|
||||
|
@ -140,7 +140,6 @@
|
||||
#define CONFIG_SYS_NAND_ECCBYTES 3
|
||||
#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
|
||||
|
||||
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
|
||||
#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x200000
|
||||
|
||||
/* SPL OS boot options */
|
||||
|
@ -91,7 +91,6 @@
|
||||
50, 51, 52, 53, 54, 55, 56, 57, }
|
||||
#define CONFIG_SYS_NAND_ECCSIZE 512
|
||||
#define CONFIG_SYS_NAND_ECCBYTES 14
|
||||
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x00140000
|
||||
/* NAND: SPL related configs */
|
||||
/* NAND: SPL falcon mode configs */
|
||||
#ifdef CONFIG_SPL_OS_BOOT
|
||||
|
@ -15,7 +15,6 @@
|
||||
#include "siemens-am33x-common.h"
|
||||
/* NAND specific changes for etamin due to different page size */
|
||||
#undef CONFIG_SYS_NAND_ECCPOS
|
||||
#undef CONFIG_SYS_NAND_U_BOOT_OFFS
|
||||
#undef CONFIG_SYS_ENV_SECT_SIZE
|
||||
#undef CONFIG_NAND_OMAP_ECCSCHEME
|
||||
#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH16_CODE_HW
|
||||
@ -49,8 +48,6 @@
|
||||
#define CONFIG_SYS_NAND_ECCSIZE 512
|
||||
#define CONFIG_SYS_NAND_ECCBYTES 26
|
||||
|
||||
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x200000
|
||||
|
||||
#undef CONFIG_SYS_MAX_NAND_DEVICE
|
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 3
|
||||
#define CONFIG_SYS_NAND_BASE2 (0x18000000) /* physical address */
|
||||
|
@ -55,7 +55,6 @@
|
||||
#define CONFIG_SYS_MCKR_CSS 0x1302
|
||||
|
||||
#define CONFIG_SPL_NAND_RAW_ONLY
|
||||
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
|
||||
#define CONFIG_SYS_NAND_U_BOOT_SIZE 0xa0000
|
||||
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
|
||||
#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
|
||||
|
@ -8,7 +8,6 @@
|
||||
|
||||
/* SPL */
|
||||
/* Location in NAND to read U-Boot from */
|
||||
#define CONFIG_SYS_NAND_U_BOOT_OFFS (14 * SZ_1M)
|
||||
|
||||
/* Falcon Mode */
|
||||
#define CONFIG_SYS_SPL_ARGS_ADDR 0x18000000
|
||||
|
@ -138,7 +138,6 @@
|
||||
# define CONFIG_SYS_MAX_NAND_DEVICE 1
|
||||
# define CONFIG_SYS_NAND_BASE 0x40000000
|
||||
# define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
|
||||
# define CONFIG_SYS_NAND_U_BOOT_OFFS 0x200000
|
||||
|
||||
/* MTD device */
|
||||
#endif
|
||||
|
@ -130,7 +130,6 @@
|
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1
|
||||
#define CONFIG_SYS_NAND_BASE 0x40000000
|
||||
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
|
||||
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x200000
|
||||
#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00500000
|
||||
|
||||
/* MTD device */
|
||||
|
@ -46,7 +46,6 @@ unsigned long get_board_sys_clk(void);
|
||||
#define CONFIG_SPL_PAD_TO 0x1c000
|
||||
|
||||
#define CONFIG_SYS_NAND_U_BOOT_SIZE (400 << 10)
|
||||
#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO
|
||||
#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
|
||||
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
|
||||
|
||||
|
@ -150,7 +150,6 @@ unsigned long get_board_sys_clk(void);
|
||||
|
||||
#ifdef CONFIG_NAND_BOOT
|
||||
#define CONFIG_SPL_PAD_TO 0x20000 /* block aligned */
|
||||
#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO
|
||||
#define CONFIG_SYS_NAND_U_BOOT_SIZE (640 << 10)
|
||||
#endif
|
||||
|
||||
|
@ -109,7 +109,6 @@
|
||||
|
||||
#ifdef CONFIG_NAND_BOOT
|
||||
#define CONFIG_SPL_PAD_TO 0x20000 /* block aligned */
|
||||
#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO
|
||||
#define CONFIG_SYS_NAND_U_BOOT_SIZE (1024 << 10)
|
||||
#endif
|
||||
|
||||
|
@ -165,7 +165,6 @@ unsigned long get_board_sys_clk(void);
|
||||
|
||||
#ifdef CONFIG_NAND_BOOT
|
||||
#define CONFIG_SPL_PAD_TO 0x40000 /* block aligned */
|
||||
#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO
|
||||
#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
|
||||
#endif
|
||||
|
||||
|
@ -208,7 +208,6 @@ unsigned long get_board_sys_clk(void);
|
||||
#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
|
||||
|
||||
#define CONFIG_SPL_PAD_TO 0x20000
|
||||
#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 * 1024)
|
||||
#define CONFIG_SYS_NAND_U_BOOT_SIZE (640 * 1024)
|
||||
#endif
|
||||
#else
|
||||
|
@ -202,7 +202,6 @@ unsigned long get_board_sys_clk(void);
|
||||
#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
|
||||
|
||||
#define CONFIG_SPL_PAD_TO 0x80000
|
||||
#define CONFIG_SYS_NAND_U_BOOT_OFFS (1024 * 1024)
|
||||
#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 * 1024)
|
||||
#else
|
||||
#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
|
||||
|
@ -139,7 +139,6 @@
|
||||
#define CONFIG_SPL_PAD_TO 0x8000
|
||||
#define CONFIG_SPL_STACK 0x70004000
|
||||
|
||||
#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO
|
||||
#define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024)
|
||||
|
||||
/*
|
||||
|
@ -27,7 +27,6 @@
|
||||
#define CONFIG_SYS_NAND_ECCSIZE 512
|
||||
#define CONFIG_SYS_NAND_ECCBYTES 3
|
||||
#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
|
||||
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
|
||||
#define CONFIG_SYS_ENV_SECT_SIZE SZ_128K
|
||||
/* NAND: SPL falcon mode configs */
|
||||
#if defined(CONFIG_SPL_OS_BOOT)
|
||||
|
@ -83,7 +83,6 @@
|
||||
|
||||
#elif CONFIG_NAND_BOOT
|
||||
#define CONFIG_SPL_NAND_SOFTECC
|
||||
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
|
||||
#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000
|
||||
|
||||
#define CONFIG_SYS_NAND_ECCSIZE 256
|
||||
|
@ -68,7 +68,6 @@
|
||||
#ifdef CONFIG_SD_BOOT
|
||||
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
|
||||
#endif
|
||||
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
|
||||
|
||||
/* Falcon boot support on raw MMC */
|
||||
#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x100 /* 128 KiB */
|
||||
|
@ -80,6 +80,5 @@
|
||||
#ifdef CONFIG_SD_BOOT
|
||||
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
|
||||
#endif
|
||||
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
|
||||
|
||||
#endif
|
||||
|
@ -44,6 +44,5 @@
|
||||
#ifdef CONFIG_SD_BOOT
|
||||
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
|
||||
#endif
|
||||
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
|
||||
|
||||
#endif
|
||||
|
@ -44,6 +44,5 @@
|
||||
#ifdef CONFIG_SD_BOOT
|
||||
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
|
||||
#endif
|
||||
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
|
||||
|
||||
#endif
|
||||
|
@ -90,8 +90,6 @@
|
||||
|
||||
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
|
||||
|
||||
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
|
||||
|
||||
/*
|
||||
* 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
|
||||
* 64 bytes before this address should be set aside for u-boot.img's
|
||||
|
@ -162,7 +162,6 @@
|
||||
#define CONFIG_SYS_USE_NANDFLASH 1
|
||||
#define CONFIG_SPL_NAND_RAW_ONLY
|
||||
#define CONFIG_SPL_NAND_SOFTECC
|
||||
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000
|
||||
#define CONFIG_SYS_NAND_U_BOOT_SIZE SZ_512K
|
||||
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
|
||||
#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
|
||||
|
@ -111,11 +111,6 @@
|
||||
/* The rest of the configuration is shared */
|
||||
#include <configs/socfpga_common.h>
|
||||
|
||||
#ifdef CONFIG_SPL_NAND_SUPPORT
|
||||
#undef CONFIG_SYS_NAND_U_BOOT_OFFS
|
||||
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
|
||||
#endif
|
||||
|
||||
#undef CONFIG_WATCHDOG_TIMEOUT_MSECS
|
||||
#define CONFIG_WATCHDOG_TIMEOUT_MSECS 60000
|
||||
|
||||
|
@ -196,13 +196,6 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
|
||||
/* SPL QSPI boot support */
|
||||
|
||||
/* SPL NAND boot support */
|
||||
#ifdef CONFIG_SPL_NAND_SUPPORT
|
||||
#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
|
||||
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
|
||||
#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
|
||||
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x100000
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* Extra Environment */
|
||||
#ifndef CONFIG_SPL_BUILD
|
||||
|
@ -135,7 +135,6 @@
|
||||
|
||||
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
|
||||
|
||||
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
|
||||
#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000
|
||||
|
||||
/* Setup MTD for NAND on the SOM */
|
||||
|
@ -164,7 +164,6 @@
|
||||
#define CONFIG_SYS_USE_NANDFLASH 1
|
||||
#define CONFIG_SPL_NAND_RAW_ONLY
|
||||
#define CONFIG_SPL_NAND_SOFTECC
|
||||
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000
|
||||
#define CONFIG_SYS_NAND_U_BOOT_SIZE SZ_512K
|
||||
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
|
||||
#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
|
||||
|
@ -69,7 +69,6 @@
|
||||
#define CONFIG_SYS_NAND_ECCSIZE 512
|
||||
#define CONFIG_SYS_NAND_ECCBYTES 14
|
||||
#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW
|
||||
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x000c0000
|
||||
|
||||
/* SPL */
|
||||
/* Defines for SPL */
|
||||
|
@ -193,8 +193,6 @@
|
||||
/* only for SPL */
|
||||
#define CONFIG_SPL_STACK (0x00100000)
|
||||
|
||||
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000
|
||||
|
||||
/* subtract sizeof(struct image_header) */
|
||||
#define CONFIG_SYS_UBOOT_BASE (0x130000 - 0x40)
|
||||
|
||||
|
@ -86,7 +86,6 @@
|
||||
/* Use the framework and generic lib */
|
||||
/* SPL will use serial */
|
||||
/* SPL will load U-Boot from NAND offset 0x40000 */
|
||||
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x00040000
|
||||
#define CONFIG_SPL_PAD_TO 0x20000
|
||||
/* U-Boot will be 0x40000 bytes, loaded and run at CONFIG_SYS_TEXT_BASE */
|
||||
#define CONFIG_SYS_MONITOR_LEN 0x40000 /* actually, MAX size */
|
||||
|
Loading…
Reference in New Issue
Block a user