board: imx8mp: Add Engicam i.Core MX8M Plus EDIMM2.2 Starter Kit
i.Core MX8M Plus is an EDIMM SoM based on NXP i.MX8M Plus from Engicam. i.Core MX8M Plus needs to mount on top of this Evaluation board for creating complete i.Core MX8M Plus EDIMM2.2 Starter Kit. Add support for it. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
This commit is contained in:
Manoj Sai
Stefano Babic
parent
3fb342a53c
commit
864ac2cf38
149
arch/arm/dts/imx8mp-icore-mx8mp-edimm2.2-u-boot.dtsi
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149
arch/arm/dts/imx8mp-icore-mx8mp-edimm2.2-u-boot.dtsi
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@ -0,0 +1,149 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2019 NXP
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* Copyright (c) 2020 Amarula Solutons(India)
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*/
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#include "imx8mp-u-boot.dtsi"
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/ {
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wdt-reboot {
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compatible = "wdt-reboot";
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wdt = <&wdog1>;
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u-boot,dm-spl;
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};
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firmware {
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optee {
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compatible = "linaro,optee-tz";
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method = "smc";
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};
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};
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};
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®_usdhc2_vmmc {
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u-boot,off-on-delay-us = <20000>;
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};
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®_usdhc2_vmmc {
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u-boot,dm-spl;
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};
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&pinctrl_uart2 {
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u-boot,dm-spl;
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};
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&pinctrl_usdhc2_gpio {
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u-boot,dm-spl;
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};
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&pinctrl_usdhc2 {
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u-boot,dm-spl;
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};
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&pinctrl_usdhc3 {
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u-boot,dm-spl;
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};
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&gpio1 {
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u-boot,dm-spl;
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};
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&gpio2 {
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u-boot,dm-spl;
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};
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&gpio3 {
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u-boot,dm-spl;
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};
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&gpio4 {
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u-boot,dm-spl;
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};
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&gpio5 {
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u-boot,dm-spl;
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};
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&uart2 {
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u-boot,dm-spl;
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};
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&crypto {
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u-boot,dm-spl;
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};
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&sec_jr0 {
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u-boot,dm-spl;
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};
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&sec_jr1 {
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u-boot,dm-spl;
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};
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&sec_jr2 {
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u-boot,dm-spl;
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};
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&i2c1 {
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u-boot,dm-spl;
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};
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&i2c2 {
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u-boot,dm-spl;
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};
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&i2c3 {
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u-boot,dm-spl;
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};
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&i2c4 {
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u-boot,dm-spl;
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};
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&i2c5 {
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u-boot,dm-spl;
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};
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&i2c6 {
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u-boot,dm-spl;
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};
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&usdhc1 {
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u-boot,dm-spl;
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};
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&usdhc2 {
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u-boot,dm-spl;
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sd-uhs-sdr104;
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sd-uhs-ddr50;
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no-1-8-v;
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};
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&usdhc3 {
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u-boot,dm-spl;
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mmc-hs400-1_8v;
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mmc-hs400-enhanced-strobe;
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};
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&wdog1 {
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u-boot,dm-spl;
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};
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&eqos {
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/delete-property/ assigned-clocks;
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/delete-property/ assigned-clock-parents;
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/delete-property/ assigned-clock-rates;
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};
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ðphy0 {
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reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
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reset-delay-us = <15000>;
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reset-post-delay-us = <100000>;
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};
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&fec {
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phy-reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
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phy-reset-duration = <15>;
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phy-reset-post-delay = <100>;
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};
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@ -160,6 +160,20 @@ config TARGET_IMX8MP_DH_DHCOM_PDK2
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select IMX8M_LPDDR4
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select SUPPORT_SPL
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config TARGET_IMX8MP_ICORE_MX8MP
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bool "Engicam i.Core MX8M Plus SOM"
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select BINMAN
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select IMX8MP
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select IMX8M_LPDDR4
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select SUPPORT_SPL
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help
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i.Core MX8M Plus is an EDIMM SOM based on NXP i.MX8MP.
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i.Core MX8M Plus EDIMM2.2:
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* EDIMM2.2 is a Form Factor Capacitive Evaluation Board.
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* i.Core MX8M Plus needs to mount on top of EDIMM2.2 for
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creating complete i.Core MX8M Plus EDIMM2.2 Starter Kit.
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config TARGET_IMX8MP_EVK
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bool "imx8mp LPDDR4 EVK board"
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select BINMAN
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@ -287,6 +301,7 @@ source "board/compulab/imx8mm-cl-iot-gate/Kconfig"
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source "board/data_modul/imx8mm_edm_sbc/Kconfig"
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source "board/dhelectronics/dh_imx8mp/Kconfig"
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source "board/engicam/imx8mm/Kconfig"
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source "board/engicam/imx8mp/Kconfig"
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source "board/freescale/imx8mq_evk/Kconfig"
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source "board/freescale/imx8mm_evk/Kconfig"
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source "board/freescale/imx8mn_evk/Kconfig"
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15
board/engicam/imx8mp/Kconfig
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15
board/engicam/imx8mp/Kconfig
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@ -0,0 +1,15 @@
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if TARGET_IMX8MP_ICORE_MX8MP
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config SYS_BOARD
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default "imx8mp"
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config SYS_VENDOR
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default "engicam"
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config SYS_CONFIG_NAME
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default "imx8mp_icore_mx8mp"
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config IMX_CONFIG
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default "board/engicam/imx8mp/imximage-lpddr4.cfg"
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endif
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7
board/engicam/imx8mp/MAINTAINERS
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7
board/engicam/imx8mp/MAINTAINERS
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@ -0,0 +1,7 @@
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i.Core-MX8M-Plus-EDIMM2.2
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M: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
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M: Matteo Lisi <matteo.lisi@engicam.com>
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S: Maintained
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F: board/engicam/imx8mp
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F: include/configs/imx8mp_icore_mx8mp.h
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F: configs/imx8mp-icore-mx8mp-edimm2.2_defconfig
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12
board/engicam/imx8mp/Makefile
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12
board/engicam/imx8mp/Makefile
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#
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# Copyright (C) 2020 Amarula Solutions(India)
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y += icore_mx8mp.o
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ifdef CONFIG_SPL_BUILD
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obj-y += spl.o
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obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o
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endif
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73
board/engicam/imx8mp/icore_mx8mp.c
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73
board/engicam/imx8mp/icore_mx8mp.c
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@ -0,0 +1,73 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2016 Engicam S.r.l.
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* Copyright (C) 2022 Amarula Solutions(India)
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*
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* Authors:
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* Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
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* Jagan Teki <jagan@amarulasolutions.com>
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*/
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#include <common.h>
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#include <env.h>
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#include <errno.h>
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#include <init.h>
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#include <miiphy.h>
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#include <netdev.h>
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#include <linux/delay.h>
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#include <asm/global_data.h>
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#include <asm/mach-imx/iomux-v3.h>
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#include <asm-generic/gpio.h>
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#include <asm/arch/imx8mp_pins.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/mach-imx/gpio.h>
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DECLARE_GLOBAL_DATA_PTR;
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static void setup_fec(void)
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{
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struct iomuxc_gpr_base_regs *gpr =
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(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
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/* Enable RGMII TX clk output */
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setbits_le32(&gpr->gpr[1], BIT(22));
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}
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static int setup_eqos(void)
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{
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struct iomuxc_gpr_base_regs *gpr =
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(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
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/* set INTF as RGMII, enable RGMII TXC clock */
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clrsetbits_le32(&gpr->gpr[1],
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IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK, BIT(16));
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setbits_le32(&gpr->gpr[1], BIT(19) | BIT(21));
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return set_clk_eqos(ENET_125MHZ);
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}
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#if CONFIG_IS_ENABLED(NET)
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int board_phy_config(struct phy_device *phydev)
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{
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if (phydev->drv->config)
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phydev->drv->config(phydev);
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return 0;
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}
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#endif
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int board_init(void)
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{
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if (CONFIG_IS_ENABLED(FEC_MXC))
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setup_fec();
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if (CONFIG_IS_ENABLED(DWC_ETH_QOS))
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setup_eqos();
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return 0;
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}
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int board_late_init(void)
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{
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return 0;
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}
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8
board/engicam/imx8mp/imximage-lpddr4.cfg
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8
board/engicam/imx8mp/imximage-lpddr4.cfg
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2021 NXP
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*/
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ROM_VERSION v2
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BOOT_FROM sd
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LOADER u-boot-spl-ddr.bin 0x920000
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1850
board/engicam/imx8mp/lpddr4_timing.c
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1850
board/engicam/imx8mp/lpddr4_timing.c
Normal file
File diff suppressed because it is too large
Load Diff
152
board/engicam/imx8mp/spl.c
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152
board/engicam/imx8mp/spl.c
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@ -0,0 +1,152 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2022 Amarula Solutions(India)
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* Copyright (C) 2016 Engicam S.r.l.
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*
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* Authors:
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* Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
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* Jagan Teki <jagan@amarulasolutions.com>
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*/
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#include <common.h>
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#include <hang.h>
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#include <init.h>
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#include <log.h>
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#include <spl.h>
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#include <asm/global_data.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/imx8mp_pins.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/mach-imx/boot_mode.h>
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#include <asm/mach-imx/gpio.h>
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#include <asm/mach-imx/iomux-v3.h>
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#include <asm/mach-imx/mxc_i2c.h>
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#include <asm/arch/ddr.h>
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#include <power/pmic.h>
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#include <power/pca9450.h>
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DECLARE_GLOBAL_DATA_PTR;
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int spl_board_boot_device(enum boot_device boot_dev_spl)
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{
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return BOOT_DEVICE_BOOTROM;
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}
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void spl_dram_init(void)
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{
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ddr_init(&dram_timing);
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}
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#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE)
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#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
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struct i2c_pads_info i2c_pad_info1 = {
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.scl = {
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.i2c_mode = MX8MP_PAD_I2C1_SCL__I2C1_SCL | PC,
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.gpio_mode = MX8MP_PAD_I2C1_SCL__GPIO5_IO14 | PC,
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.gp = IMX_GPIO_NR(5, 14),
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},
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.sda = {
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.i2c_mode = MX8MP_PAD_I2C1_SDA__I2C1_SDA | PC,
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.gpio_mode = MX8MP_PAD_I2C1_SDA__GPIO5_IO15 | PC,
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.gp = IMX_GPIO_NR(5, 15),
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},
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};
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#if CONFIG_IS_ENABLED(POWER_LEGACY)
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#define I2C_PMIC 0
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int power_init_board(void)
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{
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struct pmic *p;
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int ret;
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ret = power_pca9450_init(I2C_PMIC, 0x25);
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if (ret)
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printf("power init failed");
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p = pmic_get("PCA9450");
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pmic_probe(p);
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/* BUCKxOUT_DVS0/1 control BUCK123 output */
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pmic_reg_write(p, PCA9450_BUCK123_DVS, 0x29);
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#ifdef CONFIG_IMX8M_LPDDR4
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/*
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* increase VDD_SOC to typical value 0.95V before first
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* DRAM access, set DVS1 to 0.85v for suspend.
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* Enable DVS control through PMIC_STBY_REQ and
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* set B1_ENMODE=1 (ON by PMIC_ON_REQ=H)
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*/
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#ifdef CONFIG_IMX8M_VDD_SOC_850MV
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/* set DVS0 to 0.85v for special case*/
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pmic_reg_write(p, PCA9450_BUCK1OUT_DVS0, 0x14);
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#else
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pmic_reg_write(p, PCA9450_BUCK1OUT_DVS0, 0x1C);
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#endif
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pmic_reg_write(p, PCA9450_BUCK1OUT_DVS1, 0x14);
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pmic_reg_write(p, PCA9450_BUCK1CTRL, 0x59);
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/* Kernel uses OD/OD freq for SOC */
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/* To avoid timing risk from SOC to ARM,increase VDD_ARM to OD voltage 0.95v */
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pmic_reg_write(p, PCA9450_BUCK2OUT_DVS0, 0x1C);
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#elif defined(CONFIG_IMX8M_DDR4)
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/* DDR4 runs at 3200MTS, uses default ND 0.85v for VDD_SOC and VDD_ARM */
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pmic_reg_write(p, PCA9450_BUCK1CTRL, 0x59);
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/* Set NVCC_DRAM to 1.2v for DDR4 */
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pmic_reg_write(p, PCA9450_BUCK6OUT, 0x18);
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#endif
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/* set WDOG_B_CFG to cold reset */
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pmic_reg_write(p, PCA9450_RESET_CTRL, 0xA1);
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return 0;
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}
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#endif
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void spl_board_init(void)
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{
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/* Set GIC clock to 500Mhz for OD VDD_SOC. Kernel driver does not allow to change it.
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* Should set the clock after PMIC setting done.
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* Default is 400Mhz (system_pll1_800m with div = 2) set by ROM for ND VDD_SOC
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*/
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clock_enable(CCGR_GIC, 0);
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clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(5));
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clock_enable(CCGR_GIC, 1);
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puts("Normal Boot\n");
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}
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#ifdef CONFIG_SPL_LOAD_FIT
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int board_fit_config_name_match(const char *name)
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{
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/* Just empty function now - can't decide what to choose */
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debug("%s: %s\n", __func__, name);
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return 0;
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}
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#endif
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void board_init_f(ulong dummy)
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{
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int ret;
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arch_cpu_init();
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init_uart_clk(1);
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ret = spl_early_init();
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if (ret) {
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debug("spl_early_init() failed: %d\n", ret);
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hang();
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}
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preloader_console_init();
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enable_tzc380();
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setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
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power_init_board();
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/* DDR initialization */
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spl_dram_init();
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}
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||||
112
configs/imx8mp-icore-mx8mp-edimm2.2_defconfig
Normal file
112
configs/imx8mp-icore-mx8mp-edimm2.2_defconfig
Normal file
|
|
@ -0,0 +1,112 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_IMX8M=y
|
||||
CONFIG_SYS_TEXT_BASE=0x40200000
|
||||
CONFIG_SYS_MALLOC_LEN=0x2000000
|
||||
CONFIG_SPL_GPIO=y
|
||||
CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||
CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||
CONFIG_ENV_SIZE=0x1000
|
||||
CONFIG_ENV_OFFSET=0x400000
|
||||
CONFIG_SYS_I2C_MXC_I2C1=y
|
||||
CONFIG_SYS_I2C_MXC_I2C2=y
|
||||
CONFIG_SYS_I2C_MXC_I2C3=y
|
||||
CONFIG_DM_GPIO=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="imx8mp-icore-mx8mp-edimm2.2"
|
||||
CONFIG_SPL_TEXT_BASE=0x920000
|
||||
CONFIG_TARGET_IMX8MP_ICORE_MX8MP=y
|
||||
CONFIG_SPL_MMC=y
|
||||
CONFIG_SPL_SERIAL=y
|
||||
CONFIG_SPL_DRIVERS_MISC=y
|
||||
CONFIG_SPL=y
|
||||
CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
|
||||
CONFIG_SYS_LOAD_ADDR=0x40480000
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
|
||||
CONFIG_SPL_LOAD_FIT=y
|
||||
# CONFIG_USE_SPL_FIT_GENERATOR is not set
|
||||
CONFIG_OF_SYSTEM_SETUP=y
|
||||
CONFIG_DEFAULT_FDT_FILE="imx8mp-icore-mx8mp-edimm2.2.dtb"
|
||||
CONFIG_BOARD_LATE_INIT=y
|
||||
CONFIG_SPL_MAX_SIZE=0x26000
|
||||
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
|
||||
CONFIG_SPL_BSS_START_ADDR=0x98fc00
|
||||
CONFIG_SPL_BSS_MAX_SIZE=0x400
|
||||
CONFIG_SPL_BOARD_INIT=y
|
||||
CONFIG_SPL_BOOTROM_SUPPORT=y
|
||||
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
|
||||
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
|
||||
CONFIG_SPL_STACK=0x960000
|
||||
CONFIG_SYS_SPL_MALLOC=y
|
||||
CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
|
||||
CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000
|
||||
CONFIG_SYS_SPL_MALLOC_SIZE=0x80000
|
||||
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
|
||||
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
|
||||
CONFIG_SPL_I2C=y
|
||||
CONFIG_SPL_POWER=y
|
||||
CONFIG_SPL_WATCHDOG=y
|
||||
CONFIG_SYS_PROMPT="u-boot=> "
|
||||
CONFIG_SYS_MAXARGS=64
|
||||
CONFIG_SYS_CBSIZE=2048
|
||||
CONFIG_SYS_PBSIZE=2074
|
||||
CONFIG_SYS_BOOTM_LEN=0x2000000
|
||||
# CONFIG_CMD_EXPORTENV is not set
|
||||
# CONFIG_CMD_IMPORTENV is not set
|
||||
# CONFIG_CMD_CRC32 is not set
|
||||
CONFIG_CMD_CLK=y
|
||||
CONFIG_CMD_FUSE=y
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_CACHE=y
|
||||
CONFIG_CMD_REGULATOR=y
|
||||
CONFIG_CMD_EXT4_WRITE=y
|
||||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
CONFIG_ENV_OVERWRITE=y
|
||||
CONFIG_ENV_IS_IN_MMC=y
|
||||
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
CONFIG_SYS_MMC_ENV_DEV=1
|
||||
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
|
||||
CONFIG_USE_ETHPRIME=y
|
||||
CONFIG_ETHPRIME="eth1"
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_SPL_DM=y
|
||||
CONFIG_CLK_COMPOSITE_CCF=y
|
||||
CONFIG_CLK_IMX8MP=y
|
||||
CONFIG_MXC_GPIO=y
|
||||
CONFIG_DM_PCA953X=y
|
||||
CONFIG_DM_I2C=y
|
||||
# CONFIG_SPL_DM_I2C is not set
|
||||
CONFIG_SPL_SYS_I2C_LEGACY=y
|
||||
CONFIG_LED=y
|
||||
CONFIG_LED_GPIO=y
|
||||
CONFIG_SUPPORT_EMMC_BOOT=y
|
||||
CONFIG_MMC_IO_VOLTAGE=y
|
||||
CONFIG_MMC_UHS_SUPPORT=y
|
||||
CONFIG_MMC_HS400_ES_SUPPORT=y
|
||||
CONFIG_MMC_HS400_SUPPORT=y
|
||||
CONFIG_FSL_USDHC=y
|
||||
CONFIG_PHY_MICREL=y
|
||||
CONFIG_PHY_MICREL_KSZ90X1=y
|
||||
CONFIG_DM_ETH=y
|
||||
CONFIG_DWC_ETH_QOS=y
|
||||
CONFIG_DWC_ETH_QOS_IMX=y
|
||||
CONFIG_FEC_MXC=y
|
||||
CONFIG_MII=y
|
||||
CONFIG_PINCTRL=y
|
||||
CONFIG_SPL_PINCTRL=y
|
||||
CONFIG_PINCTRL_IMX8M=y
|
||||
CONFIG_SPL_POWER_LEGACY=y
|
||||
CONFIG_DM_REGULATOR=y
|
||||
CONFIG_DM_REGULATOR_FIXED=y
|
||||
CONFIG_DM_REGULATOR_GPIO=y
|
||||
CONFIG_SPL_POWER_I2C=y
|
||||
CONFIG_DM_SERIAL=y
|
||||
CONFIG_MXC_UART=y
|
||||
CONFIG_SYSRESET=y
|
||||
CONFIG_SPL_SYSRESET=y
|
||||
CONFIG_SYSRESET_PSCI=y
|
||||
CONFIG_SYSRESET_WATCHDOG=y
|
||||
CONFIG_IMX_WATCHDOG=y
|
||||
|
|
@ -55,11 +55,9 @@
|
|||
#define CONFIG_SYS_INIT_RAM_SIZE 0x80000
|
||||
|
||||
|
||||
/* Totally 6GB DDR */
|
||||
/* Totally 2GB DDR */
|
||||
#define CONFIG_SYS_SDRAM_BASE 0x40000000
|
||||
#define PHYS_SDRAM 0x40000000
|
||||
#define PHYS_SDRAM_SIZE 0xC0000000 /* 3 GB */
|
||||
#define PHYS_SDRAM_2 0x100000000
|
||||
#define PHYS_SDRAM_2_SIZE 0xC0000000 /* 3 GB */
|
||||
#define PHYS_SDRAM_SIZE 0x80000000
|
||||
|
||||
#endif
|
||||
|
|
|
|||
64
include/configs/imx8mp_icore_mx8mp.h
Normal file
64
include/configs/imx8mp_icore_mx8mp.h
Normal file
|
|
@ -0,0 +1,64 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (c) 2020 Engicam srl
|
||||
* Copyright (c) 2022 Amarula Solutions(India)
|
||||
*/
|
||||
|
||||
#ifndef __IMX8MP_ICORE_MX8MP_H
|
||||
#define __IMX8MP_ICORE_MX8MP_H
|
||||
|
||||
#include <linux/sizes.h>
|
||||
#include <linux/stringify.h>
|
||||
#include <asm/arch/imx-regs.h>
|
||||
|
||||
#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
|
||||
#define CONFIG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
|
||||
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
|
||||
|
||||
#define CONFIG_POWER_PCA9450
|
||||
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_CMD_NET)
|
||||
#define CONFIG_FEC_MXC_PHYADDR 1
|
||||
|
||||
#define DWC_NET_PHYADDR 1
|
||||
|
||||
#define PHY_ANEG_TIMEOUT 20000
|
||||
|
||||
#endif
|
||||
|
||||
#define BOOT_TARGET_DEVICES(func) \
|
||||
func(MMC, mmc, 1) \
|
||||
func(MMC, mmc, 2)
|
||||
|
||||
#include <config_distro_bootcmd.h>
|
||||
|
||||
/* Initial environment variables */
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
BOOTENV \
|
||||
"scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
|
||||
"kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
|
||||
"image=Image\0" \
|
||||
"console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200\0" \
|
||||
"fdt_addr_r=0x43000000\0" \
|
||||
"boot_fdt=try\0" \
|
||||
"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
|
||||
"initrd_addr=0x43800000\0" \
|
||||
"bootm_size=0x10000000\0" \
|
||||
"mmcpart=1\0" \
|
||||
"mmcroot=/dev/mmcblk1p2 rootwait rw\0" \
|
||||
|
||||
/* Link Definitions */
|
||||
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x80000
|
||||
|
||||
/* Totally 2GB DDR */
|
||||
#define CONFIG_SYS_SDRAM_BASE 0x40000000
|
||||
#define PHYS_SDRAM 0x40000000
|
||||
#define PHYS_SDRAM_SIZE 0x80000000
|
||||
|
||||
#endif /* __IMX8MP_ICORE_MX8MP_H */
|
||||
Loading…
Reference in New Issue
Block a user