net: zynq_gem: Add SGMII support for zynqMP
PCS auto negotaiation bit should be enabled along with SGMII autonegotation enabled in phy. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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@ -93,6 +93,8 @@ DECLARE_GLOBAL_DATA_PTR;
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#define ZYNQ_GEM_TSR_DONE 0x00000020 /* Tx done mask */
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#define ZYNQ_GEM_PCS_CTL_ANEG_ENBL 0x1000
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/* Use MII register 1 (MII status register) to detect PHY */
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#define PHY_DETECT_REG 1
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@ -139,7 +141,9 @@ struct zynq_gem_regs {
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u32 reserved6[18];
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#define STAT_SIZE 44
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u32 stat[STAT_SIZE]; /* 0x100 - Octects transmitted Low reg */
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u32 reserved7[164];
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u32 reserved9[20];
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u32 pcscntrl;
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u32 reserved7[143];
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u32 transmit_q1_ptr; /* 0x440 - Transmit priority queue 1 */
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u32 reserved8[15];
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u32 receive_q1_ptr; /* 0x480 - Receive priority queue 1 */
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@ -432,9 +436,14 @@ static int zynq_gem_init(struct udevice *dev)
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nwconfig = ZYNQ_GEM_NWCFG_INIT;
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if (priv->interface == PHY_INTERFACE_MODE_SGMII)
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if (priv->interface == PHY_INTERFACE_MODE_SGMII) {
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nwconfig |= ZYNQ_GEM_NWCFG_SGMII_ENBL |
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ZYNQ_GEM_NWCFG_PCS_SEL;
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#ifdef CONFIG_ARM64
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writel(readl(®s->pcscntrl) | ZYNQ_GEM_PCS_CTL_ANEG_ENBL,
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®s->pcscntrl);
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#endif
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}
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switch (priv->phydev->speed) {
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case SPEED_1000:
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