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powerpc/B4860: enable PBL tool for B4860

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Use a default RCW of protocol 0x2A_0x98, and a PBI configure file which
uses CPC1 as 512KB SRAM, then PBL tool can be used on B4860 to build a
pbl boot image.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
This commit is contained in:
Shaohui Xie 2013-09-22 09:56:02 +08:00 committed by York Sun
parent ef9a1f9a4f
commit 83d925668f
3 changed files with 36 additions and 0 deletions
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27
board/freescale/b4860qds/b4_pbi.cfg Normal file
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@ -0,0 +1,27 @@
#PBI commands
#Initialize CPC1
09010000 00200400
09138000 00000000
091380c0 00000100
#Configure CPC1 as 512KB SRAM
09010100 00000000
09010104 fff80009
09010f00 08000000
09010000 80000000
#Configure LAW for CPC1
09000d00 00000000
09000d04 fff80000
09000d08 81000012
#Configure alternate space
09000010 00000000
09000014 ff000000
09000018 81000000
#Configure SPI controller
09110000 80000403
09110020 2d170008
09110024 00100008
09110028 00100008
0911002c 00100008
#Flush PBL data
09138000 00000000
091380c0 00000000

7
board/freescale/b4860qds/b4_rcw.cfg Normal file
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@ -0,0 +1,7 @@
#PBL preamble and RCW header
aa55aa55 010e0100
# serdes protocol 0x2A_0x98
140e0018 0f001218 00000000 00000000
54980000 9000a000 f8025000 a9000000
01000000 00000000 00000000 0001b1f8
00000000 14000020 00000000 00000011

2
include/configs/B4860QDS.h
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@ -16,6 +16,8 @@
#ifdef CONFIG_RAMBOOT_PBL
#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
#define CONFIG_PBLPBI_CONFIG $(SRCTREE)/board/freescale/b4860qds/b4_pbi.cfg
#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/b4860qds/b4_rcw.cfg
#endif
#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE