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This commit is contained in:
Kim Phillips 2009-01-23 17:48:24 -06:00
commit 833d94bcdc
39 changed files with 2883 additions and 202 deletions
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5
MAINTAINERS
View File

@ -263,6 +263,10 @@ Jon Loeliger <jdl@freescale.com>
MPC8641HPCN MPC8641D
Ron Madrid <info@sheldoninst.com>
SIMPC8313 MPC8313
Dan Malek <dan@embeddedalley.com>
stxgp3 MPC85xx
@ -374,6 +378,7 @@ Heiko Schocher <hs@denx.de>
ids8247 MPC8247
jupiter MPC5200
kmeter1 MPC8360
mgcoge MPC8247
mgsuvd MPC852
mucmc52 MPC5200

2
MAKEALL
View File

@ -335,6 +335,7 @@ LIST_8260=" \
#########################################################################
LIST_83xx=" \
kmeter1 \
MPC8313ERDB_33 \
MPC8313ERDB_NAND_66 \
MPC8315ERDB \
@ -352,6 +353,7 @@ LIST_83xx=" \
MPC837XERDB \
MVBLM7 \
sbc8349 \
SIMPC8313_LP \
TQM834x \
"

18
Makefile
View File

@ -2186,6 +2186,9 @@ TASREG_config : unconfig
## MPC83xx Systems
#########################################################################
kmeter1_config: unconfig
@$(MKCONFIG) kmeter1 ppc mpc83xx kmeter1 keymile
MPC8313ERDB_33_config \
MPC8313ERDB_66_config \
MPC8313ERDB_NAND_33_config \
@ -2325,6 +2328,21 @@ MVBLM7_config: unconfig
sbc8349_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc83xx sbc8349
SIMPC8313_LP_config \
SIMPC8313_SP_config: unconfig
@mkdir -p $(obj)include
@mkdir -p $(obj)board/sheldon/simpc8313
@if [ "$(findstring _LP_,$@)" ] ; then \
$(XECHO) -n "...Large Page NAND..." ; \
echo "#define CONFIG_NAND_LP" >> $(obj)include/config.h ; \
fi ; \
if [ "$(findstring _SP_,$@)" ] ; then \
$(XECHO) -n "...Small Page NAND..." ; \
echo "#define CONFIG_NAND_SP" >> $(obj)include/config.h ; \
fi ;
@$(MKCONFIG) -a SIMPC8313 ppc mpc83xx simpc8313 sheldon
@echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk
TQM834x_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc83xx tqm834x tqc

52
board/freescale/mpc8315erdb/mpc8315erdb.c
View File

@ -30,6 +30,7 @@
#include <pci.h>
#include <mpc83xx.h>
#include <netdev.h>
#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
@ -95,12 +96,45 @@ static struct pci_region pci_regions[] = {
}
};
static struct pci_region pcie_regions_0[] = {
{
.bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
.phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
.size = CONFIG_SYS_PCIE1_MEM_SIZE,
.flags = PCI_REGION_MEM,
},
{
.bus_start = CONFIG_SYS_PCIE1_IO_BASE,
.phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
.size = CONFIG_SYS_PCIE1_IO_SIZE,
.flags = PCI_REGION_IO,
},
};
static struct pci_region pcie_regions_1[] = {
{
.bus_start = CONFIG_SYS_PCIE2_MEM_BASE,
.phys_start = CONFIG_SYS_PCIE2_MEM_PHYS,
.size = CONFIG_SYS_PCIE2_MEM_SIZE,
.flags = PCI_REGION_MEM,
},
{
.bus_start = CONFIG_SYS_PCIE2_IO_BASE,
.phys_start = CONFIG_SYS_PCIE2_IO_PHYS,
.size = CONFIG_SYS_PCIE2_IO_SIZE,
.flags = PCI_REGION_IO,
},
};
void pci_init_board(void)
{
volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
volatile sysconf83xx_t *sysconf = &immr->sysconf;
volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
volatile law83xx_t *pcie_law = sysconf->pcielaw;
struct pci_region *reg[] = { pci_regions };
struct pci_region *pcie_reg[] = { pcie_regions_0, pcie_regions_1, };
int warmboot;
/* Enable all 3 PCI_CLK_OUTPUTs. */
@ -119,6 +153,24 @@ void pci_init_board(void)
warmboot |= immr->pmc.pmccr1 & PMCCR1_POWER_OFF;
mpc83xx_pci_init(1, reg, warmboot);
/* Configure the clock for PCIE controller */
clrsetbits_be32(&clk->sccr, SCCR_PCIEXP1CM | SCCR_PCIEXP2CM,
SCCR_PCIEXP1CM_1 | SCCR_PCIEXP2CM_1);
/* Deassert the resets in the control register */
out_be32(&sysconf->pecr1, 0xE0008000);
out_be32(&sysconf->pecr2, 0xE0008000);
udelay(2000);
/* Configure PCI Express Local Access Windows */
out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR);
out_be32(&pcie_law[1].ar, LBLAWAR_EN | LBLAWAR_512MB);
mpc83xx_pcie_init(2, pcie_reg, warmboot);
}
#if defined(CONFIG_OF_BOARD_SETUP)

7
board/freescale/mpc8349emds/pci.c
View File

@ -171,15 +171,10 @@ void pci_init_board(void)
void pci_init_board(void)
{
volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
volatile pcictrl83xx_t *pci_ctrl = &immr->pci_ctrl[0];
struct pci_region *reg[] = { pci1_regions };
/* Enable all 8 PCI_CLK_OUTPUTS */
clk->occr = 0xff000000;
udelay(2000);
/* Configure PCI Local Access Windows */
pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
@ -187,8 +182,6 @@ void pci_init_board(void)
pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M;
udelay(2000);
mpc83xx_pci_init(1, reg, 0);
/* Configure PCI Inbound Translation Windows (3 1MB windows) */

6
board/freescale/mpc837xemds/mpc837xemds.c
View File

@ -18,6 +18,7 @@
#include <tsec.h>
#include <libfdt.h>
#include <fdt_support.h>
#include "pci.h"
#include "../common/pq-mds-pib.h"
int board_early_init_f(void)
@ -38,14 +39,10 @@ int board_early_init_f(void)
case SPR_8377:
fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX,
FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
break;
case SPR_8378:
fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SGMII,
FSL_SERDES_CLK_125, FSL_SERDES_VDD_1V);
fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX,
FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
break;
case SPR_8379:
fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
@ -316,6 +313,7 @@ void ft_board_setup(void *blob, bd_t *bd)
ft_pci_setup(blob, bd);
if (board_pci_host_broken())
ft_pci_fixup(blob, bd);
ft_pcie_fixup(blob, bd);
#endif
}
#endif /* CONFIG_OF_BOARD_SETUP */

89
board/freescale/mpc837xemds/pci.c
View File

@ -16,7 +16,9 @@
#include <mpc83xx.h>
#include <pci.h>
#include <i2c.h>
#include <fdt_support.h>
#include <asm/fsl_i2c.h>
#include <asm/fsl_serdes.h>
#if defined(CONFIG_PCI)
static struct pci_region pci_regions[] = {
@ -40,15 +42,59 @@ static struct pci_region pci_regions[] = {
}
};
static struct pci_region pcie_regions_0[] = {
{
.bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
.phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
.size = CONFIG_SYS_PCIE1_MEM_SIZE,
.flags = PCI_REGION_MEM,
},
{
.bus_start = CONFIG_SYS_PCIE1_IO_BASE,
.phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
.size = CONFIG_SYS_PCIE1_IO_SIZE,
.flags = PCI_REGION_IO,
},
};
static struct pci_region pcie_regions_1[] = {
{
.bus_start = CONFIG_SYS_PCIE2_MEM_BASE,
.phys_start = CONFIG_SYS_PCIE2_MEM_PHYS,
.size = CONFIG_SYS_PCIE2_MEM_SIZE,
.flags = PCI_REGION_MEM,
},
{
.bus_start = CONFIG_SYS_PCIE2_IO_BASE,
.phys_start = CONFIG_SYS_PCIE2_IO_PHYS,
.size = CONFIG_SYS_PCIE2_IO_SIZE,
.flags = PCI_REGION_IO,
},
};
static int is_pex_x2(void)
{
const char *pex_x2 = getenv("pex_x2");
if (pex_x2 && !strcmp(pex_x2, "yes"))
return 1;
return 0;
}
void pci_init_board(void)
{
volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
volatile sysconf83xx_t *sysconf = &immr->sysconf;
volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
volatile law83xx_t *pcie_law = sysconf->pcielaw;
struct pci_region *reg[] = { pci_regions };
struct pci_region *pcie_reg[] = { pcie_regions_0, pcie_regions_1, };
u32 spridr = in_be32(&immr->sysconf.spridr);
int pex2 = is_pex_x2();
if (board_pci_host_broken())
return;
goto skip_pci;
/* Enable all 5 PCI_CLK_OUTPUTS */
clk->occr |= 0xf8000000;
@ -64,5 +110,46 @@ void pci_init_board(void)
udelay(2000);
mpc83xx_pci_init(1, reg, 0);
skip_pci:
/* There is no PEX in MPC8379 parts. */
if (PARTID_NO_E(spridr) == SPR_8379)
return;
/* Configure the clock for PCIE controller */
clrsetbits_be32(&clk->sccr, SCCR_PCIEXP1CM | SCCR_PCIEXP2CM,
SCCR_PCIEXP1CM_1 | SCCR_PCIEXP2CM_1);
/* Deassert the resets in the control register */
out_be32(&sysconf->pecr1, 0xE0008000);
if (!pex2)
out_be32(&sysconf->pecr2, 0xE0008000);
udelay(2000);
/* Configure PCI Express Local Access Windows */
out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR);
out_be32(&pcie_law[1].ar, LBLAWAR_EN | LBLAWAR_512MB);
if (pex2)
fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX_X2,
FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
else
fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX,
FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
mpc83xx_pcie_init(pex2 ? 1 : 2, pcie_reg, 0);
}
void ft_pcie_fixup(void *blob, bd_t *bd)
{
const char *status = "disabled (PCIE1 is x2)";
if (!is_pex_x2())
return;
do_fixup_by_path(blob, "pci2", "status", status,
strlen(status) + 1, 1);
}
#endif /* CONFIG_PCI */

6
board/freescale/mpc837xemds/pci.h Normal file
View File

@ -0,0 +1,6 @@
#ifndef __BOARD_MPC837XEMDS_PCI_H
#define __BOARD_MPC837XEMDS_PCI_H
extern void ft_pcie_fixup(void *blob, bd_t *bd);
#endif /* __BOARD_MPC837XEMDS_PCI_H */

23
board/keymile/common/common.c
View File

@ -22,10 +22,14 @@
*/
#include <common.h>
#if defined(CONFIG_MGCOGE)
#include <mpc8260.h>
#endif
#include <ioports.h>
#include <malloc.h>
#include <hush.h>
#include <net.h>
#include <asm/io.h>
#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
#include <libfdt.h>
@ -33,8 +37,6 @@
#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
#include <i2c.h>
#endif
#include <asm/io.h>
extern int i2c_soft_read_pin (void);
@ -495,6 +497,7 @@ void i2c_init_board(void)
#endif
}
#endif
#endif
#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
int fdt_set_node_and_value (void *blob,
@ -521,3 +524,19 @@ int fdt_set_node_and_value (void *blob,
return ret;
}
#endif
int ethernet_present (void)
{
return (in_8((u8 *)CONFIG_SYS_PIGGY_BASE + CONFIG_SYS_SLOT_ID_OFF) & 0x80);
}
int board_eth_init (bd_t *bis)
{
#ifdef CONFIG_KEYMILE_HDLC_ENET
(void)keymile_hdlc_enet_initialize (bis);
#endif
if (ethernet_present ()) {
return -1;
}
return 0;
}

20
board/keymile/common/common.h Normal file
View File

@ -0,0 +1,20 @@
/*
* (C) Copyright 2008
* Heiko Schocher, DENX Software Engineering, hs@denx.de.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*/
#ifndef __KEYMILE_COMMON_H
#define __KEYMILE_COMMON_H
int ethernet_present (void);
int ivm_read_eeprom (void);
#ifdef CONFIG_KEYMILE_HDLC_ENET
int keymile_hdlc_enet_initialize (bd_t *bis);
#endif
#endif /* __KEYMILE_COMMON_H */

53
board/keymile/kmeter1/Makefile Normal file
View File

@ -0,0 +1,53 @@
#
# (C) Copyright 2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
ifneq ($(OBJTREE),$(SRCTREE))
$(shell mkdir -p $(obj)../common)
endif
LIB = $(obj)lib$(BOARD).a
COBJS += $(BOARD).o ../common/common.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
$(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak $(obj).depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

24
board/keymile/kmeter1/config.mk Normal file
View File

@ -0,0 +1,24 @@
#
# (C) Copyright 2008
# Heiko Schocher, DENX Software Engineering, hs@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
TEXT_BASE = 0xF0000000

158
board/keymile/kmeter1/kmeter1.c Normal file
View File

@ -0,0 +1,158 @@
/*
* Copyright (C) 2006 Freescale Semiconductor, Inc.
* Dave Liu <daveliu@freescale.com>
*
* Copyright (C) 2007 Logic Product Development, Inc.
* Peter Barada <peterb@logicpd.com>
*
* Copyright (C) 2007 MontaVista Software, Inc.
* Anton Vorontsov <avorontsov@ru.mvista.com>
*
* (C) Copyright 2008
* Heiko Schocher, DENX Software Engineering, hs@denx.de.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*/
#include <common.h>
#include <ioports.h>
#include <mpc83xx.h>
#include <i2c.h>
#include <miiphy.h>
#include <asm/io.h>
#include <asm/mmu.h>
#include <pci.h>
#include <libfdt.h>
#include "../common/common.h"
const qe_iop_conf_t qe_iop_conf_tab[] = {
/* port pin dir open_drain assign */
/* MDIO */
{0, 1, 3, 0, 2}, /* MDIO */
{0, 2, 1, 0, 1}, /* MDC */
/* UCC4 - UEC */
{1, 14, 1, 0, 1}, /* TxD0 */
{1, 15, 1, 0, 1}, /* TxD1 */
{1, 20, 2, 0, 1}, /* RxD0 */
{1, 21, 2, 0, 1}, /* RxD1 */
{1, 18, 1, 0, 1}, /* TX_EN */
{1, 26, 2, 0, 1}, /* RX_DV */
{1, 27, 2, 0, 1}, /* RX_ER */
{1, 24, 2, 0, 1}, /* COL */
{1, 25, 2, 0, 1}, /* CRS */
{2, 15, 2, 0, 1}, /* TX_CLK - CLK16 */
{2, 16, 2, 0, 1}, /* RX_CLK - CLK17 */
/* DUART - UART2 */
{5, 0, 1, 0, 2}, /* UART2_SOUT */
{5, 2, 1, 0, 1}, /* UART2_RTS */
{5, 3, 2, 0, 2}, /* UART2_SIN */
{5, 1, 2, 0, 3}, /* UART2_CTS */
/* END of table */
{0, 0, 0, 0, QE_IOP_TAB_END},
};
int board_early_init_r (void)
{
void *reg = (void *)(CONFIG_SYS_IMMR + 0x14a8);
u32 val;
/*
* Because of errata in the UCCs, we have to write to the reserved
* registers to slow the clocks down.
*/
val = in_be32 (reg);
/* UCC1 */
val |= 0x00003000;
/* UCC2 */
val |= 0x0c000000;
out_be32 (reg, val);
/* enable the PHY on the PIGGY */
setbits (8, (void *)(CONFIG_SYS_PIGGY_BASE + 0x10003), 0x01);
return 0;
}
int fixed_sdram(void)
{
volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
u32 msize = 0;
u32 ddr_size;
u32 ddr_size_log2;
msize = CONFIG_SYS_DDR_SIZE;
for (ddr_size = msize << 20, ddr_size_log2 = 0;
(ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) {
if (ddr_size & 1)
return -1;
}
im->sysconf.ddrlaw[0].ar =
LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
udelay (200);
im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
return msize;
}
phys_size_t initdram (int board_type)
{
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
extern void ddr_enable_ecc (unsigned int dram_size);
#endif
volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
u32 msize = 0;
if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
return -1;
/* DDR SDRAM - Main SODIMM */
im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
msize = fixed_sdram ();
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
/*
* Initialize DDR ECC byte
*/
ddr_enable_ecc (msize * 1024 * 1024);
#endif
/* return total bus SDRAM size(bytes) -- DDR */
return (msize * 1024 * 1024);
}
int checkboard (void)
{
puts ("Board: Keymile kmeter1");
if (ethernet_present ())
puts (" with PIGGY.");
puts ("\n");
return 0;
}
#if defined(CONFIG_OF_BOARD_SETUP)
void ft_board_setup (void *blob, bd_t *bd)
{
ft_cpu_setup (blob, bd);
}
#endif

10
board/keymile/mgcoge/mgcoge.c
View File

@ -25,6 +25,7 @@
#include <mpc8260.h>
#include <ioports.h>
#include <malloc.h>
#include <net.h>
#include <asm/io.h>
#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
@ -35,7 +36,8 @@
#include <i2c.h>
#endif
extern int ivm_read_eeprom (void);
#include "../common/common.h"
/*
* I/O Port configuration table
*
@ -285,8 +287,10 @@ phys_size_t initdram (int board_type)
int checkboard(void)
{
puts ("Board: mgcoge\n");
puts ("Board: Keymile mgcoge");
if (ethernet_present ())
puts (" with PIGGY.");
puts ("\n");
return 0;
}

8
board/keymile/mgsuvd/mgsuvd.c
View File

@ -22,13 +22,14 @@
*/
#include <common.h>
#include <mpc8xx.h>
#include <net.h>
#include <asm/io.h>
#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
#include <libfdt.h>
#endif
extern int ivm_read_eeprom (void);
#include "../common/common.h"
DECLARE_GLOBAL_DATA_PTR;
@ -60,7 +61,10 @@ const uint sdram_table[] =
int checkboard (void)
{
puts ("Board: Keymile mgsuvd\n");
puts ("Board: Keymile mgsuvd");
if (ethernet_present ())
puts (" with PIGGY.");
puts ("\n");
return (0);
}

50
board/sheldon/simpc8313/Makefile Normal file
View File

@ -0,0 +1,50 @@
#
# (C) Copyright 2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS := $(BOARD).o sdram.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
$(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak $(obj).depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

13
board/sheldon/simpc8313/config.mk Normal file
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@ -0,0 +1,13 @@
ifndef NAND_SPL
sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
endif
ifndef TEXT_BASE
TEXT_BASE = 0x00100000
endif
ifdef CONFIG_NAND_LP
PAD_TO = 0xFFF20000
else
PAD_TO = 0xFFF04000
endif

193
board/sheldon/simpc8313/sdram.c Normal file
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@ -0,0 +1,193 @@
/*
* Copyright (C) Freescale Semiconductor, Inc. 2006-2007
* Copyright (C) Sheldon Instruments, Inc. 2008
*
* Author: Ron Madrid <info@sheldoninst.com>
*
* (C) Copyright 2006
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <mpc83xx.h>
#include <spd_sdram.h>
#include <asm/bitops.h>
#include <asm/io.h>
#include <asm/processor.h>
#include <asm/mmu.h>
DECLARE_GLOBAL_DATA_PTR;
static long fixed_sdram(void);
#if defined(CONFIG_NAND_SPL)
void si_wait_i2c(void)
{
volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
while (!(__raw_readb(&im->i2c[0].sr) & 0x02))
;
__raw_writeb(0x00, &im->i2c[0].sr);
sync();
return;
}
void si_read_i2c(u32 lbyte, int count, u8 *buffer)
{
volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
u32 i;
u8 chip = 0x50 << 1; /* boot sequencer I2C */
u32 ubyte = (lbyte & 0xff00) >> 8;
lbyte &= 0xff;
/*
* Set up controller
*/
__raw_writeb(0x3f, &im->i2c[0].fdr);
__raw_writeb(0x00, &im->i2c[0].adr);
__raw_writeb(0x00, &im->i2c[0].sr);
__raw_writeb(0x00, &im->i2c[0].dr);
while (__raw_readb(&im->i2c[0].sr) & 0x20)
;
/*
* Writing address to device
*/
__raw_writeb(0xb0, &im->i2c[0].cr);
sync();
__raw_writeb(chip, &im->i2c[0].dr);
si_wait_i2c();
__raw_writeb(0xb0, &im->i2c[0].cr);
sync();
__raw_writeb(ubyte, &im->i2c[0].dr);
si_wait_i2c();
__raw_writeb(lbyte, &im->i2c[0].dr);
si_wait_i2c();
__raw_writeb(0xb4, &im->i2c[0].cr);
sync();
__raw_writeb(chip + 1, &im->i2c[0].dr);
si_wait_i2c();
__raw_writeb(0xa0, &im->i2c[0].cr);
sync();
/*
* Dummy read
*/
__raw_readb(&im->i2c[0].dr);
si_wait_i2c();
/*
* Read actual data
*/
for (i = 0; i < count; i++)
{
if (i == (count - 2)) /* Reached next to last byte, No ACK */
__raw_writeb(0xa8, &im->i2c[0].cr);
if (i == (count - 1)) /* Reached last byte, STOP */
__raw_writeb(0x88, &im->i2c[0].cr);
/* Read byte of data */
buffer[i] = __raw_readb(&im->i2c[0].dr);
if (i == (count - 1))
break;
si_wait_i2c();
}
return;
}
#endif /* CONFIG_NAND_SPL */
phys_size_t initdram(int board_type)
{
volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
volatile fsl_lbus_t *lbc= &im->lbus;
u32 msize;
if ((__raw_readl(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32) im)
return -1;
/* DDR SDRAM - Main SODIMM */
__raw_writel(CONFIG_SYS_DDR_BASE & LAWBAR_BAR, &im->sysconf.ddrlaw[0].bar);
msize = fixed_sdram();
/* Local Bus setup lbcr and mrtpr */
__raw_writel(CONFIG_SYS_LBC_LBCR, &lbc->lbcr);
__raw_writel(CONFIG_SYS_LBC_MRTPR, &lbc->mrtpr);
sync();
/* return total bus SDRAM size(bytes) -- DDR */
return (msize * 1024 * 1024);
}
/*************************************************************************
* fixed sdram init -- reads values from boot sequencer I2C
************************************************************************/
static long fixed_sdram(void)
{
volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
u32 msizelog2, msize = 1;
#if defined(CONFIG_NAND_SPL)
u32 i;
const u8 bytecount = 135;
u8 buffer[bytecount];
u32 addr, data;
si_read_i2c(0, bytecount, buffer);
for (i = 18; i < bytecount; i += 7){
addr = (u32)buffer[i];
addr <<= 8;
addr |= (u32)buffer[i + 1];
addr <<= 2;
data = (u32)buffer[i + 2];
data <<= 8;
data |= (u32)buffer[i + 3];
data <<= 8;
data |= (u32)buffer[i + 4];
data <<= 8;
data |= (u32)buffer[i + 5];
__raw_writel(data, (u32 *)(CONFIG_SYS_IMMR + addr));
}
sync();
/* enable DDR controller */
__raw_writel((__raw_readl(&im->ddr.sdram_cfg) | SDRAM_CFG_MEM_EN), &im->ddr.sdram_cfg);
#endif /* (CONFIG_NAND_SPL) */
msizelog2 = ((__raw_readl(&im->sysconf.ddrlaw[0].ar) & LAWAR_SIZE) + 1);
msize <<= (msizelog2 - 20);
return msize;
}

134
board/sheldon/simpc8313/simpc8313.c Normal file
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@ -0,0 +1,134 @@
/*
* Copyright (C) Freescale Semiconductor, Inc. 2006-2007
* Copyright (C) Sheldon Instruments, Inc. 2008
*
* Author: Ron Madrid <info@sheldoninst.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <libfdt.h>
#include <pci.h>
#include <mpc83xx.h>
#include <ns16550.h>
#include <nand.h>
DECLARE_GLOBAL_DATA_PTR;
int checkboard(void)
{
puts("Board: Sheldon Instruments SIMPC8313\n");
return 0;
}
#ifndef CONFIG_NAND_SPL
static struct pci_region pci_regions[] = {
{
bus_start: CONFIG_SYS_PCI1_MEM_BASE,
phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
size: CONFIG_SYS_PCI1_MEM_SIZE,
flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
},
{
bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
size: CONFIG_SYS_PCI1_MMIO_SIZE,
flags: PCI_REGION_MEM
},
{
bus_start: CONFIG_SYS_PCI1_IO_BASE,
phys_start: CONFIG_SYS_PCI1_IO_PHYS,
size: CONFIG_SYS_PCI1_IO_SIZE,
flags: PCI_REGION_IO
}
};
void pci_init_board(void)
{
volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
struct pci_region *reg[] = { pci_regions };
int warmboot;
/* Enable all 3 PCI_CLK_OUTPUTs. */
clk->occr |= 0xe0000000;
/*
* Configure PCI Local Access Windows
*/
pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
warmboot = gd->bd->bi_bootflags & BOOTFLAG_WARM;
mpc83xx_pci_init(1, reg, warmboot);
}
/*
* Miscellaneous late-boot configurations
*/
int misc_init_r(void)
{
int rc = 0;
return rc;
}
#if defined(CONFIG_OF_BOARD_SETUP)
void ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
#ifdef CONFIG_PCI
ft_pci_setup(blob, bd);
#endif
}
#endif
#else /* CONFIG_NAND_SPL */
void board_init_f(ulong bootflag)
{
NS16550_init((NS16550_t)(CONFIG_SYS_IMMR + 0x4500),
CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
puts("NAND boot... ");
init_timebase();
initdram(0);
relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000, (gd_t *)gd,
CONFIG_SYS_NAND_U_BOOT_RELOC);
}
void board_init_r(gd_t *gd, ulong dest_addr)
{
nand_boot();
}
void putc(char c)
{
if (gd->flags & GD_FLG_SILENT)
return;
if (c == '\n')
NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), '\r');
NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), c);
}
#endif

1
cpu/mpc83xx/Makefile
View File

@ -39,6 +39,7 @@ COBJS-y += ecc.o
COBJS-$(CONFIG_QE) += qe_io.o
COBJS-$(CONFIG_FSL_SERDES) += serdes.o
COBJS-$(CONFIG_83XX_GENERIC_PCI) += pci.o
COBJS-$(CONFIG_83XX_GENERIC_PCIE) += pcie.o
COBJS-$(CONFIG_OF_LIBFDT) += fdt.o
COBJS := $(COBJS-y)

5
cpu/mpc83xx/pci.c
View File

@ -118,10 +118,12 @@ static void pci_init_bus(int bus, struct pci_region *reg)
#ifdef CONFIG_PCI_SCAN_SHOW
printf("PCI: Bus Dev VenId DevId Class Int\n");
#endif
#ifndef CONFIG_PCISLAVE
/*
* Hose scan.
*/
hose->last_busno = pci_hose_scan(hose);
#endif
}
/*
@ -190,6 +192,9 @@ void mpc83xx_pcislave_unlock(int bus)
pci_hose_read_config_word (hose, dev, PCI_FUNCTION_CONFIG, &reg16);
reg16 &= ~(PCI_FUNCTION_CFG_LOCK);
pci_hose_write_config_word (hose, dev, PCI_FUNCTION_CONFIG, reg16);
/* The configuration bit is now unlocked, so we can scan the bus */
hose->last_busno = pci_hose_scan(hose);
}
#endif

314
cpu/mpc83xx/pcie.c Normal file
View File

@ -0,0 +1,314 @@
/*
* Copyright (C) 2007-2009 Freescale Semiconductor, Inc.
* Copyright (C) 2008-2009 MontaVista Software, Inc.
*
* Authors: Tony Li <tony.li@freescale.com>
* Anton Vorontsov <avorontsov@ru.mvista.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <pci.h>
#include <mpc83xx.h>
#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
#define PCIE_MAX_BUSES 2
#ifdef CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES
static int mpc83xx_pcie_remap_cfg(struct pci_controller *hose, pci_dev_t dev)
{
int bus = PCI_BUS(dev) - hose->first_busno;
immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
pex83xx_t *pex = &immr->pciexp[bus];
struct pex_outbound_window *out_win = &pex->bridge.pex_outbound_win[0];
u8 devfn = PCI_DEV(dev) << 3 | PCI_FUNC(dev);
u32 dev_base = bus << 24 | devfn << 16;
if (hose->indirect_type == INDIRECT_TYPE_NO_PCIE_LINK)
return -1;
/*
* Workaround for the HW bug: for Type 0 configure transactions the
* PCI-E controller does not check the device number bits and just
* assumes that the device number bits are 0.
*/
if (devfn & 0xf8)
return -1;
out_le32(&out_win->tarl, dev_base);
return 0;
}
#define cfg_read(val, addr, type, op) \
do { *val = op((type)(addr)); } while (0)
#define cfg_write(val, addr, type, op) \
do { op((type *)(addr), (val)); } while (0)
#define PCIE_OP(rw, size, type, op) \
static int pcie_##rw##_config_##size(struct pci_controller *hose, \
pci_dev_t dev, int offset, \
type val) \
{ \
int ret; \
\
ret = mpc83xx_pcie_remap_cfg(hose, dev); \
if (ret) \
return ret; \
cfg_##rw(val, (void *)hose->cfg_addr + offset, type, op); \
return 0; \
}
PCIE_OP(read, byte, u8 *, in_8)
PCIE_OP(read, word, u16 *, in_le16)
PCIE_OP(read, dword, u32 *, in_le32)
PCIE_OP(write, byte, u8, out_8)
PCIE_OP(write, word, u16, out_le16)
PCIE_OP(write, dword, u32, out_le32)
static void mpc83xx_pcie_register_hose(int bus, struct pci_region *reg,
u8 link)
{
extern void disable_addr_trans(void); /* start.S */
static struct pci_controller pcie_hose[PCIE_MAX_BUSES];
static int max_bus;
struct pci_controller *hose = &pcie_hose[bus];
int i;
/*
* There are no spare BATs to remap all PCI-E windows for U-Boot, so
* disable translations. In general, this is not great solution, and
* that's why we don't register PCI-E hoses by default.
*/
disable_addr_trans();
for (i = 0; i < 2; i++, reg++) {
if (reg->size == 0)
break;
hose->regions[i] = *reg;
hose->region_count++;
}
i = hose->region_count++;
hose->regions[i].bus_start = 0;
hose->regions[i].phys_start = 0;
hose->regions[i].size = gd->ram_size;
hose->regions[i].flags = PCI_REGION_MEM | PCI_REGION_MEMORY;
i = hose->region_count++;
hose->regions[i].bus_start = CONFIG_SYS_IMMR;
hose->regions[i].phys_start = CONFIG_SYS_IMMR;
hose->regions[i].size = 0x100000;
hose->regions[i].flags = PCI_REGION_MEM | PCI_REGION_MEMORY;
hose->first_busno = max_bus;
hose->last_busno = 0xff;
if (bus == 0)
hose->cfg_addr = (unsigned int *)CONFIG_SYS_PCIE1_CFG_BASE;
else
hose->cfg_addr = (unsigned int *)CONFIG_SYS_PCIE2_CFG_BASE;
pci_set_ops(hose,
pcie_read_config_byte,
pcie_read_config_word,
pcie_read_config_dword,
pcie_write_config_byte,
pcie_write_config_word,
pcie_write_config_dword);
if (!link)
hose->indirect_type = INDIRECT_TYPE_NO_PCIE_LINK;
pci_register_hose(hose);
#ifdef CONFIG_PCI_SCAN_SHOW
printf("PCI: Bus Dev VenId DevId Class Int\n");
#endif
/*
* Hose scan.
*/
hose->last_busno = pci_hose_scan(hose);
max_bus = hose->last_busno + 1;
}
#else
static void mpc83xx_pcie_register_hose(int bus, struct pci_region *reg,
u8 link) {}
#endif /* CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES */
static void mpc83xx_pcie_init_bus(int bus, struct pci_region *reg)
{
immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
pex83xx_t *pex = &immr->pciexp[bus];
struct pex_outbound_window *out_win;
struct pex_inbound_window *in_win;
void *hose_cfg_base;
unsigned int ram_sz;
unsigned int barl;
unsigned int tar;
u16 reg16;
int i;
/* Enable pex csb bridge inbound & outbound transactions */
out_le32(&pex->bridge.pex_csb_ctrl,
in_le32(&pex->bridge.pex_csb_ctrl) | PEX_CSB_CTRL_OBPIOE |
PEX_CSB_CTRL_IBPIOE);
/* Enable bridge outbound */
out_le32(&pex->bridge.pex_csb_obctrl, PEX_CSB_OBCTRL_PIOE |
PEX_CSB_OBCTRL_MEMWE | PEX_CSB_OBCTRL_IOWE |
PEX_CSB_OBCTRL_CFGWE);
out_win = &pex->bridge.pex_outbound_win[0];
if (bus) {
out_le32(&out_win->ar, PEX_OWAR_EN | PEX_OWAR_TYPE_CFG |
CONFIG_SYS_PCIE2_CFG_SIZE);
out_le32(&out_win->bar, CONFIG_SYS_PCIE2_CFG_BASE);
} else {
out_le32(&out_win->ar, PEX_OWAR_EN | PEX_OWAR_TYPE_CFG |
CONFIG_SYS_PCIE1_CFG_SIZE);
out_le32(&out_win->bar, CONFIG_SYS_PCIE1_CFG_BASE);
}
out_le32(&out_win->tarl, 0);
out_le32(&out_win->tarh, 0);
for (i = 0; i < 2; i++, reg++) {
u32 ar;
if (reg->size == 0)
break;
out_win = &pex->bridge.pex_outbound_win[i + 1];
out_le32(&out_win->bar, reg->phys_start);
out_le32(&out_win->tarl, reg->bus_start);
out_le32(&out_win->tarh, 0);
ar = PEX_OWAR_EN | (reg->size & PEX_OWAR_SIZE);
if (reg->flags & PCI_REGION_IO)
ar |= PEX_OWAR_TYPE_IO;
else
ar |= PEX_OWAR_TYPE_MEM;
out_le32(&out_win->ar, ar);
}
out_le32(&pex->bridge.pex_csb_ibctrl, PEX_CSB_IBCTRL_PIOE);
ram_sz = gd->ram_size;
barl = 0;
tar = 0;
i = 0;
while (ram_sz > 0) {
in_win = &pex->bridge.pex_inbound_win[i];
out_le32(&in_win->barl, barl);
out_le32(&in_win->barh, 0x0);
out_le32(&in_win->tar, tar);
if (ram_sz >= 0x10000000) {
/* The maxium windows size is 256M */
out_le32(&in_win->ar, PEX_IWAR_EN | PEX_IWAR_NSOV |
PEX_IWAR_TYPE_PF | 0x0FFFF000);
barl += 0x10000000;
tar += 0x10000000;
ram_sz -= 0x10000000;
} else {
/* The UM is not clear here.
* So, round up to even Mb boundary */
ram_sz = ram_sz >> (20 +
((ram_sz & 0xFFFFF) ? 1 : 0));
if (!(ram_sz % 2))
ram_sz -= 1;
out_le32(&in_win->ar, PEX_IWAR_EN | PEX_IWAR_NSOV |
PEX_IWAR_TYPE_PF | (ram_sz << 20) | 0xFF000);
ram_sz = 0;
}
i++;
}
in_win = &pex->bridge.pex_inbound_win[i];
out_le32(&in_win->barl, CONFIG_SYS_IMMR);
out_le32(&in_win->barh, 0);
out_le32(&in_win->tar, CONFIG_SYS_IMMR);
out_le32(&in_win->ar, PEX_IWAR_EN |
PEX_IWAR_TYPE_NO_PF | PEX_IWAR_SIZE_1M);
/* Enable the host virtual INTX interrupts */
out_le32(&pex->bridge.pex_int_axi_misc_enb,
in_le32(&pex->bridge.pex_int_axi_misc_enb) | 0x1E0);
/* Hose configure header is memory-mapped */
hose_cfg_base = (void *)pex;
get_clocks();
/* Configure the PCIE controller core clock ratio */
out_le32(hose_cfg_base + PEX_GCLK_RATIO,
(((bus ? gd->pciexp2_clk : gd->pciexp1_clk) / 1000000) * 16)
/ 333);
udelay(1000000);
/* Do Type 1 bridge configuration */
out_8(hose_cfg_base + PCI_PRIMARY_BUS, 0);
out_8(hose_cfg_base + PCI_SECONDARY_BUS, 1);
out_8(hose_cfg_base + PCI_SUBORDINATE_BUS, 255);
/*
* Write to Command register
*/
reg16 = in_le16(hose_cfg_base + PCI_COMMAND);
reg16 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO |
PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
out_le16(hose_cfg_base + PCI_COMMAND, reg16);
/*
* Clear non-reserved bits in status register.
*/
out_le16(hose_cfg_base + PCI_STATUS, 0xffff);
out_8(hose_cfg_base + PCI_LATENCY_TIMER, 0x80);
out_8(hose_cfg_base + PCI_CACHE_LINE_SIZE, 0x08);
printf("PCIE%d: ", bus);
reg16 = in_le16(hose_cfg_base + PCI_LTSSM);
if (reg16 >= PCI_LTSSM_L0)
printf("link\n");
else
printf("No link\n");
mpc83xx_pcie_register_hose(bus, reg, reg16 >= PCI_LTSSM_L0);
}
/*
* The caller must have already set SCCR, SERDES and the PCIE_LAW BARs
* must have been set to cover all of the requested regions.
*/
void mpc83xx_pcie_init(int num_buses, struct pci_region **reg, int warmboot)
{
int i;
/*
* Release PCI RST Output signal.
* Power on to RST high must be at least 100 ms as per PCI spec.
* On warm boots only 1 ms is required.
*/
udelay(warmboot ? 1000 : 100000);
for (i = 0; i < num_buses; i++)
mpc83xx_pcie_init_bus(i, reg[i]);
}

4
cpu/mpc83xx/speed.c
View File

@ -132,7 +132,7 @@ int get_clocks(void)
u32 qe_clk;
u32 brg_clk;
#endif
#if defined(CONFIG_MPC837X)
#if defined(CONFIG_MPC837X) || defined(CONFIG_MPC831X)
u32 pciexp1_clk;
u32 pciexp2_clk;
#endif
@ -328,7 +328,7 @@ int get_clocks(void)
i2c2_clk = csb_clk; /* i2c-2 clk is equal to csb clk */
#endif
#if defined(CONFIG_MPC837X)
#if defined(CONFIG_MPC837X) || defined(CONFIG_MPC831X)
switch ((sccr & SCCR_PCIEXP1CM) >> SCCR_PCIEXP1CM_SHIFT) {
case 0:
pciexp1_clk = 0;

95
cpu/mpc83xx/start.S
View File

@ -109,6 +109,45 @@ version_string:
.ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
.ascii " ", CONFIG_IDENT_STRING, "\0"
.align 2
.globl enable_addr_trans
enable_addr_trans:
/* enable address translation */
mfmsr r5
ori r5, r5, (MSR_IR | MSR_DR)
mtmsr r5
isync
blr
.globl disable_addr_trans
disable_addr_trans:
/* disable address translation */
mflr r4
mfmsr r3
andi. r0, r3, (MSR_IR | MSR_DR)
beqlr
andc r3, r3, r0
mtspr SRR0, r4
mtspr SRR1, r3
rfi
.globl get_pvr
get_pvr:
mfspr r3, PVR
blr
.globl ppcDWstore
ppcDWstore:
lfd 1, 0(r4)
stfd 1, 0(r3)
blr
.globl ppcDWload
ppcDWload:
lfd 1, 0(r3)
stfd 1, 0(r4)
blr
#ifndef CONFIG_DEFAULT_IMMR
#error CONFIG_DEFAULT_IMMR must be defined
@ -161,9 +200,23 @@ boot_cold: /* time t 3 */
nop
boot_warm: /* time t 5 */
mfmsr r5 /* save msr contents */
/* 83xx manuals prescribe a specific sequence for updating IMMRBAR. */
bl 1f
1: mflr r7
lis r3, CONFIG_SYS_IMMR@h
ori r3, r3, CONFIG_SYS_IMMR@l
lwz r6, IMMRBAR(r4)
isync
stw r3, IMMRBAR(r4)
lwz r6, 0(r7) /* Arbitrary external load */
isync
lwz r6, IMMRBAR(r3)
isync
/* Initialise the E300 processor core */
/*------------------------------------------*/
@ -173,9 +226,7 @@ boot_warm: /* time t 5 */
* is loaded. Wait for the rest before branching
* to another flash page.
*/
addi r7, r3, 0x50b0
1: dcbi 0, r7
lwz r6, 0(r7)
1: lwz r6, 0x50b0(r3)
andi. r6, r6, 1
beq 1b
#endif
@ -698,27 +749,6 @@ setup_bats:
blr
.globl enable_addr_trans
enable_addr_trans:
/* enable address translation */
mfmsr r5
ori r5, r5, (MSR_IR | MSR_DR)
mtmsr r5
isync
blr
.globl disable_addr_trans
disable_addr_trans:
/* disable address translation */
mflr r4
mfmsr r3
andi. r0, r3, (MSR_IR | MSR_DR)
beqlr
andc r3, r3, r0
mtspr SRR0, r4
mtspr SRR1, r3
rfi
/* Cache functions.
*
* Note: requires that all cache bits in
@ -796,23 +826,6 @@ flush_dcache:
b 1b
2: blr
.globl get_pvr
get_pvr:
mfspr r3, PVR
blr
.globl ppcDWstore
ppcDWstore:
lfd 1, 0(r4)
stfd 1, 0(r3)
blr
.globl ppcDWload
ppcDWload:
lfd 1, 0(r3)
stfd 1, 0(r4)
blr
/*-------------------------------------------------------------------*/
/*

91
doc/README.kmeter1 Normal file
View File

@ -0,0 +1,91 @@
Keymile kmeter1 Board
-----------------------------------------
1. Alternative Boot EEPROM
Upon the kmeter1 startup the I2C_1 controller is used to fetch the boot
configuration from a serial EEPROM. During the development and debugging
phase it might be helpful to apply an alternative boot configuration in
a simple way. Therefore it is an alternative boot eeprom on the PIGGY,
which can be activated by setting the "ST" jumper on the PIGGY board.
2. Memory Map
BaseAddr PortSz Size Device
----------- ------ ----- ------
0x0000_0000 64 bit 256MB DDR
0x8000_0000 8 bit 256KB GPIO/PIGGY on CS1
0xa000_0000 8 bit 256MB PAXE on CS3
0xe000_0000 2MB Int Mem Reg Space
0xf000_0000 16 bit 256MB FLASH on CS0
DDR-SDRAM:
The current realization is made with four 16-bits memory devices.
Mounting options have been foreseen for device architectures from
4Mx16 to 512Mx16. The kmeter1 is equipped with four 32Mx16 devices
thus resulting in a total capacity of 256MBytes.
3. Compilation
Assuming you're using BASH shell:
export CROSS_COMPILE=your-cross-compile-prefix
cd u-boot
make distclean
make kmeter1_config
make
4. Downloading and Flashing Images
4.0 Download over serial line using Kermit:
loadb
[Drop to kermit:
^\c
send <u-boot-bin-image>
c
]
Or via tftp:
tftp 10000 u-boot.bin
=> run load
Using FSL UEC0 device
TFTP from server 192.168.1.1; our IP address is 192.168.205.4
Filename '/tftpboot/kmeter1/u-boot.bin'.
Load address: 0x200000
Loading: ##############
done
Bytes transferred = 204204 (31dac hex)
=>
4.1 Reflash U-boot Image using U-boot
=> run update
..... done
Un-Protected 5 sectors
..... done
Erased 5 sectors
Copy to Flash... done
..... done
Protected 5 sectors
Total of 204204 bytes were the same
Saving Environment to Flash...
. done
Un-Protected 1 sectors
. done
Un-Protected 1 sectors
Erasing Flash...
. done
Erased 1 sectors
Writing to Flash... done
. done
Protected 1 sectors
. done
Protected 1 sectors
=>
5. Notes
1) The console baudrate for kmeter1 is 115200bps.

80
doc/README.simpc8313 Normal file
View File

@ -0,0 +1,80 @@
Sheldon Instruments SIMPC8313 Board
-----------------------------------------
1. Board Switches and Jumpers
S2 is used to set CFG_RESET_SOURCE.
To boot the image in Large page NAND flash, use these DIP
switch settings for S2:
+----------+ ON
| * * **** |
| * * |
+----------+
12345678
To boot the image in Small page NAND flash, use these DIP
switch settings for S2:
+----------+ ON
| *** **** |
| * |
+----------+
12345678
(where the '*' indicates the position of the tab of the switch.)
2. Memory Map
The memory map looks like this:
0x0000_0000 0x1fff_ffff DDR 512M
0x8000_0000 0x8fff_ffff PCI MEM 256M
0x9000_0000 0x9fff_ffff PCI_MMIO 256M
0xe000_0000 0xe00f_ffff IMMR 1M
0xe200_0000 0xe20f_ffff PCI IO 16M
0xe280_0000 0xe280_7fff NAND FLASH (CS0) 32K
or
0xe280_0000 0xe281_ffff NAND FLASH (CS0) 128K
0xff00_0000 0xff00_7fff FPGA (CS1) 1M
3. Compilation
Assuming you're using BASH (or similar) as your shell:
export CROSS_COMPILE=your-cross-compiler-prefix-
make distclean
make SIMPC8313_LP_config
(or make SIMPC8313_SP_config, depending on the page size
of your NAND flash)
make
4. Downloading and Flashing Images
4.1 Reflash U-boot Image using U-boot
=>run update_uboot
You may want to try
=>tftp $loadaddr $uboot
first, to make sure that the TFTP load will succeed before it
goes ahead and wipes out your current firmware. And of course,
if the new u-boot doesn't boot, you can plug the board into
your PCI slot and with the supplied driver and sample app
you can reburn a working u-boot.
4.2 Downloading and Booting Linux Kernel
Ensure that all networking-related environment variables are set
properly (including ipaddr, serverip, gatewayip (if needed),
netmask, ethaddr, eth1addr, fdtfile, and bootfile).
=>tftp $loadaddr uImage
=>nand write $loadaddr kernel $filesize
=>tftp $loadaddr $fdtfile
=>nand write $loadaddr 7e0000 1800
=>boot
5 Notes
The console baudrate for SIMPC8313 is 115200bps.

2
include/asm-ppc/global_data.h
View File

@ -75,7 +75,7 @@ typedef struct global_data {
u32 lbiu_clk;
u32 lclk_clk;
u32 pci_clk;
#if defined(CONFIG_MPC837X)
#if defined(CONFIG_MPC837X) || defined(CONFIG_MPC831X)
u32 pciexp1_clk;
u32 pciexp2_clk;
#endif

119
include/asm-ppc/immap_83xx.h
View File

@ -52,23 +52,28 @@ typedef struct sysconf83xx {
law83xx_t lblaw[4]; /* LBIU local access window */
u8 res2[0x20];
law83xx_t pcilaw[2]; /* PCI local access window */
u8 res3[0x30];
u8 res3[0x10];
law83xx_t pcielaw[2]; /* PCI Express local access window */
u8 res4[0x10];
law83xx_t ddrlaw[2]; /* DDR local access window */
u8 res4[0x50];
u8 res5[0x50];
u32 sgprl; /* System General Purpose Register Low */
u32 sgprh; /* System General Purpose Register High */
u32 spridr; /* System Part and Revision ID Register */
u8 res5[0x04];
u8 res6[0x04];
u32 spcr; /* System Priority Configuration Register */
u32 sicrl; /* System I/O Configuration Register Low */
u32 sicrh; /* System I/O Configuration Register High */
u8 res6[0x04];
u8 res7[0x04];
u32 sidcr0; /* System I/O Delay Configuration Register 0 */
u32 sidcr1; /* System I/O Delay Configuration Register 1 */
u32 ddrcdr; /* DDR Control Driver Register */
u32 ddrdsr; /* DDR Debug Status Register */
u32 obir; /* Output Buffer Impedance Register */
u8 res7[0xCC];
u8 res8[0xC];
u32 pecr1; /* PCI Express control register 1 */
u32 pecr2; /* PCI Express control register 2 */
u8 res9[0xB8];
} sysconf83xx_t;
/*
@ -503,8 +508,110 @@ typedef struct security83xx {
/*
* PCI Express
*/
struct pex_inbound_window {
u32 ar;
u32 tar;
u32 barl;
u32 barh;
};
struct pex_outbound_window {
u32 ar;
u32 bar;
u32 tarl;
u32 tarh;
};
struct pex_csb_bridge {
u32 pex_csb_ver;
u32 pex_csb_cab;
u32 pex_csb_ctrl;
u8 res0[8];
u32 pex_dms_dstmr;
u8 res1[4];
u32 pex_cbs_stat;
u8 res2[0x20];
u32 pex_csb_obctrl;
u32 pex_csb_obstat;
u8 res3[0x98];
u32 pex_csb_ibctrl;
u32 pex_csb_ibstat;
u8 res4[0xb8];
u32 pex_wdma_ctrl;
u32 pex_wdma_addr;
u32 pex_wdma_stat;
u8 res5[0x94];
u32 pex_rdma_ctrl;
u32 pex_rdma_addr;
u32 pex_rdma_stat;
u8 res6[0xd4];
u32 pex_ombcr;
u32 pex_ombdr;
u8 res7[0x38];
u32 pex_imbcr;
u32 pex_imbdr;
u8 res8[0x38];
u32 pex_int_enb;
u32 pex_int_stat;
u32 pex_int_apio_vec1;
u32 pex_int_apio_vec2;
u8 res9[0x10];
u32 pex_int_ppio_vec1;
u32 pex_int_ppio_vec2;
u32 pex_int_wdma_vec1;
u32 pex_int_wdma_vec2;
u32 pex_int_rdma_vec1;
u32 pex_int_rdma_vec2;
u32 pex_int_misc_vec;
u8 res10[4];
u32 pex_int_axi_pio_enb;
u32 pex_int_axi_wdma_enb;
u32 pex_int_axi_rdma_enb;
u32 pex_int_axi_misc_enb;
u32 pex_int_axi_pio_stat;
u32 pex_int_axi_wdma_stat;
u32 pex_int_axi_rdma_stat;
u32 pex_int_axi_misc_stat;
u8 res11[0xa0];
struct pex_outbound_window pex_outbound_win[4];
u8 res12[0x100];
u32 pex_epiwtar0;
u32 pex_epiwtar1;
u32 pex_epiwtar2;
u32 pex_epiwtar3;
u8 res13[0x70];
struct pex_inbound_window pex_inbound_win[4];
};
typedef struct pex83xx {
u8 fixme[0x1000];
u8 pex_cfg_header[0x404];
u32 pex_ltssm_stat;
u8 res0[0x30];
u32 pex_ack_replay_timeout;
u8 res1[4];
u32 pex_gclk_ratio;
u8 res2[0xc];
u32 pex_pm_timer;
u32 pex_pme_timeout;
u8 res3[4];
u32 pex_aspm_req_timer;
u8 res4[0x18];
u32 pex_ssvid_update;
u8 res5[0x34];
u32 pex_cfg_ready;
u8 res6[0x24];
u32 pex_bar_sizel;
u8 res7[4];
u32 pex_bar_sel;
u8 res8[0x20];
u32 pex_bar_pf;
u8 res9[0x88];
u32 pex_pme_to_ack_tor;
u8 res10[0xc];
u32 pex_ss_intr_mask;
u8 res11[0x25c];
struct pex_csb_bridge bridge;
u8 res12[0x160];
} pex83xx_t;
/*

21
include/configs/MPC8315ERDB.h
View File

@ -309,8 +309,29 @@
#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000
#define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000
#define CONFIG_SYS_PCIE1_BASE 0xA0000000
#define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000
#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
#define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000
#define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000
#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
#define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000
#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
#define CONFIG_SYS_PCIE2_BASE 0xC0000000
#define CONFIG_SYS_PCIE2_MEM_BASE 0xC0000000
#define CONFIG_SYS_PCIE2_MEM_PHYS 0xC0000000
#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000
#define CONFIG_SYS_PCIE2_CFG_BASE 0xD0000000
#define CONFIG_SYS_PCIE2_CFG_SIZE 0x01000000
#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000
#define CONFIG_SYS_PCIE2_IO_PHYS 0xD1000000
#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000
#define CONFIG_PCI
#define CONFIG_83XX_GENERIC_PCI 1 /* Use generic PCI setup */
#define CONFIG_83XX_GENERIC_PCIE 1
#define CONFIG_NET_MULTI
#define CONFIG_PCI_PNP /* do pci plug-and-play */

21
include/configs/MPC837XEMDS.h
View File

@ -353,11 +353,32 @@
#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000
#define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000
#define CONFIG_SYS_PCIE1_BASE 0xA0000000
#define CONFIG_SYS_PCIE1_CFG_BASE 0xA0000000
#define CONFIG_SYS_PCIE1_CFG_SIZE 0x08000000
#define CONFIG_SYS_PCIE1_MEM_BASE 0xA8000000
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA8000000
#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
#define CONFIG_SYS_PCIE1_IO_PHYS 0xB8000000
#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
#define CONFIG_SYS_PCIE2_BASE 0xC0000000
#define CONFIG_SYS_PCIE2_CFG_BASE 0xC0000000
#define CONFIG_SYS_PCIE2_CFG_SIZE 0x08000000
#define CONFIG_SYS_PCIE2_MEM_BASE 0xC8000000
#define CONFIG_SYS_PCIE2_MEM_PHYS 0xC8000000
#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000
#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000
#define CONFIG_SYS_PCIE2_IO_PHYS 0xD8000000
#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000
#ifdef CONFIG_PCI
#ifndef __ASSEMBLY__
extern int board_pci_host_broken(void);
#endif
#define CONFIG_83XX_GENERIC_PCI 1 /* Use generic PCI setup */
#define CONFIG_83XX_GENERIC_PCIE 1
#define CONFIG_PQ_MDS_PIB 1 /* PQ MDS Platform IO Board */
#define CONFIG_HAS_FSL_DR_USB 1 /* fixup device tree for the DR USB */

544
include/configs/SIMPC8313.h Normal file
View File

@ -0,0 +1,544 @@
/*
* Copyright (C) Sheldon Instruments, Inc. 2008
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* simpc8313 board configuration file
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*
* High Level Configuration Options
*/
#define CONFIG_NAND_U_BOOT
#define CONFIG_E300 1
#define CONFIG_MPC83XX 1
#define CONFIG_MPC831X 1
#define CONFIG_MPC8313 1
#define CONFIG_PCI
#define CONFIG_83XX_GENERIC_PCI
#define CONFIG_MISC_INIT_R
/*
* On-board devices
*
* TSEC1 is Marvell PHY 88E1118
*/
#define CONFIG_SYS_33MHZ
#define CONFIG_83XX_CLKIN 33333333 /* in Hz */
#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
#define CONFIG_SYS_IMMR 0xE0000000
#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
#define CONFIG_DEFAULT_IMMR CONFIG_SYS_IMMR
#endif
#define CONFIG_SYS_MEMTEST_START 0x00001000
#define CONFIG_SYS_MEMTEST_END 0x07f00000
#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
/*
* Device configurations
*/
#define CONFIG_TSEC1
/*
* DDR Setup
*/
#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
#define CONFIG_VERY_BIG_RAM
#define CONFIG_MAX_MEM_MAPPED (512 << 20)
#define CONFIG_SYS_DDRCDR ( DDRCDR_EN \
| DDRCDR_PZ_NOMZ \
| DDRCDR_NZ_NOMZ \
| DDRCDR_M_ODR )
/* 0x73000002 TODO ODR & DRN ? */
/*
* FLASH on the Local Bus
*/
#define CONFIG_SYS_NO_FLASH
#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
#if !defined(CONFIG_NAND_SPL)
#define CONFIG_SYS_RAMBOOT
#endif
#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */
#define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM*/
#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
/*
* Local Bus LCRR and LBCR regs
*/
#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_EADC_1 | LCRR_CLKDIV_2)
#define CONFIG_SYS_LBC_LBCR (0x00040000 /* TODO */ \
| (0xFF << LBCR_BMT_SHIFT) \
| 0xF ) /* 0x0004ff0f */
#define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32 */
/* drivers/mtd/nand/nand.c */
#ifdef CONFIG_NAND_SPL
#define CONFIG_SYS_NAND_BASE 0xFFF00000
#else
#define CONFIG_SYS_NAND_BASE 0xE2800000
#endif
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define NAND_MAX_CHIPS 1
#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CONFIG_CMD_NAND 1
#define CONFIG_NAND_FSL_ELBC 1
#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
#define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000
#define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
#define CONFIG_SYS_NAND_BR_PRELIM ( CONFIG_SYS_NAND_BASE \
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
| BR_PS_8 /* Port Size = 8 bit */ \
| BR_MS_FCM /* MSEL = FCM */ \
| BR_V ) /* valid */
#ifdef CONFIG_NAND_SP
#define CONFIG_SYS_NAND_OR_PRELIM ( 0xFFFF8000 /* length 32K */ \
| OR_FCM_CSCT \
| OR_FCM_CST \
| OR_FCM_CHT \
| OR_FCM_SCY_1 \
| OR_FCM_TRLX \
| OR_FCM_EHTR )
#define CONFIG_SYS_LBLAWAR0_PRELIM 0x8000000E /* 32KB */
#define CONFIG_SYS_NAND_PAGE_SIZE (512) /* NAND chip page size */
#define CONFIG_SYS_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */
#define NAND_CACHE_PAGES 32
#elif defined(CONFIG_NAND_LP)
#define CONFIG_SYS_NAND_OR_PRELIM ( 0xFFFC0000 /* length 256K */ \
| OR_FCM_PGS \
| OR_FCM_CSCT \
| OR_FCM_CST \
| OR_FCM_CHT \
| OR_FCM_SCY_1 \
| OR_FCM_TRLX \
| OR_FCM_EHTR )
#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000011 /* 256KB */
#define CONFIG_SYS_NAND_PAGE_SIZE (2048) /* NAND chip page size */
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10) /* NAND chip block size */
#define NAND_CACHE_PAGES 64
#else
#error Page size of NAND not defined.
#endif /* CONFIG_NAND_SP */
#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SYS_NAND_BLOCK_SIZE
#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM
#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM
#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_NAND_BASE
#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR0_PRELIM
#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR0_PRELIM
/*
* JFFS2 configuration
*/
#define CONFIG_JFFS2_NAND
#define CONFIG_JFFS2_DEV "nand0"
/* mtdparts command line support */
#define CONFIG_JFFS2_CMDLINE
#define MTDIDS_DEFAULT "nand0=nand0"
#define MTDPARTS_DEFAULT "mtdparts=nand0:2M(u-boot),6M(kernel),-(jffs2)"
/* pass open firmware flat tree */
#define CONFIG_OF_LIBFDT 1
#define CONFIG_OF_BOARD_SETUP 1
#define CONFIG_OF_STDOUT_VIA_ALIAS 1
/*
* Serial Port
*/
#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
/* Use the HUSH parser */
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
/* I2C */
#define CONFIG_HARD_I2C /* I2C with hardware support*/
#define CONFIG_FSL_I2C
#define CONFIG_I2C_MULTI_BUS
#define CONFIG_I2C_CMD_TREE
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
#define CONFIG_SYS_I2C_SLAVE 0x7F
#define CONFIG_SYS_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */
#define CONFIG_SYS_I2C_OFFSET 0x3000
#define CONFIG_SYS_I2C2_OFFSET 0x3100
/*
* General PCI
* Addresses are mapped 1-1.
*/
#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
#define CONFIG_PCI_PNP /* do pci plug-and-play */
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
/*
* TSEC
*/
#define CONFIG_TSEC_ENET /* TSEC ethernet support */
#define CONFIG_NET_MULTI
#define CONFIG_GMII /* MII PHY management */
#ifdef CONFIG_TSEC1
#define CONFIG_HAS_ETH0
#define CONFIG_TSEC1_NAME "TSEC0"
#define CONFIG_SYS_TSEC1_OFFSET 0x24000
#define TSEC1_PHY_ADDR 0x0
#define TSEC1_FLAGS TSEC_GIGABIT
#define TSEC1_PHYIDX 0
#endif
#ifdef CONFIG_TSEC2
#define CONFIG_HAS_ETH1
#define CONFIG_TSEC2_NAME "TSEC1"
#define CONFIG_SYS_TSEC2_OFFSET 0x25000
#define TSEC2_PHY_ADDR 4
#define TSEC2_FLAGS TSEC_GIGABIT
#define TSEC2_PHYIDX 0
#endif
/* Options are: TSEC[0-1] */
#define CONFIG_ETHPRIME "TSEC1"
/*
* Configure on-board RTC
*/
#define CONFIG_RTC_DS1337
#define CONFIG_SYS_I2C_RTC_ADDR 0x68
/*
* Environment
*/
#if defined(CONFIG_NAND_U_BOOT)
#define CONFIG_ENV_IS_IN_NAND 1
#define CONFIG_ENV_OFFSET (768 * 1024)
#define CONFIG_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
#define CONFIG_ENV_RANGE (CONFIG_ENV_SECT_SIZE * 4)
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
#elif !defined(CONFIG_SYS_RAMBOOT)
#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
#define CONFIG_ENV_SIZE 0x2000
/* Address and size of Redundant Environment Sector */
#else
#define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
#define CONFIG_ENV_SIZE 0x2000
#endif
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
/*
* BOOTP options
*/
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#undef CONFIG_CMD_IMLS
#undef CONFIG_CMD_FLASH
#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MII
#define CONFIG_CMD_DATE
#define CONFIG_CMD_PCI
#define CONFIG_CMD_JFFS2
#if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_NAND_U_BOOT)
#undef CONFIG_CMD_ENV
#undef CONFIG_CMD_LOADS
#endif
#define CONFIG_CMDLINE_EDITING 1
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE ( CONFIG_SYS_CBSIZE \
+ sizeof(CONFIG_SYS_PROMPT) \
+ 16 ) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
#define CONFIG_SYS_HRCW_LOW ( HRCWL_LCL_BUS_TO_SCB_CLK_1X1 \
| 0x20000000 /* reserved */ \
| HRCWL_DDR_TO_SCB_CLK_2X1 \
| HRCWL_CSB_TO_CLKIN_4X1 \
| HRCWL_CORE_TO_CSB_2_5X1 )
#define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 4)
#define CONFIG_SYS_HRCW_HIGH_BASE ( HRCWH_PCI_HOST \
| HRCWH_PCI1_ARBITER_ENABLE \
| HRCWH_CORE_ENABLE \
| HRCWH_BOOTSEQ_DISABLE \
| HRCWH_SW_WATCHDOG_DISABLE \
| HRCWH_TSEC1M_IN_RGMII \
| HRCWH_TSEC2M_IN_RGMII \
| HRCWH_BIG_ENDIAN \
| HRCWH_LALE_NORMAL )
#ifdef CONFIG_NAND_LP
#define CONFIG_SYS_HRCW_HIGH ( CONFIG_SYS_HRCW_HIGH_BASE \
| HRCWH_FROM_0XFFF00100 \
| HRCWH_ROM_LOC_NAND_LP_8BIT \
| HRCWH_RL_EXT_NAND)
#else
#define CONFIG_SYS_HRCW_HIGH ( CONFIG_SYS_HRCW_HIGH_BASE \
| HRCWH_FROM_0XFFF00100 \
| HRCWH_ROM_LOC_NAND_SP_8BIT \
| HRCWH_RL_EXT_NAND )
#endif
/* System IO Config */
#define CONFIG_SYS_SICRH ( SICRH_ETSEC2_B \
| SICRH_ETSEC2_C \
| SICRH_ETSEC2_D \
| SICRH_ETSEC2_E \
| SICRH_ETSEC2_F \
| SICRH_ETSEC2_G \
| SICRH_TSOBI1 \
| SICRH_TSOBI2 )
#define CONFIG_SYS_SICRL (SICRL_USBDR \
| SICRL_ETSEC2_A )
#define CONFIG_SYS_HID0_INIT 0x000000000
#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \
| HID0_ENABLE_DYNAMIC_POWER_MANAGMENT )
#define CONFIG_SYS_HID2 HID2_HBE
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
/* DDR @ 0x00000000 */
#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10)
#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
#define CONFIG_SYS_IBAT1L ((CONFIG_SYS_SDRAM_BASE + 0x10000000) | BATL_PP_10)
#define CONFIG_SYS_IBAT1U ((CONFIG_SYS_SDRAM_BASE + 0x10000000) | BATU_BL_256M | BATU_VS | BATU_VP)
/* PCI @ 0x80000000 */
#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10)
#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
/* PCI2 not supported on 8313 */
#define CONFIG_SYS_IBAT4L (0)
#define CONFIG_SYS_IBAT4U (0)
/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */
#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | BATU_VS | BATU_VP)
/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
#define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_10)
#define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
#define CONFIG_SYS_IBAT7L (0)
#define CONFIG_SYS_IBAT7U (0)
#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
/*
* Internal Definitions
*
* Boot Flags
*/
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
/*
* Environment Configuration
*/
#define CONFIG_ENV_OVERWRITE
#define CONFIG_NETDEV eth1
#define CONFIG_HOSTNAME simpc8313
#define CONFIG_ROOTPATH /tftpboot/
#define CONFIG_BOOTFILE /tftpboot/uImage
#define CONFIG_UBOOTPATH u-boot-nand.bin /* U-Boot image on TFTP server */
#define CONFIG_FDTFILE simpc8313.dtb
#define CONFIG_LOADADDR 500000 /* default location for tftp and bootm */
#define CONFIG_BOOTDELAY 5 /* 5 second delay */
#define CONFIG_BAUDRATE 115200
#define CONFIG_BOOTCOMMAND "nand read $loadaddr kernel 600000;bootm $loadaddr - $fdtaddr"
#define XMK_STR(x) #x
#define MK_STR(x) XMK_STR(x)
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=" MK_STR(CONFIG_NETDEV) "\0" \
"ethprime=TSEC1\0" \
"uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
"tftpflash=tftpboot $loadaddr $uboot; " \
"protect off " MK_STR(TEXT_BASE) " +$filesize; " \
"erase " MK_STR(TEXT_BASE) " +$filesize; " \
"cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
"protect on " MK_STR(TEXT_BASE) " +$filesize; " \
"cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
"fdtaddr=ae0000\0" \
"fdtfile=" MK_STR(CONFIG_FDTFILE) "\0" \
"console=ttyS0\0" \
"setbootargs=setenv bootargs " \
"root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
"setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
"root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
"load_uboot=tftp 100000 u-boot-nand.bin\0" \
"burn_uboot=nand erase u-boot 80000; " \
"nand write 100000 u-boot $filesize\0" \
"update_uboot=run load_uboot;run burn_uboot\0" \
"mtdids=nand0=nand0\0" \
"mtdparts=mtdparts=nand0:2M(u-boot),6M(kernel),-(jffs2)\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=${serverip}:${rootpath}\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
"addip=setenv bootargs ${bootargs} " \
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
":${hostname}:${netdev}:off panic=1\0" \
"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
"bootargs=root=/dev/mtdblock2 rootfstype=jffs2 rw " \
"console=ttyS0,115200\0" \
""
#define CONFIG_NFSBOOTCOMMAND \
"setenv rootdev /dev/nfs;" \
"run setbootargs;" \
"run setipargs;" \
"tftp $loadaddr $bootfile;" \
"tftp $fdtaddr $fdtfile;" \
"bootm $loadaddr - $fdtaddr"
#define CONFIG_RAMBOOTCOMMAND \
"setenv rootdev /dev/ram;" \
"run setbootargs;" \
"tftp $ramdiskaddr $ramdiskfile;" \
"tftp $loadaddr $bootfile;" \
"tftp $fdtaddr $fdtfile;" \
"bootm $loadaddr $ramdiskaddr $fdtaddr"
#undef MK_STR
#undef XMK_STR
#endif /* __CONFIG_H */

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/*
* (C) Copyright 2008
* Heiko Schocher, DENX Software Engineering, hs@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_KEYMILE_H
#define __CONFIG_KEYMILE_H
/* Do boardspecific init for all boards */
#define CONFIG_BOARD_EARLY_INIT_R 1
#if defined(CONFIG_MGCOGE) || defined(CONFIG_MGSUVD)
#define CONFIG_BOOTCOUNT_LIMIT
#endif
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ECHO
#define CONFIG_CMD_IMMAP
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
/* should go away, if kmeter I2C support is enabled */
#if defined(CONFIG_MGCOGE) || defined(CONFIG_MGSUVD)
#define CONFIG_CMD_DTT
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_I2C
#endif
#undef CONFIG_WATCHDOG /* disable platform specific watchdog */
#define CONFIG_BOOTCOMMAND "run net_nfs"
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
/* should go away, if kmeter I2C support is enabled */
#if defined(CONFIG_MGCOGE) || defined(CONFIG_MGSUVD)
#define CONFIG_HUSH_INIT_VAR 1
#endif
#define CONFIG_SYS_ALT_MEMTEST /* memory test, takes time */
#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
/*
* How to get access to the slot ID. Put this here to make it easy
* to modify in a centralized location. This is used in the HDLC
* driver to set the MAC.
*/
#define CONFIG_CHECK_ETHERNET_PRESENT 1
#define CONFIG_SYS_SLOT_ID_BASE CONFIG_SYS_PIGGY_BASE
#define CONFIG_SYS_SLOT_ID_OFF (0x07) /* register offset */
#define CONFIG_SYS_SLOT_ID_MASK (0x3f) /* mask for slot ID bits */
/*
* BOOTP options
*/
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#endif /* __CONFIG_KEYMILE_H */

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/*
* Copyright (C) 2006 Freescale Semiconductor, Inc.
* Dave Liu <daveliu@freescale.com>
*
* Copyright (C) 2007 Logic Product Development, Inc.
* Peter Barada <peterb@logicpd.com>
*
* Copyright (C) 2007 MontaVista Software, Inc.
* Anton Vorontsov <avorontsov@ru.mvista.com>
*
* (C) Copyright 2008
* Heiko Schocher, DENX Software Engineering, hs@denx.de.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*
* High Level Configuration Options
*/
#define CONFIG_E300 1 /* E300 family */
#define CONFIG_QE 1 /* Has QE */
#define CONFIG_MPC83XX 1 /* MPC83XX family */
#define CONFIG_MPC8360 1 /* MPC8360 CPU specific */
#define CONFIG_KMETER1 1 /* KMETER1 board specific */
/* include common defines/options for all Keymile boards */
#include "keymile-common.h"
/*
* System Clock Setup
*/
#define CONFIG_83XX_CLKIN 66000000
#define CONFIG_SYS_CLK_FREQ 66000000
#define CONFIG_83XX_PCICLK 66000000
/*
* Hardware Reset Configuration Word
*/
#define CONFIG_SYS_HRCW_LOW (\
HRCWL_CSB_TO_CLKIN_4X1 | \
HRCWL_CORE_TO_CSB_2X1 | \
HRCWL_CE_PLL_VCO_DIV_2 | \
HRCWL_CE_TO_PLL_1X6 )
#define CONFIG_SYS_HRCW_HIGH (\
HRCWH_CORE_ENABLE | \
HRCWH_FROM_0X00000100 | \
HRCWH_BOOTSEQ_NORMAL | \
HRCWH_SW_WATCHDOG_DISABLE | \
HRCWH_ROM_LOC_LOCAL_16BIT | \
HRCWH_BIG_ENDIAN | \
HRCWH_LDP_CLEAR )
/*
* System IO Config
*/
#define CONFIG_SYS_SICRH 0x00000006
#define CONFIG_SYS_SICRL 0x00000000
/*
* IMMR new address
*/
#define CONFIG_SYS_IMMR 0xE0000000
/*
* DDR Setup
*/
#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
#define CFG_83XX_DDR_USES_CS0
#undef CONFIG_DDR_ECC
/*
* DDRCDR - DDR Control Driver Register
*/
#undef CONFIG_SPD_EEPROM /* Do not use SPD EEPROM for DDR setup */
/*
* Manually set up DDR parameters
*/
#define CONFIG_DDR_II
#define CONFIG_SYS_DDR_SIZE 256 /* MB */
#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f
#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \
CSCONFIG_ROW_BIT_13 | \
CSCONFIG_COL_BIT_10 | CSCONFIG_ODT_WR_ACS)
#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \
SDRAM_CFG_SREN)
#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
#define CONFIG_SYS_DDR_INTERVAL ((0x100 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
(0x406 << SDRAM_INTERVAL_REFINT_SHIFT))
#define CONFIG_SYS_DDR_MODE 0x04440242
#define CONFIG_SYS_DDR_MODE2 0x00800000
#define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
(8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
(6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
(2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
(0 << TIMING_CFG0_WWT_SHIFT) | \
(0 << TIMING_CFG0_RRT_SHIFT) | \
(0 << TIMING_CFG0_WRT_SHIFT) | \
(0 << TIMING_CFG0_RWT_SHIFT))
#define CONFIG_SYS_DDR_TIMING_1 (( TIMING_CFG1_CASLAT_40) | \
( 2 << TIMING_CFG1_WRTORD_SHIFT) | \
( 1 << TIMING_CFG1_ACTTOACT_SHIFT) | \
( 2 << TIMING_CFG1_WRREC_SHIFT) | \
( 2 << TIMING_CFG1_REFREC_SHIFT) | \
( 2 << TIMING_CFG1_ACTTORW_SHIFT) | \
( 6 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
( 2 << TIMING_CFG1_PRETOACT_SHIFT))
#define CONFIG_SYS_DDR_TIMING_2 ((5 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
(3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
(2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
(1 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
(3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
(0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
(4 << TIMING_CFG2_CPO_SHIFT))
#define CONFIG_SYS_DDR_TIMING_3 0x00000000
/*
* The reserved memory
*/
#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
#define CONFIG_SYS_FLASH_BASE 0xF0000000
#define CONFIG_SYS_FLASH_BASE_1 0xF2000000
#define CONFIG_SYS_PIGGY_BASE 0x80000000
#define CONFIG_SYS_PAXE_BASE 0xA0000000
#define CONFIG_SYS_PAXE_SIZE 256
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#define CONFIG_SYS_RAMBOOT
#else
#undef CONFIG_SYS_RAMBOOT
#endif
#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
/*
* Initial RAM Base Address Setup
*/
#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
#define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM */
#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
/*
* Local Bus Configuration & Clock Setup
*/
#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_EADC_2 | LCRR_CLKDIV_4)
/*
* Init Local Bus Memory Controller:
*
* Bank Bus Machine PortSz Size Device
* ---- --- ------- ------ ----- ------
* 0 Local GPCM 16 bit 256MB FLASH
* 1 Local GPCM 8 bit 256KB GPIO/PIGGY
* 3 Local GPCM 8 bit 256MB PAXE
*
*/
/*
* FLASH on the Local Bus
*/
#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
#define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */
#define CONFIG_SYS_FLASH_PROTECTION 1
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* Window base at flash base */
#define CONFIG_SYS_LBLAWAR0_PRELIM 0x8000001b /* 256MB window size */
#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
(2 << BR_PS_SHIFT) | /* 16 bit port size */ \
BR_V)
#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \
OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
OR_GPCM_SCY_5 | \
OR_GPCM_TRLX | OR_GPCM_EAD)
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of flash banks */
#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_1 }
#undef CONFIG_SYS_FLASH_CHECKSUM
/*
* PRIO1/PIGGY on the local bus CS1
*/
#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_PIGGY_BASE /* Window base at flash base */
#define CONFIG_SYS_LBLAWAR1_PRELIM 0x80000011 /* 256KB window size */
#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_PIGGY_BASE | \
(1 << BR_PS_SHIFT) | /* 8 bit port size */ \
BR_V)
#define CONFIG_SYS_OR1_PRELIM (0xfffc0000 | /* 256KB */ \
OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
OR_GPCM_SCY_2 | \
OR_GPCM_TRLX | OR_GPCM_EAD)
/*
* PAXE on the local bus CS3
*/
#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_PAXE_BASE /* Window base at flash base */
#define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000001b /* 256MB window size */
#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_PAXE_BASE | \
(1 << BR_PS_SHIFT) | /* 8 bit port size */ \
BR_V)
#define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_PAXE_SIZE) | \
OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
OR_GPCM_SCY_2 | \
OR_GPCM_TRLX | OR_GPCM_EAD)
/*
* Serial Port
*/
#define CONFIG_CONS_INDEX 1
#undef CONFIG_SERIAL_SOFTWARE_FIFO
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
/* Pass open firmware flat tree */
#define CONFIG_OF_LIBFDT 1
#define CONFIG_OF_BOARD_SETUP 1
#define CONFIG_OF_STDOUT_VIA_ALIAS
/*
* General PCI
* Addresses are mapped 1-1.
*/
#undef CONFIG_PCI /* No PCI */
#ifndef CONFIG_NET_MULTI
#define CONFIG_NET_MULTI 1
#endif
/*
* QE UEC ethernet configuration
*/
#define CONFIG_UEC_ETH
#define CONFIG_ETHPRIME "FSL UEC0"
#define CONFIG_UEC_ETH1 /* GETH1 */
#define UEC_VERBOSE_DEBUG 1
#ifdef CONFIG_UEC_ETH1
#define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */
#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */
#define CONFIG_SYS_UEC1_TX_CLK QE_CLK17
#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
#define CONFIG_SYS_UEC1_PHY_ADDR 0
#define CONFIG_SYS_UEC1_INTERFACE_MODE ENET_100_RMII
#endif
/*
* Environment
*/
#ifndef CONFIG_SYS_RAMBOOT
#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
#define CONFIG_ENV_SIZE 0x20000
#define CONFIG_ENV_OFFSET (CONFIG_SYS_MONITOR_LEN)
/* Address and size of Redundant Environment Sector */
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
#else /* CFG_RAMBOOT */
#define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
#define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
#define CONFIG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
#define CONFIG_ENV_SIZE 0x2000
#endif /* CFG_RAMBOOT */
#if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI
#endif
#if defined(CFG_RAMBOOT)
#undef CONFIG_CMD_ENV
#undef CONFIG_CMD_LOADS
#endif
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*
* Core HID Setup
*/
#define CONFIG_SYS_HID0_INIT 0x000000000
#define CONFIG_SYS_HID0_FINAL HID0_ENABLE_MACHINE_CHECK
#define CONFIG_SYS_HID2 HID2_HBE
/*
* MMU Setup
*/
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
/* DDR: cache cacheable */
#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | \
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
/* IMMRBAR & PCI IO: cache-inhibit and guarded */
#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_10 | \
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS | BATU_VP)
#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
/* PRIO1, PIGGY: icache cacheable, but dcache-inhibit and guarded */
#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PIGGY_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PIGGY_BASE | BATU_BL_256K | BATU_VS | BATU_VP)
#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PIGGY_BASE | BATL_PP_10 | \
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
/* FLASH: icache cacheable, but dcache-inhibit and guarded */
#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
/* Stack in dcache: cacheable, no memory coherence */
#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
/* PAXE: icache cacheable, but dcache-inhibit and guarded */
#define CONFIG_SYS_IBAT5L (CONFIG_SYS_PAXE_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT5U (CONFIG_SYS_PAXE_BASE | BATU_BL_256K | BATU_VS | BATU_VP)
#define CONFIG_SYS_DBAT5L (CONFIG_SYS_PAXE_BASE | BATL_PP_10 | \
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
#ifdef CONFIG_PCI
/* PCI MEM space: cacheable */
#define CFG_IBAT6L (CFG_PCI1_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CFG_IBAT6U (CFG_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
#define CFG_DBAT6L CFG_IBAT6L
#define CFG_DBAT6U CFG_IBAT6U
/* PCI MMIO space: cache-inhibit and guarded */
#define CFG_IBAT7L (CFG_PCI1_MMIO_PHYS | BATL_PP_10 | \
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CFG_IBAT7U (CFG_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
#define CFG_DBAT7L CFG_IBAT7L
#define CFG_DBAT7U CFG_IBAT7U
#else /* CONFIG_PCI */
#define CONFIG_SYS_IBAT6L (0)
#define CONFIG_SYS_IBAT6U (0)
#define CONFIG_SYS_IBAT7L (0)
#define CONFIG_SYS_IBAT7U (0)
#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
#endif /* CONFIG_PCI */
/*
* Internal Definitions
*
* Boot Flags
*/
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
/*
* Environment Configuration
*/
#define CONFIG_ENV_OVERWRITE
#if defined(CONFIG_UEC_ETH)
#define CONFIG_HAS_ETH0
#endif
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"rootpath=/opt/eldk/ppc_82xx\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=${serverip}:${rootpath}\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
"addip=setenv bootargs ${bootargs} " \
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
":${hostname}:${netdev}:off panic=1\0" \
"addtty=setenv bootargs ${bootargs}" \
" console=ttyS0,${baudrate}\0" \
"fdt_addr=f0080000\0" \
"kernel_addr=f00a0000\0" \
"ramdisk_addr=f03a0000\0" \
"kernel_addr_r=400000\0" \
"fdt_addr_r=800000\0" \
"ramdisk_addr_r=810000\0" \
"flash_self=run ramargs addip addtty;" \
"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
"flash_nfs=run nfsargs addip addtty;" \
"bootm ${kernel_addr} - ${fdt_addr}\0" \
"net_nfs=tftp ${kernel_addr_r} ${boot_file}; " \
"tftp ${fdt_addr_r} ${fdt_file}; " \
"run nfsargs addip addtty;" \
"bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
"fdt_file=/tftpboot/kmeter1/kmeter1.dtb\0" \
"boot_file=/tftpboot/kmeter1/uImage\0" \
"ramdisk_file=/tftpboot/kmeter1/uRamdisk\0" \
"u-boot=/tftpboot/kmeter1/u-boot.bin\0" \
"loadaddr=" MK_STR(CONFIG_SYS_LOAD_ADDR) "\0" \
"load=tftp $loadaddr ${u-boot}\0" \
"update=protect off " MK_STR(TEXT_BASE) " +$filesize;" \
"erase " MK_STR(TEXT_BASE) " +$filesize;" \
"cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize;" \
"protect on " MK_STR(TEXT_BASE) " +$filesize;" \
"cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize;" \
"setenv filesize;saveenv\0" \
"upd=run load update\0" \
"loadram=tftp ${ramdisk_addr_r} ${ramdisk_file}\0" \
"loadfdt=tftp ${fdt_addr_r} ${fdt_file}\0" \
"loadkernel=tftp ${kernel_addr_r} ${boot_file}\0" \
"unlock=yes\0" \
""
#endif /* __CONFIG_H */

51
include/configs/mgcoge.h
View File

@ -35,8 +35,8 @@
#define CONFIG_CPM2 1 /* Has a CPM2 */
/* Do boardspecific init */
#define CONFIG_BOARD_EARLY_INIT_R 1
/* include common defines/options for all Keymile boards */
#include "keymile-common.h"
/*
* Select serial console configuration
@ -74,23 +74,6 @@
#define CONFIG_8260_CLKIN 66000000 /* in Hz */
#endif
#define CONFIG_BAUDRATE 115200
#define CONFIG_BOOTCOUNT_LIMIT
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_DTT
#define CONFIG_CMD_ECHO
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_I2C
#define CONFIG_CMD_IMMAP
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
/*
* Default environment settings
*/
@ -124,36 +107,6 @@
"run ramargs addip; " \
"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
""
#define CONFIG_BOOTCOMMAND "run net_nfs"
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#undef CONFIG_WATCHDOG /* disable platform specific watchdog */
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
#define CONFIG_HUSH_INIT_VAR 1
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_FLASH_BASE 0xFE000000

72
include/configs/mgsuvd.h
View File

@ -36,8 +36,8 @@
#define CONFIG_MPC866 1 /* This is a MPC866 CPU */
#define CONFIG_MGSUVD 1 /* ...on a mgsuvd board */
/* Do boardspecific init */
#define CONFIG_BOARD_EARLY_INIT_R 1
/* include common defines/options for all Keymile boards */
#include "keymile-common.h"
#define CONFIG_8xx_GCLK_FREQ 66000000
@ -45,22 +45,13 @@
#define CONFIG_SYS_SMC_DPMEM_OFFSET 0x1fc0
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
#define CONFIG_BOOTCOUNT_LIMIT
#define CONFIG_SYS_CPM_BOOTCOUNT_ADDR 0x1eb0 /* In case of SMC relocation, the
* default value is not working */
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#define CONFIG_BOARD_TYPES 1 /* support board types */
#define CONFIG_PREBOOT "echo;" \
"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
"echo"
#undef CONFIG_BOOTARGS
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"addcons=setenv bootargs ${bootargs} console=ttyCPM0,${baudrate}\0" \
@ -88,70 +79,11 @@
"cp.b 200000 f0000000 ${filesize};" \
"protect on f0000000 +${filesize}\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
#undef CONFIG_WATCHDOG /* watchdog disabled */
/*
* BOOTP options
*/
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_BOOTFILESIZE
#undef CONFIG_RTC_MPC8xx /* MPC866 does not support RTC */
#define CONFIG_TIMESTAMP /* but print image timestmps */
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_DTT
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_I2C
#define CONFIG_CMD_NFS
#define CONFIG_CMD_PING
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
#ifdef CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#define CONFIG_HUSH_INIT_VAR 1
#endif
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
/*
* Low Level Configuration Settings
* (address mappings, register initial values, etc.)

68
include/mpc83xx.h
View File

@ -751,9 +751,6 @@
#define SCCR_USBDRCM_2 0x00800000
#define SCCR_USBDRCM_3 0x00c00000
#define SCCR_PCIEXP1CM 0x00300000
#define SCCR_PCIEXP2CM 0x000c0000
#define SCCR_SATA1CM 0x00003000
#define SCCR_SATA1CM_SHIFT 12
#define SCCR_SATACM 0x00003c00
@ -800,6 +797,17 @@
#define SCCR_USBDRCM_2 0x00800000
#define SCCR_USBDRCM_3 0x00c00000
/* All of the four SATA controllers must have the same clock ratio */
#define SCCR_SATA1CM 0x000000c0
#define SCCR_SATA1CM_SHIFT 6
#define SCCR_SATACM 0x000000ff
#define SCCR_SATACM_SHIFT 0
#define SCCR_SATACM_0 0x00000000
#define SCCR_SATACM_1 0x00000055
#define SCCR_SATACM_2 0x000000aa
#define SCCR_SATACM_3 0x000000ff
#endif
#define SCCR_PCIEXP1CM 0x00300000
#define SCCR_PCIEXP1CM_SHIFT 20
#define SCCR_PCIEXP1CM_0 0x00000000
@ -814,17 +822,6 @@
#define SCCR_PCIEXP2CM_2 0x00080000
#define SCCR_PCIEXP2CM_3 0x000c0000
/* All of the four SATA controllers must have the same clock ratio */
#define SCCR_SATA1CM 0x000000c0
#define SCCR_SATA1CM_SHIFT 6
#define SCCR_SATACM 0x000000ff
#define SCCR_SATACM_SHIFT 0
#define SCCR_SATACM_0 0x00000000
#define SCCR_SATACM_1 0x00000055
#define SCCR_SATACM_2 0x000000aa
#define SCCR_SATACM_3 0x000000ff
#endif
/* CSn_BDNS - Chip Select memory Bounds Register
*/
#define CSBNDS_SA 0x00FF0000
@ -1170,9 +1167,52 @@
#define DDRCDR_M_ODR 0x00000002
#define DDRCDR_Q_DRN 0x00000001
/* PCIE Bridge Register
*/
#define PEX_CSB_CTRL_OBPIOE 0x00000001
#define PEX_CSB_CTRL_IBPIOE 0x00000002
#define PEX_CSB_CTRL_WDMAE 0x00000004
#define PEX_CSB_CTRL_RDMAE 0x00000008
#define PEX_CSB_OBCTRL_PIOE 0x00000001
#define PEX_CSB_OBCTRL_MEMWE 0x00000002
#define PEX_CSB_OBCTRL_IOWE 0x00000004
#define PEX_CSB_OBCTRL_CFGWE 0x00000008
#define PEX_CSB_IBCTRL_PIOE 0x00000001
#define PEX_OWAR_EN 0x00000001
#define PEX_OWAR_TYPE_CFG 0x00000000
#define PEX_OWAR_TYPE_IO 0x00000002
#define PEX_OWAR_TYPE_MEM 0x00000004
#define PEX_OWAR_RLXO 0x00000008
#define PEX_OWAR_NANP 0x00000010
#define PEX_OWAR_SIZE 0xFFFFF000
#define PEX_IWAR_EN 0x00000001
#define PEX_IWAR_TYPE_INT 0x00000000
#define PEX_IWAR_TYPE_PF 0x00000004
#define PEX_IWAR_TYPE_NO_PF 0x00000006
#define PEX_IWAR_NSOV 0x00000008
#define PEX_IWAR_NSNP 0x00000010
#define PEX_IWAR_SIZE 0xFFFFF000
#define PEX_IWAR_SIZE_1M 0x000FF000
#define PEX_IWAR_SIZE_2M 0x001FF000
#define PEX_IWAR_SIZE_4M 0x003FF000
#define PEX_IWAR_SIZE_8M 0x007FF000
#define PEX_IWAR_SIZE_16M 0x00FFF000
#define PEX_IWAR_SIZE_32M 0x01FFF000
#define PEX_IWAR_SIZE_64M 0x03FFF000
#define PEX_IWAR_SIZE_128M 0x07FFF000
#define PEX_IWAR_SIZE_256M 0x0FFFF000
#define PEX_GCLK_RATIO 0x440
#ifndef __ASSEMBLY__
struct pci_region;
void mpc83xx_pci_init(int num_buses, struct pci_region **reg, int warmboot);
void mpc83xx_pcislave_unlock(int bus);
void mpc83xx_pcie_init(int num_buses, struct pci_region **reg, int warmboot);
#endif
#endif /* __MPC83XX_H__ */

4
include/pci.h
View File

@ -382,6 +382,8 @@ extern void pci_cfgfunc_config_device(struct pci_controller* hose, pci_dev_t dev
#define MAX_PCI_REGIONS 7
#define INDIRECT_TYPE_NO_PCIE_LINK 1
/*
* Structure of a PCI controller (host bridge)
*/
@ -394,6 +396,8 @@ struct pci_controller {
volatile unsigned int *cfg_addr;
volatile unsigned char *cfg_data;
int indirect_type;
struct pci_region regions[MAX_PCI_REGIONS];
int region_count;

100
nand_spl/board/sheldon/simpc8313/Makefile Normal file
View File

@ -0,0 +1,100 @@
#
# (C) Copyright 2007
# Stefan Roese, DENX Software Engineering, sr@denx.de.
# (C) Copyright 2008 Freescale Semiconductor
# (C) Copyright Sheldon Instruments, Inc. 2008
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
NAND_SPL := y
TEXT_BASE := 0xfff00000
include $(TOPDIR)/config.mk
LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
LDFLAGS = -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS)
AFLAGS += -DCONFIG_NAND_SPL
CFLAGS += -DCONFIG_NAND_SPL
SOBJS = start.o ticks.o
COBJS = nand_boot_fsl_elbc.o $(BOARD).o sdram.o ns16550.o nand_init.o time.o
SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
__OBJS := $(SOBJS) $(COBJS)
LNDIR := $(OBJTREE)/nand_spl/board/$(BOARDDIR)
nandobj := $(OBJTREE)/nand_spl/
ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
all: $(obj).depend $(ALL)
$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
$(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@
$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl
$(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
$(nandobj)u-boot-spl: $(OBJS)
cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) \
-Map $(nandobj)u-boot-spl.map \
-o $(nandobj)u-boot-spl
# create symbolic links for common files
$(obj)start.S:
ln -sf $(SRCTREE)/cpu/mpc83xx/start.S $<
$(obj)nand_boot_fsl_elbc.c:
ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_elbc.c $<
$(obj)sdram.c:
ln -sf $(SRCTREE)/board/$(BOARDDIR)/sdram.c $<
$(obj)$(BOARD).c:
ln -sf $(SRCTREE)/board/$(BOARDDIR)/$(BOARD).c $<
$(obj)ns16550.c:
ln -sf $(SRCTREE)/drivers/serial/ns16550.c $<
$(obj)nand_init.c:
ln -sf $(SRCTREE)/cpu/mpc83xx/nand_init.c $<
$(obj)time.c:
ln -sf $(SRCTREE)/lib_ppc/time.c $<
$(obj)ticks.S:
ln -sf $(SRCTREE)/lib_ppc/ticks.S $<
#########################################################################
$(obj)%.o: $(obj)%.S
$(CC) $(AFLAGS) -c -o $@ $<
$(obj)%.o: $(obj)%.c
$(CC) $(CFLAGS) -c -o $@ $<
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

52
nand_spl/board/sheldon/simpc8313/u-boot.lds Normal file
View File

@ -0,0 +1,52 @@
/*
* (C) Copyright 2006
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* Copyright 2008 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(powerpc)
SECTIONS
{
. = 0xfff00000;
.text : {
*(.text*)
. = ALIGN(16);
*(.rodata*)
*(.eh_frame)
}
. = ALIGN(8);
.data : {
*(.data*)
*(.sdata*)
_GOT2_TABLE_ = .;
*(.got2)
__got2_entries = (. - _GOT2_TABLE_) >> 2;
}
. = ALIGN(8);
__bss_start = .;
.bss (NOLOAD) : { *(.*bss) }
_end = .;
}
ENTRY(_start)
ASSERT(_end <= 0xfff01000, "NAND bootstrap too big");