driver: clk: Add support for clocks on Armada 37xx
The drivers are based on Linux driver by Gregory Clement.
The TBG clocks support only the .get_rate method.
- since setting rate is not supported, the driver computes the rates
when probing and so subsequent calls to the .get_rate method do not
read the corresponding registers again
The peripheral clocks support methods .get_rate, .enable and .disable.
- the .set_parent method theoretically could be supported on some clocks
(the parent would have to be one of the TBG clocks)
- the .set_rate method would have to try all the divider values to find
the best approximation of a given rate, and it doesn't seem like
this should be needed in U-Boot, therefore not implemented
Signed-off-by: Marek Behun <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Marek Behún
Stefan Roese
parent
7288182aa6
commit
82a248df9a
@ -107,6 +107,26 @@
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status = "disabled";
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};
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nb_periph_clk: nb-periph-clk@13000 {
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compatible = "marvell,armada-3700-periph-clock-nb";
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reg = <0x13000 0x100>;
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clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>, <&tbg 3>;
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#clock-cells = <1>;
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};
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sb_periph_clk: sb-periph-clk@18000 {
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compatible = "marvell,armada-3700-periph-clock-sb";
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reg = <0x18000 0x100>;
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clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>, <&tbg 3>;
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#clock-cells = <1>;
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};
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tbg: tbg@13200 {
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compatible = "marvell,armada-3700-tbg-clock";
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reg = <0x13200 0x100>;
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#clock-cells = <1>;
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};
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pinctrl_nb: pinctrl-nb@13800 {
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compatible = "marvell,armada3710-nb-pinctrl",
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"syscon", "simple-mfd";
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@ -88,6 +88,7 @@ source "drivers/clk/uniphier/Kconfig"
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source "drivers/clk/exynos/Kconfig"
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source "drivers/clk/at91/Kconfig"
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source "drivers/clk/renesas/Kconfig"
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source "drivers/clk/mvebu/Kconfig"
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config ICS8N3QV01
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bool "Enable ICS8N3QV01 VCXO driver"
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@ -11,6 +11,7 @@ obj-y += tegra/
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obj-$(CONFIG_ARCH_ASPEED) += aspeed/
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obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
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obj-$(CONFIG_CLK_AT91) += at91/
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obj-$(CONFIG_CLK_MVEBU) += mvebu/
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obj-$(CONFIG_CLK_BCM6345) += clk_bcm6345.o
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obj-$(CONFIG_CLK_BOSTON) += clk_boston.o
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obj-$(CONFIG_CLK_EXYNOS) += exynos/
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11
drivers/clk/mvebu/Kconfig
Normal file
11
drivers/clk/mvebu/Kconfig
Normal file
@ -0,0 +1,11 @@
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config CLK_MVEBU
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bool "MVEBU clock drivers"
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depends on CLK && ARCH_MVEBU
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help
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Enable support for clock present on Marvell MVEBU SoCs.
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config CLK_ARMADA_3720
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bool "Marvell Armada 3720 clock driver"
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depends on CLK_MVEBU && ARM64
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help
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Enable this to support the clocks on Marvell Armada 3720 SoC.
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1
drivers/clk/mvebu/Makefile
Normal file
1
drivers/clk/mvebu/Makefile
Normal file
@ -0,0 +1 @@
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obj-$(CONFIG_CLK_ARMADA_3720) += armada-37xx-periph.o armada-37xx-tbg.o
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465
drivers/clk/mvebu/armada-37xx-periph.c
Normal file
465
drivers/clk/mvebu/armada-37xx-periph.c
Normal file
@ -0,0 +1,465 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Marvell Armada 37xx SoC Peripheral clocks
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*
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* Marek Behun <marek.behun@nic.cz>
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*
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* Based on Linux driver by:
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* Gregory CLEMENT <gregory.clement@free-electrons.com>
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*/
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#include <common.h>
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#include <malloc.h>
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#include <clk-uclass.h>
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#include <clk.h>
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#include <dm.h>
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#include <asm/io.h>
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#include <asm/arch/cpu.h>
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#define TBG_SEL 0x0
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#define DIV_SEL0 0x4
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#define DIV_SEL1 0x8
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#define DIV_SEL2 0xC
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#define CLK_SEL 0x10
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#define CLK_DIS 0x14
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enum a37xx_periph_parent {
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TBG_A_P = 0,
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TBG_B_P = 1,
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TBG_A_S = 2,
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TBG_B_S = 3,
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MAX_TBG_PARENTS = 4,
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XTAL = 4,
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MAX_PARENTS = 5,
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};
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static const struct {
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const char *name;
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enum a37xx_periph_parent parent;
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} a37xx_periph_parent_names[] = {
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{ "TBG-A-P", TBG_A_P },
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{ "TBG-B-P", TBG_B_P },
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{ "TBG-A-S", TBG_A_S },
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{ "TBG-B-S", TBG_B_S },
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{ "xtal", XTAL },
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};
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struct clk_periph;
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struct a37xx_periphclk {
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void __iomem *reg;
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ulong parents[MAX_PARENTS];
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const struct clk_periph *clks;
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bool clk_has_periph_parent[16];
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int clk_parent[16];
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int count;
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};
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struct clk_div_table {
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u32 div;
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u32 val;
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};
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struct clk_periph {
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const char *name;
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const char *parent_name;
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u32 disable_bit;
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int mux_shift;
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const struct clk_div_table *div_table[2];
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s32 div_reg_off[2];
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u32 div_mask[2];
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int div_shift[2];
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unsigned can_gate : 1;
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unsigned can_mux : 1;
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unsigned dividers : 2;
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};
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static const struct clk_div_table div_table1[] = {
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{ 1, 1 },
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{ 2, 2 },
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{ 0, 0 },
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};
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static const struct clk_div_table div_table2[] = {
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{ 2, 1 },
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{ 4, 2 },
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{ 0, 0 },
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};
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static const struct clk_div_table div_table6[] = {
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{ 1, 1 },
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{ 2, 2 },
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{ 3, 3 },
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{ 4, 4 },
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{ 5, 5 },
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{ 6, 6 },
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{ 0, 0 },
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};
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#define CLK_FULL_DD(_n, _d, _mux, _r0, _r1, _s0, _s1) \
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{ \
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.name = #_n, \
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.disable_bit = BIT(_d), \
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.mux_shift = _mux, \
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.div_table[0] = div_table6, \
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.div_table[1] = div_table6, \
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.div_reg_off[0] = _r0, \
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.div_reg_off[1] = _r1, \
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.div_shift[0] = _s0, \
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.div_shift[1] = _s1, \
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.div_mask[0] = 7, \
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.div_mask[1] = 7, \
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.can_gate = 1, \
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.can_mux = 1, \
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.dividers = 2, \
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}
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#define CLK_FULL(_n, _d, _mux, _r, _s, _m, _t) \
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{ \
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.name = #_n, \
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.disable_bit = BIT(_d), \
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.mux_shift = _mux, \
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.div_table[0] = _t, \
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.div_reg_off[0] = _r, \
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.div_shift[0] = _s, \
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.div_mask[0] = _m, \
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.can_gate = 1, \
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.can_mux = 1, \
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.dividers = 1, \
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}
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#define CLK_GATE_DIV(_n, _d, _r, _s, _m, _t, _p) \
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{ \
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.name = #_n, \
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.parent_name = _p, \
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.disable_bit = BIT(_d), \
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.div_table[0] = _t, \
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.div_reg_off[0] = _r, \
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.div_shift[0] = _s, \
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.div_mask[0] = _m, \
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.can_gate = 1, \
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.dividers = 1, \
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}
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#define CLK_GATE(_n, _d, _p) \
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{ \
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.name = #_n, \
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.parent_name = _p, \
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.disable_bit = BIT(_d), \
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.can_gate = 1, \
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}
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#define CLK_MUX_DIV(_n, _mux, _r, _s, _m, _t) \
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{ \
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.name = #_n, \
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.mux_shift = _mux, \
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.div_table[0] = _t, \
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.div_reg_off[0] = _r, \
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.div_shift[0] = _s, \
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.div_mask[0] = _m, \
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.can_mux = 1, \
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.dividers = 1, \
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}
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#define CLK_MUX_DD(_n, _mux, _r0, _r1, _s0, _s1) \
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{ \
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.name = #_n, \
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.mux_shift = _mux, \
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.div_table[0] = div_table6, \
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.div_table[1] = div_table6, \
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.div_reg_off[0] = _r0, \
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.div_reg_off[1] = _r1, \
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.div_shift[0] = _s0, \
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.div_shift[1] = _s1, \
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.div_mask[0] = 7, \
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.div_mask[1] = 7, \
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.can_mux = 1, \
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.dividers = 2, \
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}
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/* NB periph clocks */
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static const struct clk_periph clks_nb[] = {
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CLK_FULL_DD(mmc, 2, 0, DIV_SEL2, DIV_SEL2, 16, 13),
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CLK_FULL_DD(sata_host, 3, 2, DIV_SEL2, DIV_SEL2, 10, 7),
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CLK_FULL_DD(sec_at, 6, 4, DIV_SEL1, DIV_SEL1, 3, 0),
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CLK_FULL_DD(sec_dap, 7, 6, DIV_SEL1, DIV_SEL1, 9, 6),
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CLK_FULL_DD(tscem, 8, 8, DIV_SEL1, DIV_SEL1, 15, 12),
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CLK_FULL(tscem_tmx, 10, 10, DIV_SEL1, 18, 7, div_table6),
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CLK_GATE(avs, 11, "xtal"),
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CLK_FULL_DD(sqf, 12, 12, DIV_SEL1, DIV_SEL1, 27, 24),
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CLK_FULL_DD(pwm, 13, 14, DIV_SEL0, DIV_SEL0, 3, 0),
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CLK_GATE(i2c_2, 16, "xtal"),
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CLK_GATE(i2c_1, 17, "xtal"),
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CLK_GATE_DIV(ddr_phy, 19, DIV_SEL0, 18, 1, div_table2, "TBG-A-S"),
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CLK_FULL_DD(ddr_fclk, 21, 16, DIV_SEL0, DIV_SEL0, 15, 12),
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CLK_FULL(trace, 22, 18, DIV_SEL0, 20, 7, div_table6),
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CLK_FULL(counter, 23, 20, DIV_SEL0, 23, 7, div_table6),
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CLK_FULL_DD(eip97, 24, 24, DIV_SEL2, DIV_SEL2, 22, 19),
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CLK_MUX_DIV(cpu, 22, DIV_SEL0, 28, 7, div_table6),
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{ },
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};
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/* SB periph clocks */
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static const struct clk_periph clks_sb[] = {
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CLK_MUX_DD(gbe_50, 6, DIV_SEL2, DIV_SEL2, 6, 9),
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CLK_MUX_DD(gbe_core, 8, DIV_SEL1, DIV_SEL1, 18, 21),
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CLK_MUX_DD(gbe_125, 10, DIV_SEL1, DIV_SEL1, 6, 9),
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CLK_GATE(gbe1_50, 0, "gbe_50"),
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CLK_GATE(gbe0_50, 1, "gbe_50"),
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CLK_GATE(gbe1_125, 2, "gbe_125"),
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CLK_GATE(gbe0_125, 3, "gbe_125"),
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CLK_GATE_DIV(gbe1_core, 4, DIV_SEL1, 13, 1, div_table1, "gbe_core"),
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CLK_GATE_DIV(gbe0_core, 5, DIV_SEL1, 14, 1, div_table1, "gbe_core"),
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CLK_GATE_DIV(gbe_bm, 12, DIV_SEL1, 0, 1, div_table1, "gbe_core"),
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CLK_FULL_DD(sdio, 11, 14, DIV_SEL0, DIV_SEL0, 3, 6),
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CLK_FULL_DD(usb32_usb2_sys, 16, 16, DIV_SEL0, DIV_SEL0, 9, 12),
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CLK_FULL_DD(usb32_ss_sys, 17, 18, DIV_SEL0, DIV_SEL0, 15, 18),
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{ },
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};
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static inline int get_mux(struct a37xx_periphclk *priv, int shift)
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{
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return (readl(priv->reg + TBG_SEL) >> shift) & 3;
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}
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static ulong periph_clk_get_rate(struct a37xx_periphclk *priv, int id);
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static ulong get_parent_rate(struct a37xx_periphclk *priv, int id)
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{
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const struct clk_periph *clk = &priv->clks[id];
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ulong res;
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if (clk->can_mux) {
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/* parent is one of TBG clocks */
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int tbg = get_mux(priv, clk->mux_shift);
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res = priv->parents[tbg];
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} else if (priv->clk_has_periph_parent[id]) {
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/* parent is one of other periph clocks */
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if (priv->clk_parent[id] >= priv->count)
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return -EINVAL;
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res = periph_clk_get_rate(priv, priv->clk_parent[id]);
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} else {
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/* otherwise parent is one of TBGs or XTAL */
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if (priv->clk_parent[id] >= MAX_PARENTS)
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return -EINVAL;
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res = priv->parents[priv->clk_parent[id]];
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}
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return res;
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}
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static ulong get_div(struct a37xx_periphclk *priv,
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const struct clk_periph *clk, int idx)
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{
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const struct clk_div_table *i;
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u32 reg;
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reg = readl(priv->reg + clk->div_reg_off[idx]);
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reg = (reg >> clk->div_shift[idx]) & clk->div_mask[idx];
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/* find divisor for register value val */
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for (i = clk->div_table[idx]; i && i->div != 0; ++i)
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if (i->val == reg)
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return i->div;
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return 0;
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}
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static ulong periph_clk_get_rate(struct a37xx_periphclk *priv, int id)
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{
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const struct clk_periph *clk = &priv->clks[id];
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ulong rate, div;
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int i;
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rate = get_parent_rate(priv, id);
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if (rate == -EINVAL)
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return -EINVAL;
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/* divide the parent rate by dividers */
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div = 1;
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for (i = 0; i < clk->dividers; ++i)
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div *= get_div(priv, clk, i);
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if (!div)
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return 0;
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return DIV_ROUND_UP(rate, div);
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}
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static ulong armada_37xx_periph_clk_get_rate(struct clk *clk)
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{
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struct a37xx_periphclk *priv = dev_get_priv(clk->dev);
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if (clk->id >= priv->count)
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return -EINVAL;
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return periph_clk_get_rate(priv, clk->id);
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}
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static int periph_clk_enable(struct clk *clk, int enable)
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{
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struct a37xx_periphclk *priv = dev_get_priv(clk->dev);
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const struct clk_periph *periph_clk = &priv->clks[clk->id];
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if (clk->id >= priv->count)
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return -EINVAL;
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if (!periph_clk->can_gate)
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return -ENOTSUPP;
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if (enable)
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clrbits_le32(priv->reg + CLK_DIS, periph_clk->disable_bit);
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else
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setbits_le32(priv->reg + CLK_DIS, periph_clk->disable_bit);
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return 0;
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}
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static int armada_37xx_periph_clk_enable(struct clk *clk)
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{
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return periph_clk_enable(clk, 1);
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}
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static int armada_37xx_periph_clk_disable(struct clk *clk)
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{
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return periph_clk_enable(clk, 0);
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}
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int armada_37xx_periph_clk_dump(struct udevice *dev)
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{
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struct a37xx_periphclk *priv = dev_get_priv(dev);
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const struct clk_periph *clks;
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int i;
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if (!priv)
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return -ENODEV;
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clks = priv->clks;
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for (i = 0; i < priv->count; ++i)
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printf(" %s at %lu Hz\n", clks[i].name,
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periph_clk_get_rate(priv, i));
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printf("\n");
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return 0;
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}
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static int armada_37xx_periph_clk_probe(struct udevice *dev)
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{
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struct a37xx_periphclk *priv = dev_get_priv(dev);
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const struct clk_periph *clks;
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int ret, i;
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clks = (const struct clk_periph *)dev_get_driver_data(dev);
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if (!clks)
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return -ENODEV;
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priv->reg = dev_read_addr_ptr(dev);
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if (!priv->reg) {
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||||
dev_err(dev, "no io address\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
/* count clk_periph nodes */
|
||||
priv->count = 0;
|
||||
while (clks[priv->count].name)
|
||||
priv->count++;
|
||||
|
||||
priv->clks = clks;
|
||||
|
||||
/* assign parent IDs to nodes which have non-NULL parent_name */
|
||||
for (i = 0; i < priv->count; ++i) {
|
||||
int j;
|
||||
|
||||
if (!clks[i].parent_name)
|
||||
continue;
|
||||
|
||||
/* first try if parent_name is one of TBGs or XTAL */
|
||||
for (j = 0; j < MAX_PARENTS; ++j)
|
||||
if (!strcmp(clks[i].parent_name,
|
||||
a37xx_periph_parent_names[j].name))
|
||||
break;
|
||||
|
||||
if (j < MAX_PARENTS) {
|
||||
priv->clk_has_periph_parent[i] = false;
|
||||
priv->clk_parent[i] =
|
||||
a37xx_periph_parent_names[j].parent;
|
||||
continue;
|
||||
}
|
||||
|
||||
/* else parent_name should be one of other periph clocks */
|
||||
for (j = 0; j < priv->count; ++j) {
|
||||
if (!strcmp(clks[i].parent_name, clks[j].name))
|
||||
break;
|
||||
}
|
||||
|
||||
if (j < priv->count) {
|
||||
priv->clk_has_periph_parent[i] = true;
|
||||
priv->clk_parent[i] = j;
|
||||
continue;
|
||||
}
|
||||
|
||||
dev_err(dev, "undefined parent %s\n", clks[i].parent_name);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
for (i = 0; i < MAX_PARENTS; ++i) {
|
||||
struct clk clk;
|
||||
|
||||
if (i == XTAL) {
|
||||
priv->parents[i] = get_ref_clk() * 1000000;
|
||||
continue;
|
||||
}
|
||||
|
||||
ret = clk_get_by_index(dev, i, &clk);
|
||||
if (ret) {
|
||||
dev_err(dev, "one of parent clocks (%i) missing: %i\n",
|
||||
i, ret);
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
priv->parents[i] = clk_get_rate(&clk);
|
||||
clk_free(&clk);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct clk_ops armada_37xx_periph_clk_ops = {
|
||||
.get_rate = armada_37xx_periph_clk_get_rate,
|
||||
.enable = armada_37xx_periph_clk_enable,
|
||||
.disable = armada_37xx_periph_clk_disable,
|
||||
};
|
||||
|
||||
static const struct udevice_id armada_37xx_periph_clk_ids[] = {
|
||||
{
|
||||
.compatible = "marvell,armada-3700-periph-clock-nb",
|
||||
.data = (ulong)clks_nb,
|
||||
},
|
||||
{
|
||||
.compatible = "marvell,armada-3700-periph-clock-sb",
|
||||
.data = (ulong)clks_sb,
|
||||
},
|
||||
{}
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(armada_37xx_periph_clk) = {
|
||||
.name = "armada_37xx_periph_clk",
|
||||
.id = UCLASS_CLK,
|
||||
.of_match = armada_37xx_periph_clk_ids,
|
||||
.ops = &armada_37xx_periph_clk_ops,
|
||||
.priv_auto_alloc_size = sizeof(struct a37xx_periphclk),
|
||||
.probe = armada_37xx_periph_clk_probe,
|
||||
};
|
||||
152
drivers/clk/mvebu/armada-37xx-tbg.c
Normal file
152
drivers/clk/mvebu/armada-37xx-tbg.c
Normal file
@ -0,0 +1,152 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Marvell Armada 37xx SoC Time Base Generator clocks
|
||||
*
|
||||
* Marek Behun <marek.behun@nic.cz>
|
||||
*
|
||||
* Based on Linux driver by:
|
||||
* Gregory CLEMENT <gregory.clement@free-electrons.com>
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <clk-uclass.h>
|
||||
#include <clk.h>
|
||||
#include <dm.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/cpu.h>
|
||||
|
||||
#define NUM_TBG 4
|
||||
|
||||
#define TBG_CTRL0 0x4
|
||||
#define TBG_CTRL1 0x8
|
||||
#define TBG_CTRL7 0x20
|
||||
#define TBG_CTRL8 0x30
|
||||
|
||||
#define TBG_DIV_MASK 0x1FF
|
||||
|
||||
#define TBG_A_REFDIV 0
|
||||
#define TBG_B_REFDIV 16
|
||||
|
||||
#define TBG_A_FBDIV 2
|
||||
#define TBG_B_FBDIV 18
|
||||
|
||||
#define TBG_A_VCODIV_SE 0
|
||||
#define TBG_B_VCODIV_SE 16
|
||||
|
||||
#define TBG_A_VCODIV_DIFF 1
|
||||
#define TBG_B_VCODIV_DIFF 17
|
||||
|
||||
struct tbg_def {
|
||||
const char *name;
|
||||
u32 refdiv_offset;
|
||||
u32 fbdiv_offset;
|
||||
u32 vcodiv_reg;
|
||||
u32 vcodiv_offset;
|
||||
};
|
||||
|
||||
static const struct tbg_def tbg[NUM_TBG] = {
|
||||
{"TBG-A-P", TBG_A_REFDIV, TBG_A_FBDIV, TBG_CTRL8, TBG_A_VCODIV_DIFF},
|
||||
{"TBG-B-P", TBG_B_REFDIV, TBG_B_FBDIV, TBG_CTRL8, TBG_B_VCODIV_DIFF},
|
||||
{"TBG-A-S", TBG_A_REFDIV, TBG_A_FBDIV, TBG_CTRL1, TBG_A_VCODIV_SE},
|
||||
{"TBG-B-S", TBG_B_REFDIV, TBG_B_FBDIV, TBG_CTRL1, TBG_B_VCODIV_SE},
|
||||
};
|
||||
|
||||
struct a37xx_tbgclk {
|
||||
ulong rates[NUM_TBG];
|
||||
unsigned int mult[NUM_TBG];
|
||||
unsigned int div[NUM_TBG];
|
||||
};
|
||||
|
||||
static unsigned int tbg_get_mult(void __iomem *reg, const struct tbg_def *ptbg)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
val = readl(reg + TBG_CTRL0);
|
||||
|
||||
return ((val >> ptbg->fbdiv_offset) & TBG_DIV_MASK) << 2;
|
||||
}
|
||||
|
||||
static unsigned int tbg_get_div(void __iomem *reg, const struct tbg_def *ptbg)
|
||||
{
|
||||
u32 val;
|
||||
unsigned int div;
|
||||
|
||||
val = readl(reg + TBG_CTRL7);
|
||||
|
||||
div = (val >> ptbg->refdiv_offset) & TBG_DIV_MASK;
|
||||
if (div == 0)
|
||||
div = 1;
|
||||
val = readl(reg + ptbg->vcodiv_reg);
|
||||
|
||||
div *= 1 << ((val >> ptbg->vcodiv_offset) & TBG_DIV_MASK);
|
||||
|
||||
return div;
|
||||
}
|
||||
|
||||
static ulong armada_37xx_tbg_clk_get_rate(struct clk *clk)
|
||||
{
|
||||
struct a37xx_tbgclk *priv = dev_get_priv(clk->dev);
|
||||
|
||||
if (clk->id >= NUM_TBG)
|
||||
return -ENODEV;
|
||||
|
||||
return priv->rates[clk->id];
|
||||
}
|
||||
|
||||
int armada_37xx_tbg_clk_dump(struct udevice *dev)
|
||||
{
|
||||
struct a37xx_tbgclk *priv = dev_get_priv(dev);
|
||||
int i;
|
||||
|
||||
for (i = 0; i < NUM_TBG; ++i)
|
||||
printf(" %s at %lu Hz\n", tbg[i].name,
|
||||
priv->rates[i]);
|
||||
printf("\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int armada_37xx_tbg_clk_probe(struct udevice *dev)
|
||||
{
|
||||
struct a37xx_tbgclk *priv = dev_get_priv(dev);
|
||||
void __iomem *reg;
|
||||
ulong xtal;
|
||||
int i;
|
||||
|
||||
reg = dev_read_addr_ptr(dev);
|
||||
if (!reg) {
|
||||
dev_err(dev, "no io address\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
xtal = (ulong)get_ref_clk() * 1000000;
|
||||
|
||||
for (i = 0; i < NUM_TBG; ++i) {
|
||||
unsigned int mult, div;
|
||||
|
||||
mult = tbg_get_mult(reg, &tbg[i]);
|
||||
div = tbg_get_div(reg, &tbg[i]);
|
||||
|
||||
priv->rates[i] = (xtal * mult) / div;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct clk_ops armada_37xx_tbg_clk_ops = {
|
||||
.get_rate = armada_37xx_tbg_clk_get_rate,
|
||||
};
|
||||
|
||||
static const struct udevice_id armada_37xx_tbg_clk_ids[] = {
|
||||
{ .compatible = "marvell,armada-3700-tbg-clock" },
|
||||
{}
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(armada_37xx_tbg_clk) = {
|
||||
.name = "armada_37xx_tbg_clk",
|
||||
.id = UCLASS_CLK,
|
||||
.of_match = armada_37xx_tbg_clk_ids,
|
||||
.ops = &armada_37xx_tbg_clk_ops,
|
||||
.priv_auto_alloc_size = sizeof(struct a37xx_tbgclk),
|
||||
.probe = armada_37xx_tbg_clk_probe,
|
||||
};
|
||||
Loading…
Reference in New Issue
Block a user