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ddr: fsl: Remove CONFIG_MEM_INIT_VALUE

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The way all of the memory init code here works is that we pass
0xDEADBEEF around for the initial value (as it's a well known 'poison'
value and so easily recognized in debuggers, etc). The only point of
this CONFIG symbol was to pass in a different value for that purpose.
Drop this symbol and cleanup the code slightly.

Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini 2022-12-02 16:42:35 -05:00
parent 2cc61a631b
commit 829e9d2236
23 changed files with 6 additions and 81 deletions
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2
arch/powerpc/include/asm/fsl_dma.h
View File

@ -117,7 +117,7 @@ typedef struct fsl_dma {
void dma_init(void);
int dmacpy(phys_addr_t dest, phys_addr_t src, phys_size_t n);
#if (defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER))
void dma_meminit(uint val, uint size);
void dma_meminit(uint size);
#endif
#endif

17
drivers/ddr/fsl/ctrl_regs.c
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@ -938,7 +938,7 @@ static void set_ddr_sdram_cfg_2(const unsigned int ctrl_num,
#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
/* Use the DDR controller to auto initialize memory. */
d_init = popts->ecc_init_using_memctl;
ddr->ddr_data_init = CONFIG_MEM_INIT_VALUE;
ddr->ddr_data_init = 0xDEADBEEF;
debug("DDR: ddr_data_init = 0x%08x\n", ddr->ddr_data_init);
#else
/* Memory will be initialized via DMA, or not at all. */
@ -1842,19 +1842,6 @@ static void set_ddr_sdram_mode(const unsigned int ctrl_num,
}
#endif
/* DDR SDRAM Data Initialization (DDR_DATA_INIT) */
static void set_ddr_data_init(fsl_ddr_cfg_regs_t *ddr)
{
unsigned int init_value; /* Initialization value */
#ifdef CONFIG_MEM_INIT_VALUE
init_value = CONFIG_MEM_INIT_VALUE;
#else
init_value = 0xDEADBEEF;
#endif
ddr->ddr_data_init = init_value;
}
/*
* DDR SDRAM Clock Control (DDR_SDRAM_CLK_CNTL)
* The old controller on the 8540/60 doesn't have this register.
@ -2537,7 +2524,7 @@ compute_fsl_memctl_config_regs(const unsigned int ctrl_num,
set_ddr_sdram_rcw(ctrl_num, ddr, popts, common_dimm);
set_ddr_sdram_interval(ctrl_num, ddr, popts, common_dimm);
set_ddr_data_init(ddr);
ddr->ddr_data_init = 0xDEADBEEF;
set_ddr_sdram_clk_cntl(ddr, popts);
set_ddr_init_addr(ddr);
set_ddr_init_ext_addr(ddr);

2
drivers/ddr/fsl/mpc85xx_ddr_gen1.c
View File

@ -73,7 +73,7 @@ ddr_enable_ecc(unsigned int dram_size)
struct ccsr_ddr __iomem *ddr =
(struct ccsr_ddr __iomem *)(CFG_SYS_FSL_DDR_ADDR);
dma_meminit(CONFIG_MEM_INIT_VALUE, dram_size);
dma_meminit(dram_size);
/*
* Enable errors for ECC.

4
drivers/dma/fsl_dma.c
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@ -133,7 +133,7 @@ int dmacpy(phys_addr_t dest, phys_addr_t src, phys_size_t count) {
*/
#if ((!defined CONFIG_MPC83xx && defined(CONFIG_DDR_ECC) && \
!defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)))
void dma_meminit(uint val, uint size)
void dma_meminit(uint size)
{
uint *p = 0;
uint i = 0;
@ -142,7 +142,7 @@ void dma_meminit(uint val, uint size)
if (((uint)p & 0x1f) == 0)
ppcDcbz((ulong)p);
*p = (uint)CONFIG_MEM_INIT_VALUE;
*p = (uint)0xDEADBEEF;
if (((uint)p & 0x1c) == 0x1c)
ppcDcbf((ulong)p);

2
include/configs/MPC8548CDS.h
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@ -26,8 +26,6 @@
/* DDR Setup */
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
#define CFG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE

2
include/configs/P1010RDB.h
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@ -98,8 +98,6 @@
/* DDR Setup */
#define SPD_EEPROM_ADDRESS 0x52
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
#ifndef __ASSEMBLY__
extern unsigned long get_sdram_size(void);
#endif

3
include/configs/T102xRDB.h
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@ -94,9 +94,6 @@
* These can be toggled for performance analysis, otherwise use default.
*/
#define CFG_SYS_INIT_L2CSR0 L2CSR0_L2E
#ifdef CONFIG_DDR_ECC
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#endif
/*
* Config the L3 Cache as L3 SRAM

3
include/configs/T104xRDB.h
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@ -64,9 +64,6 @@
* These can be toggled for performance analysis, otherwise use default.
*/
#define CFG_SYS_INIT_L2CSR0 L2CSR0_L2E
#ifdef CONFIG_DDR_ECC
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#endif
/*
* Config the L3 Cache as L3 SRAM

7
include/configs/T208xQDS.h
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@ -59,13 +59,6 @@
#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
#endif
/*
* These can be toggled for performance analysis, otherwise use default.
*/
#ifdef CONFIG_DDR_ECC
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#endif
/*
* Config the L3 Cache as L3 SRAM
*/

7
include/configs/T208xRDB.h
View File

@ -59,13 +59,6 @@
#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
#endif
/*
* These can be toggled for performance analysis, otherwise use default.
*/
#ifdef CONFIG_DDR_ECC
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#endif
/*
* Config the L3 Cache as L3 SRAM
*/

7
include/configs/T4240RDB.h
View File

@ -40,13 +40,6 @@
#define CFG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
/*
* These can be toggled for performance analysis, otherwise use default.
*/
#ifdef CONFIG_DDR_ECC
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#endif
/*
* Config the L3 Cache as L3 SRAM
*/

3
include/configs/kontron_sl28.h
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@ -15,9 +15,6 @@
#undef CFG_SYS_MEM_RESERVE_SECURE
#endif
/* DDR */
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#define CFG_SYS_DDR_SDRAM_BASE 0x80000000
#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE

4
include/configs/ls1021aqds.h
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@ -22,10 +22,6 @@
#define CFG_SYS_DDR_SDRAM_BASE 0x80000000UL
#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
#ifdef CONFIG_DDR_ECC
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#endif
/*
* IFC Definitions
*/

4
include/configs/ls1043aqds.h
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@ -12,10 +12,6 @@
#define SPD_EEPROM_ADDRESS 0x51
#ifdef CONFIG_DDR_ECC
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#endif
#ifdef CONFIG_SYS_DPAA_FMAN
#define RGMII_PHY1_ADDR 0x1
#define RGMII_PHY2_ADDR 0x2

6
include/configs/ls1043ardb.h
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@ -9,12 +9,6 @@
#include "ls1043a_common.h"
/* Physical Memory Map */
#ifndef CONFIG_SPL
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#endif
/*
* NOR Flash Definitions
*/

4
include/configs/ls1046aqds.h
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@ -12,10 +12,6 @@
#define SPD_EEPROM_ADDRESS 0x51
#ifdef CONFIG_DDR_ECC
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#endif
#ifdef CONFIG_SYS_DPAA_FMAN
#define RGMII_PHY1_ADDR 0x1
#define RGMII_PHY2_ADDR 0x2

2
include/configs/ls1046ardb.h
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@ -13,8 +13,6 @@
#define SPD_EEPROM_ADDRESS 0x51
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#if defined(CONFIG_QSPI_BOOT)
#define CFG_SYS_UBOOT_BASE 0x40100000
#endif

1
include/configs/ls1088aqds.h
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@ -14,7 +14,6 @@
#define COUNTER_FREQUENCY_REAL (get_board_sys_clk()/4)
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#define SPD_EEPROM_ADDRESS 0x51

1
include/configs/ls1088ardb.h
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@ -15,7 +15,6 @@
#define COUNTER_FREQUENCY_REAL 25000000 /* 25MHz */
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#define SPD_EEPROM_ADDRESS 0x51

1
include/configs/ls2080aqds.h
View File

@ -16,7 +16,6 @@
#define CFG_SYS_I2C_FPGA_ADDR 0x66
#define COUNTER_FREQUENCY_REAL (get_board_sys_clk()/4)
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#define SPD_EEPROM_ADDRESS1 0x51
#define SPD_EEPROM_ADDRESS2 0x52
#define SPD_EEPROM_ADDRESS3 0x53

1
include/configs/ls2080ardb.h
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@ -21,7 +21,6 @@
#define COUNTER_FREQUENCY_REAL (get_board_sys_clk()/4)
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#define SPD_EEPROM_ADDRESS1 0x51
#define SPD_EEPROM_ADDRESS2 0x52
#define SPD_EEPROM_ADDRESS3 0x53

1
include/configs/lx2160a_common.h
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@ -18,7 +18,6 @@
#define CFG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL
#define CFG_SYS_SDRAM_SIZE 0x200000000UL
#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#define SPD_EEPROM_ADDRESS1 0x51
#define SPD_EEPROM_ADDRESS2 0x52
#define SPD_EEPROM_ADDRESS3 0x53

3
include/configs/socrates.h
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@ -42,9 +42,6 @@
#define CFG_SYS_CCSRBAR_PHYS_LOW CFG_SYS_CCSRBAR
/* DDR Setup */
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
#define CFG_SYS_DDR_SDRAM_BASE 0x00000000
#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE