arm: socfpga: Add reset driver support for Arria 10
Add reset driver support for Arria 10. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
This commit is contained in:
Ley Foon Tan
Marek Vasut
parent
d83b8193ad
commit
827e6a7e0d
@ -10,6 +10,8 @@
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obj-y += misc.o timer.o reset_manager.o clock_manager.o \
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fpga_manager.o board.o
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obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += reset_manager_arria10.o
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obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
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# QTS-generated config file wrappers
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@ -43,6 +43,8 @@ void socfpga_per_reset_all(void);
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#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
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#include <asm/arch/reset_manager_gen5.h>
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#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
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#include <asm/arch/reset_manager_arria10.h>
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#endif
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#endif /* _RESET_MANAGER_H_ */
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147
arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
Normal file
147
arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
Normal file
@ -0,0 +1,147 @@
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/*
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* Copyright (C) 2016-2017 Intel Corporation
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#ifndef _RESET_MANAGER_ARRIA10_H_
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#define _RESET_MANAGER_ARRIA10_H_
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#include <dt-bindings/reset/altr,rst-mgr-a10.h>
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void socfpga_watchdog_disable(void);
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void socfpga_reset_deassert_noc_ddr_scheduler(void);
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int socfpga_is_wdt_in_reset(void);
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void socfpga_emac_manage_reset(ulong emacbase, u32 state);
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int socfpga_reset_deassert_bridges_handoff(void);
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void socfpga_reset_assert_fpga_connected_peripherals(void);
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void socfpga_reset_deassert_osc1wd0(void);
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void socfpga_reset_uart(int assert);
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int socfpga_bridges_reset(int enable);
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struct socfpga_reset_manager {
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u32 stat;
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u32 ramstat;
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u32 miscstat;
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u32 ctrl;
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u32 hdsken;
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u32 hdskreq;
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u32 hdskack;
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u32 counts;
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u32 mpumodrst;
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u32 per0modrst;
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u32 per1modrst;
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u32 brgmodrst;
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u32 sysmodrst;
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u32 coldmodrst;
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u32 nrstmodrst;
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u32 dbgmodrst;
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u32 mpuwarmmask;
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u32 per0warmmask;
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u32 per1warmmask;
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u32 brgwarmmask;
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u32 syswarmmask;
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u32 nrstwarmmask;
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u32 l3warmmask;
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u32 tststa;
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u32 tstscratch;
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u32 hdsktimeout;
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u32 hmcintr;
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u32 hmcintren;
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u32 hmcintrens;
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u32 hmcintrenr;
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u32 hmcgpout;
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u32 hmcgpin;
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};
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/*
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* SocFPGA Arria10 reset IDs, bank mapping is as follows:
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* 0 ... mpumodrst
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* 1 ... per0modrst
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* 2 ... per1modrst
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* 3 ... brgmodrst
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* 4 ... sysmodrst
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*/
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#define RSTMGR_EMAC0 RSTMGR_DEFINE(1, 0)
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#define RSTMGR_EMAC1 RSTMGR_DEFINE(1, 1)
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#define RSTMGR_EMAC2 RSTMGR_DEFINE(1, 2)
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#define RSTMGR_NAND RSTMGR_DEFINE(1, 5)
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#define RSTMGR_QSPI RSTMGR_DEFINE(1, 6)
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#define RSTMGR_SDMMC RSTMGR_DEFINE(1, 7)
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#define RSTMGR_DMA RSTMGR_DEFINE(1, 16)
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#define RSTMGR_SPIM0 RSTMGR_DEFINE(1, 17)
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#define RSTMGR_SPIM1 RSTMGR_DEFINE(1, 18)
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#define RSTMGR_L4WD0 RSTMGR_DEFINE(2, 0)
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#define RSTMGR_L4WD1 RSTMGR_DEFINE(2, 1)
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#define RSTMGR_L4SYSTIMER0 RSTMGR_DEFINE(2, 2)
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#define RSTMGR_L4SYSTIMER1 RSTMGR_DEFINE(2, 3)
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#define RSTMGR_SPTIMER0 RSTMGR_DEFINE(2, 4)
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#define RSTMGR_SPTIMER1 RSTMGR_DEFINE(2, 5)
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#define RSTMGR_UART0 RSTMGR_DEFINE(2, 16)
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#define RSTMGR_UART1 RSTMGR_DEFINE(2, 17)
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#define RSTMGR_DDRSCH RSTMGR_DEFINE(3, 6)
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#define ALT_RSTMGR_CTL_SWWARMRSTREQ_SET_MSK BIT(1)
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#define ALT_RSTMGR_PER0MODRST_EMAC0_SET_MSK BIT(0)
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#define ALT_RSTMGR_PER0MODRST_EMAC1_SET_MSK BIT(1)
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#define ALT_RSTMGR_PER0MODRST_EMAC2_SET_MSK BIT(2)
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#define ALT_RSTMGR_PER0MODRST_USB0_SET_MSK BIT(3)
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#define ALT_RSTMGR_PER0MODRST_USB1_SET_MSK BIT(4)
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#define ALT_RSTMGR_PER0MODRST_NAND_SET_MSK BIT(5)
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#define ALT_RSTMGR_PER0MODRST_QSPI_SET_MSK BIT(6)
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#define ALT_RSTMGR_PER0MODRST_SDMMC_SET_MSK BIT(7)
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#define ALT_RSTMGR_PER0MODRST_EMACECC0_SET_MSK BIT(8)
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#define ALT_RSTMGR_PER0MODRST_EMACECC1_SET_MSK BIT(9)
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#define ALT_RSTMGR_PER0MODRST_EMACECC2_SET_MSK BIT(10)
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#define ALT_RSTMGR_PER0MODRST_USBECC0_SET_MSK BIT(11)
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#define ALT_RSTMGR_PER0MODRST_USBECC1_SET_MSK BIT(12)
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#define ALT_RSTMGR_PER0MODRST_NANDECC_SET_MSK BIT(13)
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#define ALT_RSTMGR_PER0MODRST_QSPIECC_SET_MSK BIT(14)
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#define ALT_RSTMGR_PER0MODRST_SDMMCECC_SET_MSK BIT(15)
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#define ALT_RSTMGR_PER0MODRST_DMA_SET_MSK BIT(16)
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#define ALT_RSTMGR_PER0MODRST_SPIM0_SET_MSK BIT(17)
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#define ALT_RSTMGR_PER0MODRST_SPIM1_SET_MSK BIT(18)
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#define ALT_RSTMGR_PER0MODRST_SPIS0_SET_MSK BIT(19)
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#define ALT_RSTMGR_PER0MODRST_SPIS1_SET_MSK BIT(20)
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#define ALT_RSTMGR_PER0MODRST_DMAECC_SET_MSK BIT(21)
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#define ALT_RSTMGR_PER0MODRST_EMACPTP_SET_MSK BIT(22)
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#define ALT_RSTMGR_PER0MODRST_DMAIF0_SET_MSK BIT(24)
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#define ALT_RSTMGR_PER0MODRST_DMAIF1_SET_MSK BIT(25)
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#define ALT_RSTMGR_PER0MODRST_DMAIF2_SET_MSK BIT(26)
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#define ALT_RSTMGR_PER0MODRST_DMAIF3_SET_MSK BIT(27)
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#define ALT_RSTMGR_PER0MODRST_DMAIF4_SET_MSK BIT(28)
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#define ALT_RSTMGR_PER0MODRST_DMAIF5_SET_MSK BIT(29)
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#define ALT_RSTMGR_PER0MODRST_DMAIF6_SET_MSK BIT(30)
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#define ALT_RSTMGR_PER0MODRST_DMAIF7_SET_MSK BIT(31)
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#define ALT_RSTMGR_PER1MODRST_WD0_SET_MSK BIT(0)
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#define ALT_RSTMGR_PER1MODRST_WD1_SET_MSK BIT(1)
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#define ALT_RSTMGR_PER1MODRST_L4SYSTMR0_SET_MSK BIT(2)
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#define ALT_RSTMGR_PER1MODRST_L4SYSTMR1_SET_MSK BIT(3)
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#define ALT_RSTMGR_PER1MODRST_SPTMR0_SET_MSK BIT(4)
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#define ALT_RSTMGR_PER1MODRST_SPTMR1_SET_MSK BIT(5)
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#define ALT_RSTMGR_PER1MODRST_I2C0_SET_MSK BIT(8)
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#define ALT_RSTMGR_PER1MODRST_I2C1_SET_MSK BIT(9)
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#define ALT_RSTMGR_PER1MODRST_I2C2_SET_MSK BIT(10)
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#define ALT_RSTMGR_PER1MODRST_I2C3_SET_MSK BIT(11)
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#define ALT_RSTMGR_PER1MODRST_I2C4_SET_MSK BIT(12)
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#define ALT_RSTMGR_PER1MODRST_UART0_SET_MSK BIT(16)
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#define ALT_RSTMGR_PER1MODRST_UART1_SET_MSK BIT(17)
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#define ALT_RSTMGR_PER1MODRST_GPIO0_SET_MSK BIT(24)
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#define ALT_RSTMGR_PER1MODRST_GPIO1_SET_MSK BIT(25)
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#define ALT_RSTMGR_PER1MODRST_GPIO2_SET_MSK BIT(26)
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#define ALT_RSTMGR_BRGMODRST_H2F_SET_MSK BIT(0)
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#define ALT_RSTMGR_BRGMODRST_LWH2F_SET_MSK BIT(1)
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#define ALT_RSTMGR_BRGMODRST_F2H_SET_MSK BIT(2)
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#define ALT_RSTMGR_BRGMODRST_F2SSDRAM0_SET_MSK BIT(3)
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#define ALT_RSTMGR_BRGMODRST_F2SSDRAM1_SET_MSK BIT(4)
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#define ALT_RSTMGR_BRGMODRST_F2SSDRAM2_SET_MSK BIT(5)
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#define ALT_RSTMGR_BRGMODRST_DDRSCH_SET_MSK BIT(6)
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#define ALT_RSTMGR_HDSKEN_SDRSELFREFEN_SET_MSK BIT(0)
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#define ALT_RSTMGR_HDSKEN_FPGAMGRHSEN_SET_MSK BIT(1)
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#define ALT_RSTMGR_HDSKEN_FPGAHSEN_SET_MSK BIT(2)
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#define ALT_RSTMGR_HDSKEN_ETRSTALLEN_SET_MSK BIT(3)
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#endif /* _RESET_MANAGER_ARRIA10_H_ */
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383
arch/arm/mach-socfpga/reset_manager_arria10.c
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383
arch/arm/mach-socfpga/reset_manager_arria10.c
Normal file
@ -0,0 +1,383 @@
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/*
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* Copyright (C) 2016-2017 Intel Corporation
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#include <asm/io.h>
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#include <asm/arch/fpga_manager.h>
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#include <asm/arch/misc.h>
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#include <asm/arch/reset_manager.h>
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#include <asm/arch/system_manager.h>
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#include <common.h>
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#include <errno.h>
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#include <fdtdec.h>
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#include <wait_bit.h>
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DECLARE_GLOBAL_DATA_PTR;
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static const struct socfpga_reset_manager *reset_manager_base =
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(void *)SOCFPGA_RSTMGR_ADDRESS;
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static const struct socfpga_system_manager *sysmgr_regs =
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(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
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#define ECC_MASK (ALT_RSTMGR_PER0MODRST_EMACECC0_SET_MSK | \
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ALT_RSTMGR_PER0MODRST_EMACECC1_SET_MSK | \
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ALT_RSTMGR_PER0MODRST_EMACECC2_SET_MSK | \
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ALT_RSTMGR_PER0MODRST_NANDECC_SET_MSK | \
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ALT_RSTMGR_PER0MODRST_QSPIECC_SET_MSK | \
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ALT_RSTMGR_PER0MODRST_SDMMCECC_SET_MSK)
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void socfpga_reset_uart(int assert)
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{
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unsigned int com_port;
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com_port = uart_com_port(gd->fdt_blob);
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if (com_port == SOCFPGA_UART1_ADDRESS)
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socfpga_per_reset(SOCFPGA_RESET(UART1), assert);
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else if (com_port == SOCFPGA_UART0_ADDRESS)
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socfpga_per_reset(SOCFPGA_RESET(UART0), assert);
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}
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static const u32 per0fpgamasks[] = {
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ALT_RSTMGR_PER0MODRST_EMACECC0_SET_MSK |
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ALT_RSTMGR_PER0MODRST_EMAC0_SET_MSK,
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ALT_RSTMGR_PER0MODRST_EMACECC1_SET_MSK |
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ALT_RSTMGR_PER0MODRST_EMAC1_SET_MSK,
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ALT_RSTMGR_PER0MODRST_EMACECC2_SET_MSK |
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ALT_RSTMGR_PER0MODRST_EMAC2_SET_MSK,
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0, /* i2c0 per1mod */
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0, /* i2c1 per1mod */
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0, /* i2c0_emac */
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0, /* i2c1_emac */
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0, /* i2c2_emac */
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ALT_RSTMGR_PER0MODRST_NANDECC_SET_MSK |
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ALT_RSTMGR_PER0MODRST_NAND_SET_MSK,
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ALT_RSTMGR_PER0MODRST_QSPIECC_SET_MSK |
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ALT_RSTMGR_PER0MODRST_QSPI_SET_MSK,
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ALT_RSTMGR_PER0MODRST_SDMMCECC_SET_MSK |
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ALT_RSTMGR_PER0MODRST_SDMMC_SET_MSK,
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ALT_RSTMGR_PER0MODRST_SPIM0_SET_MSK,
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ALT_RSTMGR_PER0MODRST_SPIM1_SET_MSK,
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ALT_RSTMGR_PER0MODRST_SPIS0_SET_MSK,
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ALT_RSTMGR_PER0MODRST_SPIS1_SET_MSK,
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0, /* uart0 per1mod */
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0, /* uart1 per1mod */
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};
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static const u32 per1fpgamasks[] = {
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0, /* emac0 per0mod */
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0, /* emac1 per0mod */
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0, /* emac2 per0mod */
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ALT_RSTMGR_PER1MODRST_I2C0_SET_MSK,
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ALT_RSTMGR_PER1MODRST_I2C1_SET_MSK,
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ALT_RSTMGR_PER1MODRST_I2C2_SET_MSK, /* i2c0_emac */
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ALT_RSTMGR_PER1MODRST_I2C3_SET_MSK, /* i2c1_emac */
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ALT_RSTMGR_PER1MODRST_I2C4_SET_MSK, /* i2c2_emac */
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0, /* nand per0mod */
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0, /* qspi per0mod */
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0, /* sdmmc per0mod */
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0, /* spim0 per0mod */
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0, /* spim1 per0mod */
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0, /* spis0 per0mod */
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0, /* spis1 per0mod */
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ALT_RSTMGR_PER1MODRST_UART0_SET_MSK,
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ALT_RSTMGR_PER1MODRST_UART1_SET_MSK,
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};
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struct bridge_cfg {
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int compat_id;
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u32 mask_noc;
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u32 mask_rstmgr;
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};
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static const struct bridge_cfg bridge_cfg_tbl[] = {
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{
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COMPAT_ALTERA_SOCFPGA_H2F_BRG,
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ALT_SYSMGR_NOC_H2F_SET_MSK,
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ALT_RSTMGR_BRGMODRST_H2F_SET_MSK,
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},
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{
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COMPAT_ALTERA_SOCFPGA_LWH2F_BRG,
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ALT_SYSMGR_NOC_LWH2F_SET_MSK,
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ALT_RSTMGR_BRGMODRST_LWH2F_SET_MSK,
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},
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{
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COMPAT_ALTERA_SOCFPGA_F2H_BRG,
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ALT_SYSMGR_NOC_F2H_SET_MSK,
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ALT_RSTMGR_BRGMODRST_F2H_SET_MSK,
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},
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{
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COMPAT_ALTERA_SOCFPGA_F2SDR0,
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ALT_SYSMGR_NOC_F2SDR0_SET_MSK,
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ALT_RSTMGR_BRGMODRST_F2SSDRAM0_SET_MSK,
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},
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{
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COMPAT_ALTERA_SOCFPGA_F2SDR1,
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ALT_SYSMGR_NOC_F2SDR1_SET_MSK,
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ALT_RSTMGR_BRGMODRST_F2SSDRAM1_SET_MSK,
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},
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{
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COMPAT_ALTERA_SOCFPGA_F2SDR2,
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ALT_SYSMGR_NOC_F2SDR2_SET_MSK,
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ALT_RSTMGR_BRGMODRST_F2SSDRAM2_SET_MSK,
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},
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};
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/* Disable the watchdog (toggle reset to watchdog) */
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void socfpga_watchdog_disable(void)
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{
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/* assert reset for watchdog */
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setbits_le32(&reset_manager_base->per1modrst,
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ALT_RSTMGR_PER1MODRST_WD0_SET_MSK);
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}
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/* Release NOC ddr scheduler from reset */
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void socfpga_reset_deassert_noc_ddr_scheduler(void)
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{
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clrbits_le32(&reset_manager_base->brgmodrst,
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ALT_RSTMGR_BRGMODRST_DDRSCH_SET_MSK);
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}
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/* Check whether Watchdog in reset state? */
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int socfpga_is_wdt_in_reset(void)
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{
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u32 val;
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val = readl(&reset_manager_base->per1modrst);
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val &= ALT_RSTMGR_PER1MODRST_WD0_SET_MSK;
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/* return 0x1 if watchdog in reset */
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return val;
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}
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/* emacbase: base address of emac to enable/disable reset
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* state: 0 - disable reset, !0 - enable reset
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*/
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void socfpga_emac_manage_reset(ulong emacbase, u32 state)
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{
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ulong eccmask;
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ulong emacmask;
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switch (emacbase) {
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case SOCFPGA_EMAC0_ADDRESS:
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eccmask = ALT_RSTMGR_PER0MODRST_EMACECC0_SET_MSK;
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emacmask = ALT_RSTMGR_PER0MODRST_EMAC0_SET_MSK;
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break;
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case SOCFPGA_EMAC1_ADDRESS:
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eccmask = ALT_RSTMGR_PER0MODRST_EMACECC1_SET_MSK;
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emacmask = ALT_RSTMGR_PER0MODRST_EMAC1_SET_MSK;
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break;
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case SOCFPGA_EMAC2_ADDRESS:
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eccmask = ALT_RSTMGR_PER0MODRST_EMACECC2_SET_MSK;
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emacmask = ALT_RSTMGR_PER0MODRST_EMAC2_SET_MSK;
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break;
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default:
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error("emac base address unexpected! %lx", emacbase);
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hang();
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break;
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}
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if (state) {
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/* Enable ECC OCP first */
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setbits_le32(&reset_manager_base->per0modrst, eccmask);
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setbits_le32(&reset_manager_base->per0modrst, emacmask);
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} else {
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/* Disable ECC OCP first */
|
||||
clrbits_le32(&reset_manager_base->per0modrst, emacmask);
|
||||
clrbits_le32(&reset_manager_base->per0modrst, eccmask);
|
||||
}
|
||||
}
|
||||
|
||||
static int get_bridge_init_val(const void *blob, int compat_id)
|
||||
{
|
||||
int node;
|
||||
|
||||
node = fdtdec_next_compatible(blob, 0, compat_id);
|
||||
if (node < 0)
|
||||
return 0;
|
||||
|
||||
return fdtdec_get_uint(blob, node, "init-val", 0);
|
||||
}
|
||||
|
||||
/* Enable bridges (hps2fpga, lwhps2fpga, fpga2hps, fpga2sdram) per handoff */
|
||||
int socfpga_reset_deassert_bridges_handoff(void)
|
||||
{
|
||||
u32 mask_noc = 0, mask_rstmgr = 0;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(bridge_cfg_tbl); i++) {
|
||||
if (get_bridge_init_val(gd->fdt_blob,
|
||||
bridge_cfg_tbl[i].compat_id)) {
|
||||
mask_noc |= bridge_cfg_tbl[i].mask_noc;
|
||||
mask_rstmgr |= bridge_cfg_tbl[i].mask_rstmgr;
|
||||
}
|
||||
}
|
||||
|
||||
/* clear idle request to all bridges */
|
||||
setbits_le32(&sysmgr_regs->noc_idlereq_clr, mask_noc);
|
||||
|
||||
/* Release bridges from reset state per handoff value */
|
||||
clrbits_le32(&reset_manager_base->brgmodrst, mask_rstmgr);
|
||||
|
||||
/* Poll until all idleack to 0, timeout at 1000ms */
|
||||
return wait_for_bit(__func__, &sysmgr_regs->noc_idleack, mask_noc,
|
||||
false, 1000, false);
|
||||
}
|
||||
|
||||
void socfpga_reset_assert_fpga_connected_peripherals(void)
|
||||
{
|
||||
u32 mask0 = 0;
|
||||
u32 mask1 = 0;
|
||||
u32 fpga_pinux_addr = SOCFPGA_PINMUX_FPGA_INTERFACE_ADDRESS;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(per1fpgamasks); i++) {
|
||||
if (readl(fpga_pinux_addr)) {
|
||||
mask0 |= per0fpgamasks[i];
|
||||
mask1 |= per1fpgamasks[i];
|
||||
}
|
||||
fpga_pinux_addr += sizeof(u32);
|
||||
}
|
||||
|
||||
setbits_le32(&reset_manager_base->per0modrst, mask0 & ECC_MASK);
|
||||
setbits_le32(&reset_manager_base->per1modrst, mask1);
|
||||
setbits_le32(&reset_manager_base->per0modrst, mask0);
|
||||
}
|
||||
|
||||
/* Release L4 OSC1 Watchdog Timer 0 from reset through reset manager */
|
||||
void socfpga_reset_deassert_osc1wd0(void)
|
||||
{
|
||||
clrbits_le32(&reset_manager_base->per1modrst,
|
||||
ALT_RSTMGR_PER1MODRST_WD0_SET_MSK);
|
||||
}
|
||||
|
||||
/*
|
||||
* Assert or de-assert SoCFPGA reset manager reset.
|
||||
*/
|
||||
void socfpga_per_reset(u32 reset, int set)
|
||||
{
|
||||
const u32 *reg;
|
||||
u32 rstmgr_bank = RSTMGR_BANK(reset);
|
||||
|
||||
switch (rstmgr_bank) {
|
||||
case 0:
|
||||
reg = &reset_manager_base->mpumodrst;
|
||||
break;
|
||||
case 1:
|
||||
reg = &reset_manager_base->per0modrst;
|
||||
break;
|
||||
case 2:
|
||||
reg = &reset_manager_base->per1modrst;
|
||||
break;
|
||||
case 3:
|
||||
reg = &reset_manager_base->brgmodrst;
|
||||
break;
|
||||
case 4:
|
||||
reg = &reset_manager_base->sysmodrst;
|
||||
break;
|
||||
|
||||
default:
|
||||
return;
|
||||
}
|
||||
|
||||
if (set)
|
||||
setbits_le32(reg, 1 << RSTMGR_RESET(reset));
|
||||
else
|
||||
clrbits_le32(reg, 1 << RSTMGR_RESET(reset));
|
||||
}
|
||||
|
||||
/*
|
||||
* Assert reset on every peripheral but L4WD0.
|
||||
* Watchdog must be kept intact to prevent glitches
|
||||
* and/or hangs.
|
||||
* For the Arria10, we disable all the peripherals except L4 watchdog0,
|
||||
* L4 Timer 0, and ECC.
|
||||
*/
|
||||
void socfpga_per_reset_all(void)
|
||||
{
|
||||
const u32 l4wd0 = (1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0)) |
|
||||
(1 << RSTMGR_RESET(SOCFPGA_RESET(L4SYSTIMER0))));
|
||||
unsigned mask_ecc_ocp =
|
||||
ALT_RSTMGR_PER0MODRST_EMACECC0_SET_MSK |
|
||||
ALT_RSTMGR_PER0MODRST_EMACECC1_SET_MSK |
|
||||
ALT_RSTMGR_PER0MODRST_EMACECC2_SET_MSK |
|
||||
ALT_RSTMGR_PER0MODRST_USBECC0_SET_MSK |
|
||||
ALT_RSTMGR_PER0MODRST_USBECC1_SET_MSK |
|
||||
ALT_RSTMGR_PER0MODRST_NANDECC_SET_MSK |
|
||||
ALT_RSTMGR_PER0MODRST_QSPIECC_SET_MSK |
|
||||
ALT_RSTMGR_PER0MODRST_SDMMCECC_SET_MSK;
|
||||
|
||||
/* disable all components except ECC_OCP, L4 Timer0 and L4 WD0 */
|
||||
writel(~l4wd0, &reset_manager_base->per1modrst);
|
||||
setbits_le32(&reset_manager_base->per0modrst, ~mask_ecc_ocp);
|
||||
|
||||
/* Finally disable the ECC_OCP */
|
||||
setbits_le32(&reset_manager_base->per0modrst, mask_ecc_ocp);
|
||||
}
|
||||
|
||||
#if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
|
||||
int socfpga_bridges_reset(int enable)
|
||||
{
|
||||
/* For SoCFPGA-VT, this is NOP. */
|
||||
return 0;
|
||||
}
|
||||
#else
|
||||
int socfpga_bridges_reset(int enable)
|
||||
{
|
||||
int ret;
|
||||
|
||||
/* Disable all the bridges (hps2fpga, lwhps2fpga, fpga2hps,
|
||||
fpga2sdram) */
|
||||
/* set idle request to all bridges */
|
||||
writel(ALT_SYSMGR_NOC_H2F_SET_MSK |
|
||||
ALT_SYSMGR_NOC_LWH2F_SET_MSK |
|
||||
ALT_SYSMGR_NOC_F2H_SET_MSK |
|
||||
ALT_SYSMGR_NOC_F2SDR0_SET_MSK |
|
||||
ALT_SYSMGR_NOC_F2SDR1_SET_MSK |
|
||||
ALT_SYSMGR_NOC_F2SDR2_SET_MSK,
|
||||
&sysmgr_regs->noc_idlereq_set);
|
||||
|
||||
/* Enable the NOC timeout */
|
||||
writel(ALT_SYSMGR_NOC_TMO_EN_SET_MSK, &sysmgr_regs->noc_timeout);
|
||||
|
||||
/* Poll until all idleack to 1 */
|
||||
ret = wait_for_bit(__func__, &sysmgr_regs->noc_idleack,
|
||||
ALT_SYSMGR_NOC_H2F_SET_MSK |
|
||||
ALT_SYSMGR_NOC_LWH2F_SET_MSK |
|
||||
ALT_SYSMGR_NOC_F2H_SET_MSK |
|
||||
ALT_SYSMGR_NOC_F2SDR0_SET_MSK |
|
||||
ALT_SYSMGR_NOC_F2SDR1_SET_MSK |
|
||||
ALT_SYSMGR_NOC_F2SDR2_SET_MSK,
|
||||
true, 10000, false);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* Poll until all idlestatus to 1 */
|
||||
ret = wait_for_bit(__func__, &sysmgr_regs->noc_idlestatus,
|
||||
ALT_SYSMGR_NOC_H2F_SET_MSK |
|
||||
ALT_SYSMGR_NOC_LWH2F_SET_MSK |
|
||||
ALT_SYSMGR_NOC_F2H_SET_MSK |
|
||||
ALT_SYSMGR_NOC_F2SDR0_SET_MSK |
|
||||
ALT_SYSMGR_NOC_F2SDR1_SET_MSK |
|
||||
ALT_SYSMGR_NOC_F2SDR2_SET_MSK,
|
||||
true, 10000, false);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* Put all bridges (except NOR DDR scheduler) into reset state */
|
||||
setbits_le32(&reset_manager_base->brgmodrst,
|
||||
(ALT_RSTMGR_BRGMODRST_H2F_SET_MSK |
|
||||
ALT_RSTMGR_BRGMODRST_LWH2F_SET_MSK |
|
||||
ALT_RSTMGR_BRGMODRST_F2H_SET_MSK |
|
||||
ALT_RSTMGR_BRGMODRST_F2SSDRAM0_SET_MSK |
|
||||
ALT_RSTMGR_BRGMODRST_F2SSDRAM1_SET_MSK |
|
||||
ALT_RSTMGR_BRGMODRST_F2SSDRAM2_SET_MSK));
|
||||
|
||||
/* Disable NOC timeout */
|
||||
writel(0, &sysmgr_regs->noc_timeout);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
110
include/dt-bindings/reset/altr,rst-mgr-a10.h
Normal file
110
include/dt-bindings/reset/altr,rst-mgr-a10.h
Normal file
@ -0,0 +1,110 @@
|
||||
/*
|
||||
* Copyright (c) 2014, Steffen Trumtrar <s.trumtrar@pengutronix.de>
|
||||
*
|
||||
* This software is licensed under the terms of the GNU General Public
|
||||
* License version 2, as published by the Free Software Foundation, and
|
||||
* may be copied, distributed, and modified under those terms.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_A10_H
|
||||
#define _DT_BINDINGS_RESET_ALTR_RST_MGR_A10_H
|
||||
|
||||
/* MPUMODRST */
|
||||
#define CPU0_RESET 0
|
||||
#define CPU1_RESET 1
|
||||
#define WDS_RESET 2
|
||||
#define SCUPER_RESET 3
|
||||
|
||||
/* PER0MODRST */
|
||||
#define EMAC0_RESET 32
|
||||
#define EMAC1_RESET 33
|
||||
#define EMAC2_RESET 34
|
||||
#define USB0_RESET 35
|
||||
#define USB1_RESET 36
|
||||
#define NAND_RESET 37
|
||||
#define QSPI_RESET 38
|
||||
#define SDMMC_RESET 39
|
||||
#define EMAC0_OCP_RESET 40
|
||||
#define EMAC1_OCP_RESET 41
|
||||
#define EMAC2_OCP_RESET 42
|
||||
#define USB0_OCP_RESET 43
|
||||
#define USB1_OCP_RESET 44
|
||||
#define NAND_OCP_RESET 45
|
||||
#define QSPI_OCP_RESET 46
|
||||
#define SDMMC_OCP_RESET 47
|
||||
#define DMA_RESET 48
|
||||
#define SPIM0_RESET 49
|
||||
#define SPIM1_RESET 50
|
||||
#define SPIS0_RESET 51
|
||||
#define SPIS1_RESET 52
|
||||
#define DMA_OCP_RESET 53
|
||||
#define EMAC_PTP_RESET 54
|
||||
/* 55 is empty*/
|
||||
#define DMAIF0_RESET 56
|
||||
#define DMAIF1_RESET 57
|
||||
#define DMAIF2_RESET 58
|
||||
#define DMAIF3_RESET 59
|
||||
#define DMAIF4_RESET 60
|
||||
#define DMAIF5_RESET 61
|
||||
#define DMAIF6_RESET 62
|
||||
#define DMAIF7_RESET 63
|
||||
|
||||
/* PER1MODRST */
|
||||
#define L4WD0_RESET 64
|
||||
#define L4WD1_RESET 65
|
||||
#define L4SYSTIMER0_RESET 66
|
||||
#define L4SYSTIMER1_RESET 67
|
||||
#define SPTIMER0_RESET 68
|
||||
#define SPTIMER1_RESET 69
|
||||
/* 70-71 is reserved */
|
||||
#define I2C0_RESET 72
|
||||
#define I2C1_RESET 73
|
||||
#define I2C2_RESET 74
|
||||
#define I2C3_RESET 75
|
||||
#define I2C4_RESET 76
|
||||
/* 77-79 is reserved */
|
||||
#define UART0_RESET 80
|
||||
#define UART1_RESET 81
|
||||
/* 82-87 is reserved */
|
||||
#define GPIO0_RESET 88
|
||||
#define GPIO1_RESET 89
|
||||
#define GPIO2_RESET 90
|
||||
|
||||
/* BRGMODRST */
|
||||
#define HPS2FPGA_RESET 96
|
||||
#define LWHPS2FPGA_RESET 97
|
||||
#define FPGA2HPS_RESET 98
|
||||
#define F2SSDRAM0_RESET 99
|
||||
#define F2SSDRAM1_RESET 100
|
||||
#define F2SSDRAM2_RESET 101
|
||||
#define DDRSCH_RESET 102
|
||||
|
||||
/* SYSMODRST*/
|
||||
#define ROM_RESET 128
|
||||
#define OCRAM_RESET 129
|
||||
/* 130 is reserved */
|
||||
#define FPGAMGR_RESET 131
|
||||
#define S2F_RESET 132
|
||||
#define SYSDBG_RESET 133
|
||||
#define OCRAM_OCP_RESET 134
|
||||
|
||||
/* COLDMODRST */
|
||||
#define CLKMGRCOLD_RESET 160
|
||||
/* 161-162 is reserved */
|
||||
#define S2FCOLD_RESET 163
|
||||
#define TIMESTAMPCOLD_RESET 164
|
||||
#define TAPCOLD_RESET 165
|
||||
#define HMCCOLD_RESET 166
|
||||
#define IOMGRCOLD_RESET 167
|
||||
|
||||
/* NRSTMODRST */
|
||||
#define NRSTPINOE_RESET 192
|
||||
|
||||
/* DBGMODRST */
|
||||
#define DBG_RESET 224
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user