Merge git://www.denx.de/git/u-boot-imx
Signed-off-by: Tom Rini <trini@konsulko.com> Conflicts: include/configs/imx6qdl_icore_rqs.h include/configs/imx6ul_geam.h include/configs/imx6ul_isiot.h
This commit is contained in:
Tom Rini
commit
821560fd8e
@ -58,6 +58,14 @@ static ulong imx_get_mpllclk(void)
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return imx_decode_pll(readl(&ccm->mpctl), fref);
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}
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static ulong imx_get_upllclk(void)
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{
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struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
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ulong fref = MXC_HCLK;
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return imx_decode_pll(readl(&ccm->upctl), fref);
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}
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static ulong imx_get_armclk(void)
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{
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struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
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@ -95,7 +103,8 @@ static ulong imx_get_ipgclk(void)
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static ulong imx_get_perclk(int clk)
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{
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struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
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ulong fref = imx_get_ahbclk();
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ulong fref = readl(&ccm->mcr) & (1 << clk) ? imx_get_upllclk() :
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imx_get_ahbclk();
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ulong div;
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div = readl(&ccm->pcdr[CCM_PERCLK_REG(clk)]);
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@ -104,6 +113,25 @@ static ulong imx_get_perclk(int clk)
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return fref / div;
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}
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int imx_set_perclk(enum mxc_clock clk, bool from_upll, unsigned int freq)
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{
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struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
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ulong fref = from_upll ? imx_get_upllclk() : imx_get_ahbclk();
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ulong div = (fref + freq - 1) / freq;
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if (clk > MXC_UART_CLK || !div || --div > CCM_PERCLK_MASK)
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return -EINVAL;
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clrsetbits_le32(&ccm->pcdr[CCM_PERCLK_REG(clk)],
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CCM_PERCLK_MASK << CCM_PERCLK_SHIFT(clk),
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div << CCM_PERCLK_SHIFT(clk));
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if (from_upll)
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setbits_le32(&ccm->mcr, 1 << clk);
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else
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clrbits_le32(&ccm->mcr, 1 << clk);
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return 0;
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}
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unsigned int mxc_get_clock(enum mxc_clock clk)
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{
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if (clk >= MXC_CLK_NUM)
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@ -158,7 +158,7 @@ u32 get_cpu_speed_grade_hz(void)
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* OCOTP_MEM0[7:6] (see Fusemap Description Table offset 0x480)
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* defines a 2-bit Temperature Grade
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*
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* return temperature grade and min/max temperature in celcius
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* return temperature grade and min/max temperature in Celsius
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*/
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#define OCOTP_MEM0_TEMP_SHIFT 6
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@ -25,6 +25,13 @@ config TARGET_MX7DSABRESD
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select DM
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select DM_THERMAL
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config TARGET_PICO_IMX7D
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bool "pico-imx7d"
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select BOARD_LATE_INIT
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select MX7D
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select DM
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select DM_THERMAL
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config TARGET_WARP7
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bool "warp7"
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select BOARD_LATE_INIT
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@ -45,6 +52,7 @@ config SYS_SOC
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default "mx7"
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source "board/freescale/mx7dsabresd/Kconfig"
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source "board/technexion/pico-imx7d/Kconfig"
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source "board/toradex/colibri_imx7/Kconfig"
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source "board/warp7/Kconfig"
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@ -275,6 +275,9 @@ u32 get_ahb_clk(void)
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void arch_preboot_os(void)
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{
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#if defined(CONFIG_PCIE_IMX)
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imx_pcie_remove();
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#endif
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#if defined(CONFIG_CMD_SATA)
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sata_stop();
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#if defined(CONFIG_MX6)
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@ -51,6 +51,7 @@ enum mxc_clock {
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MXC_CLK_NUM
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};
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int imx_set_perclk(enum mxc_clock clk, bool from_upll, unsigned int freq);
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unsigned int mxc_get_clock(enum mxc_clock clk);
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#define imx_get_uartclk() mxc_get_clock(MXC_UART_CLK)
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@ -53,6 +53,11 @@ int board_late_init(void)
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break;
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}
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if (is_mx6ul())
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setenv("console", "ttymxc0");
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else
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setenv("console", "ttymxc3");
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setenv_fdt_file();
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return 0;
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@ -7,6 +7,6 @@ config SYS_VENDOR
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default "engicam"
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config SYS_CONFIG_NAME
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default "imx6ul_geam"
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default "imx6-engicam"
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endif
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@ -7,6 +7,6 @@ config SYS_VENDOR
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default "engicam"
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config SYS_CONFIG_NAME
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default "imx6qdl_icore"
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default "imx6-engicam"
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endif
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@ -7,6 +7,6 @@ config SYS_VENDOR
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default "engicam"
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config SYS_CONFIG_NAME
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default "imx6qdl_icore_rqs"
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default "imx6-engicam"
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endif
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@ -7,6 +7,6 @@ config SYS_VENDOR
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default "engicam"
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config SYS_CONFIG_NAME
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default "imx6ul_isiot"
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default "imx6-engicam"
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endif
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@ -175,6 +175,12 @@ int board_mmc_init(bd_t *bis)
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imx_iomux_v3_setup_multiple_pads(sdhc1_pads, ARRAY_SIZE(sdhc1_pads));
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/*
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* Set the eSDHC1 PER clock to the maximum frequency lower than or equal
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* to 50 MHz that can be obtained, which requires to use UPLL as the
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* clock source. This actually gives 48 MHz.
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*/
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imx_set_perclk(MXC_ESDHC1_CLK, true, 50000000);
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esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
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return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
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}
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@ -3,6 +3,4 @@ M: Fabio Estevam <fabio.estevam@nxp.com>
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S: Maintained
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F: board/freescale/mx6sabresd/
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F: include/configs/mx6sabresd.h
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F: configs/mx6dlsabresd_defconfig
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F: configs/mx6qsabresd_defconfig
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F: configs/mx6sabresd_spl_defconfig
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F: configs/mx6sabresd_defconfig
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@ -1,56 +1,47 @@
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How to use and build U-Boot on mx6sabresd:
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----------------------------------
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Currently there are four methods for booting mx6sabresd boards:
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1. Booting from SD card via normal U-Boot (u-boot.imx)
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2. Booting from eMMC via normal U-Boot
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3. Booting via SPL (SPL and u-boot.img)
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4. Booting via Falcon mode (SPL launches the kernel directly)
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1. Booting from SD card via normal U-Boot
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How to use and build U-Boot on mx6sabresd
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-----------------------------------------
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$ make mx6qsabresd_defconfig (If you want to build for mx6qsabresd)
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The following methods can be used for booting mx6sabresd boards:
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or
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1. Booting from SD card
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$ make mx6dlsabresd_defconfig (If you want to build for mx6dlsabresd)
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2. Booting from eMMC
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3. Booting via Falcon mode (SPL launches the kernel directly)
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1. Booting from SD card via SPL
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-------------------------------
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mx6sabresd_defconfig target supports mx6q/mx6dl/mx6qp sabresd variants.
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In order to build it:
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$ make mx6sabresd_defconfig
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$ make
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This will generate the image called u-boot.imx.
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This will generate the SPL and u-boot.img binaries.
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- Flash the u-boot.imx binary into the SD card:
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- Flash the SPL binary into the SD card:
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$ sudo dd if=u-boot.imx of=/dev/sdb bs=1K seek=1 && sync
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$ sudo dd if=SPL of=/dev/sdX bs=1K seek=1 && sync
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- Flash the u-boot.img binary into the SD card:
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$ sudo dd if=u-boot.img of=/dev/sdX bs=1K seek=69 && sync
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2. Booting from eMMC via normal U-Boot
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--------------------------------------
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2. Booting from eMMC
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--------------------
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$ make mx6qsabresd_defconfig (If you want to build for mx6qsabresd)
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or
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$ make mx6dlsabresd_defconfig (If you want to build for mx6dlsabresd)
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$ make mx6sabresd_defconfig
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$ make
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This will generate the image called u-boot.imx.
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This will generate the SPL and u-boot.img binaries.
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- Flash the u-boot.imx binary into the eMMC:
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Set SW6 to download mode: 00001100
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Plug a usb cable to USB-OTG and load the u-boot image using the imx_usb_loader
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tool (https://github.com/boundarydevices/imx_usb_loader):
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$ sudo ./imx_usb u-boot.imx
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- Boot first from SD card as shown in the previous section
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In U-boot change the eMMC partition config:
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@ -60,48 +51,29 @@ Mount the eMMC in the host PC:
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=> ums 0 mmc 2
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Flash the u-boot.imx binary
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- Flash SPL and u-boot.img binaries into the eMMC:
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$ sudo dd if=u-boot.imx of=/dev/sdX bs=1K seek=1 && sync
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$ sudo dd if=SPL of=/dev/sdX bs=1K seek=1 && sync
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$ sudo dd if=u-boot.img of=/dev/sdX bs=1K seek=69 && sync
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Set SW6 to eMMC 8-bit boot: 11010110
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3. Booting via SPL
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------------------
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Other method for building U-Boot on mx6qsabresd and mx6qpsabresd is
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through SPL. In order to do so:
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$ make mx6sabresd_spl_defconfig
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$ make
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This will generate the SPL image called SPL and the u-boot.img.
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- Flash the SPL image into the SD card:
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$ sudo dd if=SPL of=/dev/sdb bs=1K seek=1 && sync
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- Flash the u-boot.img image into the SD card:
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$ sudo dd if=u-boot.img of=/dev/sdbbs=1K seek=69 && sync
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4. Booting via Falcon mode
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3. Booting via Falcon mode
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--------------------------
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$ make mx6sabresd_spl_defconfig
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$ make mx6sabresd_defconfig
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$ make
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This will generate the SPL image called SPL and the u-boot.img.
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- Flash the SPL image into the SD card:
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$ sudo dd if=SPL of=/dev/sdb bs=1K seek=1 oflag=sync status=none && sync
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$ sudo dd if=SPL of=/dev/sdX bs=1K seek=1 oflag=sync status=none && sync
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- Flash the u-boot.img image into the SD card:
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$ sudo dd if=u-boot.img of=/dev/sdbbs=1K seek=69 oflag=sync status=none && sync
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$ sudo dd if=u-boot.img of=/dev/sdX bs=1K seek=69 oflag=sync status=none && sync
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Create a partition for root file system and extract it there:
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15
board/technexion/pico-imx7d/Kconfig
Normal file
15
board/technexion/pico-imx7d/Kconfig
Normal file
@ -0,0 +1,15 @@
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if TARGET_PICO_IMX7D
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config SYS_BOARD
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default "pico-imx7d"
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config SYS_VENDOR
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default "technexion"
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config SYS_SOC
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default "mx7"
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config SYS_CONFIG_NAME
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default "pico-imx7d"
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endif
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7
board/technexion/pico-imx7d/MAINTAINERS
Normal file
7
board/technexion/pico-imx7d/MAINTAINERS
Normal file
@ -0,0 +1,7 @@
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Technexion PICO-IMX7D board
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M: Wig Cheng <wig.cheng@technexion.com>
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M: Vanessa Maegima <vanessa.maegima@nxp.com>
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S: Maintained
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F: board/technexion/pico-imx7d/
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F: include/configs/pico-imx7d.h
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F: configs/pico-imx7d_defconfig
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6
board/technexion/pico-imx7d/Makefile
Normal file
6
board/technexion/pico-imx7d/Makefile
Normal file
@ -0,0 +1,6 @@
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# (C) Copyright 2017 NXP Semiconductors
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y := pico-imx7d.o
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49
board/technexion/pico-imx7d/README
Normal file
49
board/technexion/pico-imx7d/README
Normal file
@ -0,0 +1,49 @@
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How to update U-Boot on pico-imx7d board
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----------------------------------------
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Required software on the host PC:
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- imx_usb_loader: https://github.com/boundarydevices/imx_usb_loader
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Build U-Boot for pico:
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$ make mrproper
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$ make pico-imx7d_defconfig
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$ make
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This generates the U-Boot binary called u-boot.imx.
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Put pico board in USB download mode (refer to the PICO-iMX7D Quick Start Guide
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page 3)
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Connect a USB to serial adapter between the host PC and pico.
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Connect a USB cable between the OTG pico port and the host PC.
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Open a terminal program such as minicom.
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Copy u-boot.imx to the imx_usb_loader folder.
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Load u-boot.imx via USB:
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$ sudo ./imx_usb u-boot.imx
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Then U-Boot starts and its messages appear in the console program.
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Use the default environment variables:
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|
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=> env default -f -a
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=> saveenv
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Run the UMS command:
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=> ums 0 mmc 0
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Transfer u-boot.imx to be flashed into the eMMC:
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$ sudo dd if=u-boot.imx of=/dev/sdX bs=1K seek=1; sync
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Remove power from the pico board.
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Put pico board into normal boot mode.
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Power up the board and the new updated U-Boot should boot from eMMC.
|
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98
board/technexion/pico-imx7d/imximage.cfg
Normal file
98
board/technexion/pico-imx7d/imximage.cfg
Normal file
@ -0,0 +1,98 @@
|
||||
/*
|
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* Copyright (C) 2017 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
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*
|
||||
* Refer docs/README.imxmage for more details about how-to configure
|
||||
* and create imximage boot image
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||||
*
|
||||
* The syntax is taken as close as possible with the kwbimage
|
||||
*/
|
||||
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||||
#define __ASSEMBLY__
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#include <config.h>
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||||
|
||||
/* image version */
|
||||
|
||||
IMAGE_VERSION 2
|
||||
|
||||
BOOT_FROM sd
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||||
|
||||
/* Secure boot support */
|
||||
#ifdef CONFIG_SECURE_BOOT
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CSF CONFIG_CSF_SIZE
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#endif
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|
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/*
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* Device Configuration Data (DCD)
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||||
*
|
||||
* Each entry must have the format:
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||||
* Addr-type Address Value
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*
|
||||
* where:
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||||
* Addr-type register length (1,2 or 4 bytes)
|
||||
* Address absolute address of the register
|
||||
* value value to be stored in the register
|
||||
*/
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||||
|
||||
DATA 4 0x30340004 0x4F400005
|
||||
/* Clear then set bit30 to ensure exit from DDR retention */
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||||
DATA 4 0x30360388 0x40000000
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DATA 4 0x30360384 0x40000000
|
||||
|
||||
DATA 4 0x30391000 0x00000002
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||||
DATA 4 0x307a0000 0x01040001
|
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DATA 4 0x307a01a0 0x80400003
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DATA 4 0x307a01a4 0x00100020
|
||||
DATA 4 0x307a01a8 0x80100004
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||||
DATA 4 0x307a0064 0x00400046
|
||||
DATA 4 0x307a0490 0x00000001
|
||||
DATA 4 0x307a00d0 0x00020083
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||||
DATA 4 0x307a00d4 0x00690000
|
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DATA 4 0x307a00dc 0x09300004
|
||||
DATA 4 0x307a00e0 0x04080000
|
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DATA 4 0x307a00e4 0x00100004
|
||||
DATA 4 0x307a00f4 0x0000033f
|
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DATA 4 0x307a0100 0x09081109
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||||
DATA 4 0x307a0104 0x0007020d
|
||||
DATA 4 0x307a0108 0x03040407
|
||||
DATA 4 0x307a010c 0x00002006
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||||
DATA 4 0x307a0110 0x04020205
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DATA 4 0x307a0114 0x03030202
|
||||
DATA 4 0x307a0120 0x00000803
|
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DATA 4 0x307a0180 0x00800020
|
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DATA 4 0x307a0184 0x02000100
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DATA 4 0x307a0190 0x02098204
|
||||
DATA 4 0x307a0194 0x00030303
|
||||
DATA 4 0x307a0200 0x00000016
|
||||
DATA 4 0x307a0204 0x00080808
|
||||
DATA 4 0x307a0210 0x00000f0f
|
||||
DATA 4 0x307a0214 0x07070707
|
||||
DATA 4 0x307a0218 0x0f070707
|
||||
DATA 4 0x307a0240 0x06000604
|
||||
DATA 4 0x307a0244 0x00000001
|
||||
DATA 4 0x30391000 0x00000000
|
||||
DATA 4 0x30790000 0x17420f40
|
||||
DATA 4 0x30790004 0x10210100
|
||||
DATA 4 0x30790010 0x00060807
|
||||
DATA 4 0x307900b0 0x1010007e
|
||||
DATA 4 0x3079009c 0x00000b24
|
||||
DATA 4 0x30790020 0x08080808
|
||||
DATA 4 0x30790030 0x08080808
|
||||
DATA 4 0x30790050 0x01000010
|
||||
DATA 4 0x30790050 0x00000010
|
||||
|
||||
DATA 4 0x307900c0 0x0e407304
|
||||
DATA 4 0x307900c0 0x0e447304
|
||||
DATA 4 0x307900c0 0x0e447306
|
||||
|
||||
CHECK_BITS_SET 4 0x307900c4 0x1
|
||||
|
||||
DATA 4 0x307900c0 0x0e407304
|
||||
|
||||
DATA 4 0x30384130 0x00000000
|
||||
DATA 4 0x30340020 0x00000178
|
||||
DATA 4 0x30384130 0x00000002
|
||||
DATA 4 0x30790018 0x0000000f
|
||||
|
||||
CHECK_BITS_SET 4 0x307a0004 0x1
|
||||
289
board/technexion/pico-imx7d/pico-imx7d.c
Normal file
289
board/technexion/pico-imx7d/pico-imx7d.c
Normal file
@ -0,0 +1,289 @@
|
||||
/*
|
||||
* Copyright (C) 2017 NXP Semiconductors
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/crm_regs.h>
|
||||
#include <asm/arch/imx-regs.h>
|
||||
#include <asm/arch/mx7-pins.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <asm/gpio.h>
|
||||
#include <asm/imx-common/iomux-v3.h>
|
||||
#include <asm/imx-common/mxc_i2c.h>
|
||||
#include <asm/io.h>
|
||||
#include <common.h>
|
||||
#include <fsl_esdhc.h>
|
||||
#include <i2c.h>
|
||||
#include <miiphy.h>
|
||||
#include <mmc.h>
|
||||
#include <netdev.h>
|
||||
#include <usb.h>
|
||||
#include <power/pmic.h>
|
||||
#include <power/pfuze3000_pmic.h>
|
||||
#include "../../freescale/common/pfuze.h"
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \
|
||||
PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)
|
||||
|
||||
#define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
|
||||
PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
|
||||
|
||||
#define ENET_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
|
||||
#define ENET_PAD_CTRL_MII (PAD_CTL_DSE_3P3V_32OHM)
|
||||
|
||||
#define ENET_RX_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
|
||||
|
||||
#define I2C_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
|
||||
PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU100KOHM)
|
||||
|
||||
#ifdef CONFIG_SYS_I2C_MXC
|
||||
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
|
||||
/* I2C4 for PMIC */
|
||||
static struct i2c_pads_info i2c_pad_info4 = {
|
||||
.scl = {
|
||||
.i2c_mode = MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL | PC,
|
||||
.gpio_mode = MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16 | PC,
|
||||
.gp = IMX_GPIO_NR(6, 16),
|
||||
},
|
||||
.sda = {
|
||||
.i2c_mode = MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA | PC,
|
||||
.gpio_mode = MX7D_PAD_SAI1_RX_BCLK__GPIO6_IO17 | PC,
|
||||
.gp = IMX_GPIO_NR(6, 17),
|
||||
},
|
||||
};
|
||||
#endif
|
||||
|
||||
int dram_init(void)
|
||||
{
|
||||
gd->ram_size = PHYS_SDRAM_SIZE;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_POWER
|
||||
#define I2C_PMIC 3
|
||||
int power_init_board(void)
|
||||
{
|
||||
struct pmic *p;
|
||||
int ret;
|
||||
unsigned int reg, rev_id;
|
||||
|
||||
ret = power_pfuze3000_init(I2C_PMIC);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
p = pmic_get("PFUZE3000");
|
||||
ret = pmic_probe(p);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
pmic_reg_read(p, PFUZE3000_DEVICEID, ®);
|
||||
pmic_reg_read(p, PFUZE3000_REVID, &rev_id);
|
||||
printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id);
|
||||
|
||||
/* disable Low Power Mode during standby mode */
|
||||
pmic_reg_read(p, PFUZE3000_LDOGCTL, ®);
|
||||
reg |= 0x1;
|
||||
pmic_reg_write(p, PFUZE3000_LDOGCTL, reg);
|
||||
|
||||
/* SW1A/1B mode set to APS/APS */
|
||||
reg = 0x8;
|
||||
pmic_reg_write(p, PFUZE3000_SW1AMODE, reg);
|
||||
pmic_reg_write(p, PFUZE3000_SW1BMODE, reg);
|
||||
|
||||
/* SW1A/1B standby voltage set to 1.025V */
|
||||
reg = 0xd;
|
||||
pmic_reg_write(p, PFUZE3000_SW1ASTBY, reg);
|
||||
pmic_reg_write(p, PFUZE3000_SW1BSTBY, reg);
|
||||
|
||||
/* decrease SW1B normal voltage to 0.975V */
|
||||
pmic_reg_read(p, PFUZE3000_SW1BVOLT, ®);
|
||||
reg &= ~0x1f;
|
||||
reg |= PFUZE3000_SW1AB_SETP(975);
|
||||
pmic_reg_write(p, PFUZE3000_SW1BVOLT, reg);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
static iomux_v3_cfg_t const wdog_pads[] = {
|
||||
MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
};
|
||||
|
||||
static iomux_v3_cfg_t const uart5_pads[] = {
|
||||
MX7D_PAD_I2C4_SCL__UART5_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
|
||||
MX7D_PAD_I2C4_SDA__UART5_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
|
||||
};
|
||||
|
||||
static iomux_v3_cfg_t const usdhc3_emmc_pads[] = {
|
||||
MX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX7D_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX7D_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX7D_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX7D_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX7D_PAD_SD3_DATA4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX7D_PAD_SD3_DATA5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX7D_PAD_SD3_DATA6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX7D_PAD_SD3_DATA7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX7D_PAD_GPIO1_IO14__GPIO1_IO14 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
};
|
||||
|
||||
#ifdef CONFIG_FEC_MXC
|
||||
static iomux_v3_cfg_t const fec1_pads[] = {
|
||||
MX7D_PAD_SD2_CD_B__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
|
||||
MX7D_PAD_SD2_WP__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
|
||||
MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
|
||||
MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
|
||||
MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
|
||||
MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
|
||||
MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
|
||||
MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
|
||||
MX7D_PAD_SD3_STROBE__GPIO6_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
MX7D_PAD_SD3_RESET_B__GPIO6_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
};
|
||||
|
||||
#define FEC1_RST_GPIO IMX_GPIO_NR(6, 11)
|
||||
|
||||
static void setup_iomux_fec(void)
|
||||
{
|
||||
imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
|
||||
|
||||
gpio_direction_output(FEC1_RST_GPIO, 0);
|
||||
udelay(500);
|
||||
gpio_set_value(FEC1_RST_GPIO, 1);
|
||||
}
|
||||
|
||||
int board_eth_init(bd_t *bis)
|
||||
{
|
||||
setup_iomux_fec();
|
||||
|
||||
return fecmxc_initialize_multi(bis, 0,
|
||||
CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
|
||||
}
|
||||
|
||||
static int setup_fec(void)
|
||||
{
|
||||
struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
|
||||
= (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
|
||||
|
||||
/* Use 125M anatop REF_CLK1 for ENET1, clear gpr1[13], gpr1[17] */
|
||||
clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
|
||||
(IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK |
|
||||
IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK), 0);
|
||||
|
||||
return set_clk_enet(ENET_125MHz);
|
||||
}
|
||||
|
||||
int board_phy_config(struct phy_device *phydev)
|
||||
{
|
||||
unsigned short val;
|
||||
|
||||
/* To enable AR8035 ouput a 125MHz clk from CLK_25M */
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
|
||||
|
||||
val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
|
||||
val &= 0xffe7;
|
||||
val |= 0x18;
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
|
||||
|
||||
/* introduce tx clock delay */
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
|
||||
val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
|
||||
val |= 0x0100;
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
|
||||
|
||||
if (phydev->drv->config)
|
||||
phydev->drv->config(phydev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
static void setup_iomux_uart(void)
|
||||
{
|
||||
imx_iomux_v3_setup_multiple_pads(uart5_pads, ARRAY_SIZE(uart5_pads));
|
||||
}
|
||||
|
||||
static struct fsl_esdhc_cfg usdhc_cfg[1] = {
|
||||
{USDHC3_BASE_ADDR},
|
||||
};
|
||||
|
||||
int board_mmc_getcd(struct mmc *mmc)
|
||||
{
|
||||
/* Assume uSDHC3 emmc is always present */
|
||||
return 1;
|
||||
}
|
||||
|
||||
int board_mmc_init(bd_t *bis)
|
||||
{
|
||||
imx_iomux_v3_setup_multiple_pads(
|
||||
usdhc3_emmc_pads, ARRAY_SIZE(usdhc3_emmc_pads));
|
||||
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
|
||||
|
||||
return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
|
||||
}
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
setup_iomux_uart();
|
||||
|
||||
#ifdef CONFIG_SYS_I2C_MXC
|
||||
setup_i2c(3, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info4);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
/* address of boot parameters */
|
||||
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
|
||||
|
||||
#ifdef CONFIG_FEC_MXC
|
||||
setup_fec();
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_late_init(void)
|
||||
{
|
||||
struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
|
||||
|
||||
imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
|
||||
|
||||
set_wdog_reset(wdog);
|
||||
|
||||
/*
|
||||
* Do not assert internal WDOG_RESET_B_DEB(controlled by bit 4),
|
||||
* since we use PMIC_PWRON to reset the board.
|
||||
*/
|
||||
clrsetbits_le16(&wdog->wcr, 0, 0x10);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int checkboard(void)
|
||||
{
|
||||
puts("Board: i.MX7D PICOSOM\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_usb_phy_mode(int port)
|
||||
{
|
||||
return USB_INIT_DEVICE;
|
||||
}
|
||||
@ -43,3 +43,5 @@ CONFIG_PINCTRL_IMX6=y
|
||||
CONFIG_MXC_UART=y
|
||||
CONFIG_IMX_THERMAL=y
|
||||
CONFIG_VIDEO_IPUV3=y
|
||||
CONFIG_PHYLIB=y
|
||||
CONFIG_PHY_SMSC=y
|
||||
|
||||
47
configs/imx6qdl_icore_nand_defconfig
Normal file
47
configs/imx6qdl_icore_nand_defconfig
Normal file
@ -0,0 +1,47 @@
|
||||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_MX6=y
|
||||
CONFIG_SPL_GPIO_SUPPORT=y
|
||||
CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||
CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||
CONFIG_TARGET_MX6Q_ICORE=y
|
||||
CONFIG_SPL_SERIAL_SUPPORT=y
|
||||
CONFIG_SPL_WATCHDOG_SUPPORT=y
|
||||
# CONFIG_CMD_BMODE is not set
|
||||
CONFIG_VIDEO=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="imx6q-icore"
|
||||
CONFIG_OF_LIST="imx6q-icore imx6dl-icore"
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_SIGNATURE=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,ENV_IS_IN_NAND"
|
||||
CONFIG_BOOTDELAY=3
|
||||
CONFIG_SPL=y
|
||||
CONFIG_SPL_DMA_SUPPORT=y
|
||||
CONFIG_HUSH_PARSER=y
|
||||
CONFIG_SYS_PROMPT="icorem6qdl> "
|
||||
# CONFIG_CMD_IMLS is not set
|
||||
CONFIG_CMD_MEMTEST=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_NAND=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_MII=y
|
||||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_CACHE=y
|
||||
CONFIG_CMD_EXT4=y
|
||||
CONFIG_CMD_EXT4_WRITE=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_CMD_FS_GENERIC=y
|
||||
CONFIG_CMD_UBI=y
|
||||
# CONFIG_BLK is not set
|
||||
CONFIG_SYS_I2C_MXC=y
|
||||
# CONFIG_DM_MMC_OPS is not set
|
||||
CONFIG_NAND_MXS=y
|
||||
CONFIG_FEC_MXC=y
|
||||
CONFIG_PINCTRL=y
|
||||
CONFIG_PINCTRL_IMX6=y
|
||||
CONFIG_MXC_UART=y
|
||||
CONFIG_IMX_THERMAL=y
|
||||
CONFIG_VIDEO_IPUV3=y
|
||||
CONFIG_PHYLIB=y
|
||||
CONFIG_PHY_SMSC=y
|
||||
@ -40,3 +40,6 @@ CONFIG_FEC_MXC=y
|
||||
CONFIG_PINCTRL=y
|
||||
CONFIG_PINCTRL_IMX6=y
|
||||
CONFIG_MXC_UART=y
|
||||
CONFIG_PHYLIB=y
|
||||
CONFIG_PHY_MICREL=y
|
||||
CONFIG_PHY_MICREL_KSZ9021=y
|
||||
|
||||
@ -40,3 +40,5 @@ CONFIG_PINCTRL=y
|
||||
CONFIG_PINCTRL_IMX6=y
|
||||
CONFIG_MXC_UART=y
|
||||
CONFIG_IMX_THERMAL=y
|
||||
CONFIG_PHYLIB=y
|
||||
CONFIG_PHY_SMSC=y
|
||||
|
||||
@ -41,3 +41,5 @@ CONFIG_PINCTRL=y
|
||||
CONFIG_PINCTRL_IMX6=y
|
||||
CONFIG_MXC_UART=y
|
||||
CONFIG_IMX_THERMAL=y
|
||||
CONFIG_PHYLIB=y
|
||||
CONFIG_PHY_SMSC=y
|
||||
|
||||
@ -38,3 +38,5 @@ CONFIG_PINCTRL=y
|
||||
CONFIG_PINCTRL_IMX6=y
|
||||
CONFIG_MXC_UART=y
|
||||
CONFIG_IMX_THERMAL=y
|
||||
CONFIG_PHYLIB=y
|
||||
CONFIG_PHY_SMSC=y
|
||||
|
||||
@ -40,3 +40,5 @@ CONFIG_PINCTRL=y
|
||||
CONFIG_PINCTRL_IMX6=y
|
||||
CONFIG_MXC_UART=y
|
||||
CONFIG_IMX_THERMAL=y
|
||||
CONFIG_PHYLIB=y
|
||||
CONFIG_PHY_SMSC=y
|
||||
|
||||
@ -41,3 +41,5 @@ CONFIG_PINCTRL=y
|
||||
CONFIG_PINCTRL_IMX6=y
|
||||
CONFIG_MXC_UART=y
|
||||
CONFIG_IMX_THERMAL=y
|
||||
CONFIG_PHYLIB=y
|
||||
CONFIG_PHY_SMSC=y
|
||||
|
||||
35
configs/pico-imx7d_defconfig
Normal file
35
configs/pico-imx7d_defconfig
Normal file
@ -0,0 +1,35 @@
|
||||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_MX7=y
|
||||
CONFIG_TARGET_PICO_IMX7D=y
|
||||
CONFIG_IMX_RDC=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/technexion/pico-imx7d/imximage.cfg"
|
||||
CONFIG_HUSH_PARSER=y
|
||||
CONFIG_CMD_BOOTZ=y
|
||||
# CONFIG_CMD_BOOTD is not set
|
||||
# CONFIG_CMD_IMI is not set
|
||||
# CONFIG_CMD_IMLS is not set
|
||||
# CONFIG_CMD_XIMG is not set
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_PART=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_DHCP=y
|
||||
CONFIG_CMD_CACHE=y
|
||||
CONFIG_CMD_EXT2=y
|
||||
CONFIG_CMD_EXT4=y
|
||||
CONFIG_CMD_EXT4_WRITE=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_CMD_USB=y
|
||||
CONFIG_CMD_USB_MASS_STORAGE=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_MXC_USB_OTG_HACTIVE=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_USB_GADGET=y
|
||||
CONFIG_CI_UDC=y
|
||||
CONFIG_USB_GADGET_DOWNLOAD=y
|
||||
CONFIG_G_DNL_MANUFACTURER="FSL"
|
||||
CONFIG_G_DNL_VENDOR_NUM=0x0525
|
||||
CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
|
||||
CONFIG_OF_LIBFDT=y
|
||||
@ -521,7 +521,13 @@ out:
|
||||
|
||||
static void set_sysctl(struct mmc *mmc, uint clock)
|
||||
{
|
||||
int div, pre_div;
|
||||
int div = 1;
|
||||
#ifdef ARCH_MXC
|
||||
int pre_div = 1;
|
||||
#else
|
||||
int pre_div = 2;
|
||||
#endif
|
||||
int ddr_pre_div = mmc->ddr_mode ? 2 : 1;
|
||||
struct fsl_esdhc_priv *priv = mmc->priv;
|
||||
struct fsl_esdhc *regs = priv->esdhc_regs;
|
||||
int sdhc_clk = priv->sdhc_clk;
|
||||
@ -530,18 +536,13 @@ static void set_sysctl(struct mmc *mmc, uint clock)
|
||||
if (clock < mmc->cfg->f_min)
|
||||
clock = mmc->cfg->f_min;
|
||||
|
||||
if (sdhc_clk / 16 > clock) {
|
||||
for (pre_div = 2; pre_div < 256; pre_div *= 2)
|
||||
if ((sdhc_clk / pre_div) <= (clock * 16))
|
||||
break;
|
||||
} else
|
||||
pre_div = 2;
|
||||
while (sdhc_clk / (16 * pre_div * ddr_pre_div) > clock && pre_div < 256)
|
||||
pre_div *= 2;
|
||||
|
||||
for (div = 1; div <= 16; div++)
|
||||
if ((sdhc_clk / (div * pre_div)) <= clock)
|
||||
break;
|
||||
while (sdhc_clk / (div * pre_div * ddr_pre_div) > clock && div < 16)
|
||||
div++;
|
||||
|
||||
pre_div >>= mmc->ddr_mode ? 2 : 1;
|
||||
pre_div >>= 1;
|
||||
div -= 1;
|
||||
|
||||
clk = (pre_div << 8) | (div << 4);
|
||||
@ -723,20 +724,6 @@ static const struct mmc_ops esdhc_ops = {
|
||||
.getcd = esdhc_getcd,
|
||||
};
|
||||
|
||||
static int fsl_esdhc_cfg_to_priv(struct fsl_esdhc_cfg *cfg,
|
||||
struct fsl_esdhc_priv *priv)
|
||||
{
|
||||
if (!cfg || !priv)
|
||||
return -EINVAL;
|
||||
|
||||
priv->esdhc_regs = (struct fsl_esdhc *)(unsigned long)(cfg->esdhc_base);
|
||||
priv->bus_width = cfg->max_bus_width;
|
||||
priv->sdhc_clk = cfg->sdhc_clk;
|
||||
priv->wp_enable = cfg->wp_enable;
|
||||
|
||||
return 0;
|
||||
};
|
||||
|
||||
static int fsl_esdhc_init(struct fsl_esdhc_priv *priv)
|
||||
{
|
||||
struct fsl_esdhc *regs;
|
||||
@ -833,6 +820,21 @@ static int fsl_esdhc_init(struct fsl_esdhc_priv *priv)
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifndef CONFIG_DM_MMC
|
||||
static int fsl_esdhc_cfg_to_priv(struct fsl_esdhc_cfg *cfg,
|
||||
struct fsl_esdhc_priv *priv)
|
||||
{
|
||||
if (!cfg || !priv)
|
||||
return -EINVAL;
|
||||
|
||||
priv->esdhc_regs = (struct fsl_esdhc *)(unsigned long)(cfg->esdhc_base);
|
||||
priv->bus_width = cfg->max_bus_width;
|
||||
priv->sdhc_clk = cfg->sdhc_clk;
|
||||
priv->wp_enable = cfg->wp_enable;
|
||||
|
||||
return 0;
|
||||
};
|
||||
|
||||
int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
|
||||
{
|
||||
struct fsl_esdhc_priv *priv;
|
||||
@ -871,6 +873,7 @@ int fsl_esdhc_mmc_init(bd_t *bis)
|
||||
cfg->sdhc_clk = gd->arch.sdhc_clk;
|
||||
return fsl_esdhc_initialize(bis, cfg);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
|
||||
void mmc_adapter_card_type_ident(void)
|
||||
|
||||
@ -92,6 +92,14 @@ config PHY_MICREL_KSZ9031
|
||||
|
||||
endif # PHY_MICREL
|
||||
|
||||
config PHY_MICREL_KSZ9021
|
||||
bool "Micrel KSZ9021 Ethernet PHYs support"
|
||||
depends on PHY_MICREL
|
||||
help
|
||||
KSZ9021 is a completely integrated triple speed (10Base-T/100Base-TX/1000Base-T)
|
||||
Ethernet Physical Layer Transceiver for transmission and reception of data over
|
||||
standard CAT-5 unshielded twisted pair (UTP) cable.
|
||||
|
||||
config PHY_MSCC
|
||||
bool "Microsemi Corp Ethernet PHYs support"
|
||||
|
||||
|
||||
@ -42,6 +42,9 @@
|
||||
|
||||
/* PCIe Port Logic registers (memory-mapped) */
|
||||
#define PL_OFFSET 0x700
|
||||
#define PCIE_PL_PFLR (PL_OFFSET + 0x08)
|
||||
#define PCIE_PL_PFLR_LINK_STATE_MASK (0x3f << 16)
|
||||
#define PCIE_PL_PFLR_FORCE_LINK (1 << 15)
|
||||
#define PCIE_PHY_DEBUG_R0 (PL_OFFSET + 0x28)
|
||||
#define PCIE_PHY_DEBUG_R1 (PL_OFFSET + 0x2c)
|
||||
#define PCIE_PHY_DEBUG_R1_LINK_UP (1 << 4)
|
||||
@ -445,6 +448,36 @@ static int imx6_pcie_assert_core_reset(void)
|
||||
/* Power up PCIe PHY */
|
||||
setbits_le32(&gpc_regs->cntr, PCIE_PHY_PUP_REQ);
|
||||
#else
|
||||
/*
|
||||
* If the bootloader already enabled the link we need some special
|
||||
* handling to get the core back into a state where it is safe to
|
||||
* touch it for configuration. As there is no dedicated reset signal
|
||||
* wired up for MX6QDL, we need to manually force LTSSM into "detect"
|
||||
* state before completely disabling LTSSM, which is a prerequisite
|
||||
* for core configuration.
|
||||
*
|
||||
* If both LTSSM_ENABLE and REF_SSP_ENABLE are active we have a strong
|
||||
* indication that the bootloader activated the link.
|
||||
*/
|
||||
if (is_mx6dq()) {
|
||||
u32 val, gpr1, gpr12;
|
||||
|
||||
gpr1 = readl(&iomuxc_regs->gpr[1]);
|
||||
gpr12 = readl(&iomuxc_regs->gpr[12]);
|
||||
if ((gpr1 & IOMUXC_GPR1_PCIE_REF_CLK_EN) &&
|
||||
(gpr12 & IOMUXC_GPR12_PCIE_CTL_2)) {
|
||||
val = readl(MX6_DBI_ADDR + PCIE_PL_PFLR);
|
||||
val &= ~PCIE_PL_PFLR_LINK_STATE_MASK;
|
||||
val |= PCIE_PL_PFLR_FORCE_LINK;
|
||||
|
||||
imx_pcie_fix_dabt_handler(true);
|
||||
writel(val, MX6_DBI_ADDR + PCIE_PL_PFLR);
|
||||
imx_pcie_fix_dabt_handler(false);
|
||||
|
||||
gpr12 &= ~IOMUXC_GPR12_PCIE_CTL_2;
|
||||
writel(val, &iomuxc_regs->gpr[12]);
|
||||
}
|
||||
}
|
||||
setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_TEST_POWERDOWN);
|
||||
clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_REF_SSP_EN);
|
||||
#endif
|
||||
@ -652,6 +685,11 @@ void imx_pcie_init(void)
|
||||
}
|
||||
}
|
||||
|
||||
void imx_pcie_remove(void)
|
||||
{
|
||||
imx6_pcie_assert_core_reset();
|
||||
}
|
||||
|
||||
/* Probe function. */
|
||||
void pci_init_board(void)
|
||||
{
|
||||
|
||||
@ -1,3 +1,11 @@
|
||||
/*
|
||||
* Copyright 2017 NXP
|
||||
*
|
||||
* Peng Fan <peng.fan@nxp.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <fdtdec.h>
|
||||
#include <errno.h>
|
||||
@ -306,7 +314,7 @@ static int pfuze100_regulator_probe(struct udevice *dev)
|
||||
|
||||
static int pfuze100_regulator_mode(struct udevice *dev, int op, int *opmode)
|
||||
{
|
||||
unsigned char val;
|
||||
int val;
|
||||
struct pfuze100_regulator_platdata *plat = dev_get_platdata(dev);
|
||||
struct pfuze100_regulator_desc *desc = plat->desc;
|
||||
|
||||
@ -376,7 +384,7 @@ static int pfuze100_regulator_mode(struct udevice *dev, int op, int *opmode)
|
||||
|
||||
static int pfuze100_regulator_enable(struct udevice *dev, int op, bool *enable)
|
||||
{
|
||||
unsigned char val;
|
||||
int val;
|
||||
int ret, on_off;
|
||||
struct dm_regulator_uclass_platdata *uc_pdata =
|
||||
dev_get_uclass_platdata(dev);
|
||||
@ -440,7 +448,7 @@ static int pfuze100_regulator_enable(struct udevice *dev, int op, bool *enable)
|
||||
static int pfuze100_regulator_val(struct udevice *dev, int op, int *uV)
|
||||
{
|
||||
int i;
|
||||
unsigned char val;
|
||||
int val;
|
||||
struct pfuze100_regulator_platdata *plat = dev_get_platdata(dev);
|
||||
struct pfuze100_regulator_desc *desc = plat->desc;
|
||||
struct dm_regulator_uclass_platdata *uc_pdata =
|
||||
|
||||
@ -2,13 +2,13 @@
|
||||
* Copyright (C) 2016 Amarula Solutions B.V.
|
||||
* Copyright (C) 2016 Engicam S.r.l.
|
||||
*
|
||||
* Configuration settings for the Engicam i.CoreM6 QDL Starter Kits.
|
||||
* Configuration settings for the Engicam i.MX6 SOM Starter Kits.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __IMX6QLD_ICORE_CONFIG_H
|
||||
#define __IMX6QLD_ICORE_CONFIG_H
|
||||
#ifndef __IMX6_ENGICAM_CONFIG_H
|
||||
#define __IMX6_ENGICAM_CONFIG_H
|
||||
|
||||
#include <linux/sizes.h>
|
||||
#include "mx6_common.h"
|
||||
@ -40,9 +40,8 @@
|
||||
"splashpos=m,m\0" \
|
||||
"image=uImage\0" \
|
||||
"fit_image=fit.itb\0" \
|
||||
"console=ttymxc3\0" \
|
||||
"fdt_high=0xffffffff\0" \
|
||||
"fdt_addr=0x18000000\0" \
|
||||
"fdt_addr=" FDT_ADDR "\0" \
|
||||
"boot_fdt=try\0" \
|
||||
"mmcpart=1\0" \
|
||||
"nandroot=ubi0:rootfs rootfstype=ubifs\0" \
|
||||
@ -110,6 +109,14 @@
|
||||
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
|
||||
#define CONFIG_SYS_HZ 1000
|
||||
|
||||
#ifdef CONFIG_MX6UL
|
||||
# define DRAM_OFFSET(x) 0x87##x
|
||||
# define FDT_ADDR __stringify(DRAM_OFFSET(800000))
|
||||
#else
|
||||
# define DRAM_OFFSET(x) 0x1##x
|
||||
# define FDT_ADDR __stringify(DRAM_OFFSET(8000000))
|
||||
#endif
|
||||
|
||||
/* Physical Memory Map */
|
||||
#define CONFIG_NR_DRAM_BANKS 1
|
||||
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
|
||||
@ -130,14 +137,16 @@
|
||||
|
||||
/* UART */
|
||||
#ifdef CONFIG_MXC_UART
|
||||
# define CONFIG_MXC_UART_BASE UART4_BASE
|
||||
# ifdef CONFIG_MX6UL
|
||||
# define CONFIG_MXC_UART_BASE UART1_BASE
|
||||
# else
|
||||
# define CONFIG_MXC_UART_BASE UART4_BASE
|
||||
# endif
|
||||
#endif
|
||||
|
||||
/* MMC */
|
||||
#ifdef CONFIG_FSL_USDHC
|
||||
# define CONFIG_SYS_MMC_ENV_DEV 0
|
||||
# define CONFIG_SYS_FSL_USDHC_NUM 1
|
||||
# define CONFIG_SYS_FSL_ESDHC_ADDR 0
|
||||
#endif
|
||||
|
||||
/* NAND */
|
||||
@ -169,14 +178,15 @@
|
||||
|
||||
/* Ethernet */
|
||||
#ifdef CONFIG_FEC_MXC
|
||||
# define IMX_FEC_BASE ENET_BASE_ADDR
|
||||
# define CONFIG_FEC_MXC_PHYADDR 0
|
||||
# define CONFIG_FEC_XCV_TYPE RMII
|
||||
# define CONFIG_ETHPRIME "FEC"
|
||||
# ifdef CONFIG_TARGET_MX6Q_ICORE_RQS
|
||||
# define CONFIG_FEC_MXC_PHYADDR 3
|
||||
# define CONFIG_FEC_XCV_TYPE RGMII
|
||||
# else
|
||||
# define CONFIG_FEC_MXC_PHYADDR 0
|
||||
# define CONFIG_FEC_XCV_TYPE RMII
|
||||
# endif
|
||||
|
||||
# define CONFIG_MII
|
||||
# define CONFIG_PHYLIB
|
||||
# define CONFIG_PHY_SMSC
|
||||
#endif
|
||||
|
||||
/* Framebuffer */
|
||||
@ -202,9 +212,16 @@
|
||||
|
||||
# include "imx6_spl.h"
|
||||
# ifdef CONFIG_SPL_BUILD
|
||||
# if defined(CONFIG_TARGET_MX6Q_ICORE_RQS) || defined(CONFIG_TARGET_MX6UL_ISIOT)
|
||||
# define CONFIG_SYS_FSL_USDHC_NUM 2
|
||||
# else
|
||||
# define CONFIG_SYS_FSL_USDHC_NUM 1
|
||||
# endif
|
||||
|
||||
# define CONFIG_SYS_FSL_ESDHC_ADDR 0
|
||||
# undef CONFIG_DM_GPIO
|
||||
# undef CONFIG_DM_MMC
|
||||
# endif
|
||||
#endif
|
||||
|
||||
#endif /* __IMX6QLD_ICORE_CONFIG_H */
|
||||
#endif /* __IMX6_ENGICAM_CONFIG_H */
|
||||
@ -35,11 +35,6 @@
|
||||
*/
|
||||
#define CONFIG_SPL_PAD_TO 0x11000
|
||||
|
||||
/* NAND support */
|
||||
#if defined(CONFIG_SPL_NAND_SUPPORT)
|
||||
#define CONFIG_SPL_NAND_MXS
|
||||
#endif
|
||||
|
||||
/* MMC support */
|
||||
#if defined(CONFIG_SPL_MMC_SUPPORT)
|
||||
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
|
||||
|
||||
@ -1,146 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2016 Amarula Solutions B.V.
|
||||
* Copyright (C) 2016 Engicam S.r.l.
|
||||
*
|
||||
* Configuration settings for the Engicam i.CoreM6 QDL RQS Starter Kits.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __IMX6QLD_ICORE_RQS_CONFIG_H
|
||||
#define __IMX6QLD_ICORE_RQS_CONFIG_H
|
||||
|
||||
#include <linux/sizes.h>
|
||||
#include "mx6_common.h"
|
||||
|
||||
/* Size of malloc() pool */
|
||||
#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M)
|
||||
|
||||
/* Total Size of Environment Sector */
|
||||
#define CONFIG_ENV_SIZE SZ_128K
|
||||
|
||||
/* Allow to overwrite serial and ethaddr */
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
|
||||
/* Environment */
|
||||
#ifndef CONFIG_ENV_IS_NOWHERE
|
||||
/* Environment in MMC */
|
||||
# if defined(CONFIG_ENV_IS_IN_MMC)
|
||||
# define CONFIG_ENV_OFFSET 0x100000
|
||||
# endif
|
||||
#endif
|
||||
|
||||
/* Default environment */
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"script=boot.scr\0" \
|
||||
"image=uImage\0" \
|
||||
"fit_image=fit.itb\0" \
|
||||
"console=ttymxc3\0" \
|
||||
"fdt_high=0xffffffff\0" \
|
||||
"fdt_addr=0x18000000\0" \
|
||||
"boot_fdt=try\0" \
|
||||
"mmcpart=1\0" \
|
||||
"mmcautodetect=yes\0" \
|
||||
"mmcargs=setenv bootargs console=${console},${baudrate} " \
|
||||
"root=${mmcroot}\0" \
|
||||
"loadbootscript=" \
|
||||
"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
|
||||
"bootscript=echo Running bootscript from mmc ...; " \
|
||||
"source\0" \
|
||||
"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
|
||||
"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
|
||||
"loadfit=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${fit_image}\0" \
|
||||
"fitboot=echo Booting FIT image from mmc ...; " \
|
||||
"run mmcargs; " \
|
||||
"bootm ${loadaddr}\0" \
|
||||
"_mmcboot=run mmcargs; " \
|
||||
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
|
||||
"if run loadfdt; then " \
|
||||
"bootm ${loadaddr} - ${fdt_addr}; " \
|
||||
"else " \
|
||||
"if test ${boot_fdt} = try; then " \
|
||||
"bootm; " \
|
||||
"else " \
|
||||
"echo WARN: Cannot load the DT; " \
|
||||
"fi; " \
|
||||
"fi; " \
|
||||
"else " \
|
||||
"bootm; " \
|
||||
"fi\0" \
|
||||
"mmcboot=echo Booting from mmc ...; " \
|
||||
"mmc dev ${mmcdev};" \
|
||||
"if mmc rescan; then " \
|
||||
"if run loadbootscript; then " \
|
||||
"run bootscript; " \
|
||||
"else " \
|
||||
"if run loadfit; then " \
|
||||
"run fitboot; " \
|
||||
"else " \
|
||||
"if run loadimage; then " \
|
||||
"run _mmcboot; " \
|
||||
"fi; " \
|
||||
"fi; " \
|
||||
"fi; " \
|
||||
"fi\0"
|
||||
|
||||
#define CONFIG_BOOTCOMMAND "run $modeboot"
|
||||
|
||||
/* Miscellaneous configurable options */
|
||||
#define CONFIG_SYS_MEMTEST_START 0x80000000
|
||||
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x8000000)
|
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
|
||||
#define CONFIG_SYS_HZ 1000
|
||||
|
||||
/* Physical Memory Map */
|
||||
#define CONFIG_NR_DRAM_BANKS 1
|
||||
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
|
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
|
||||
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
|
||||
GENERATED_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
|
||||
CONFIG_SYS_INIT_SP_OFFSET)
|
||||
|
||||
/* FIT */
|
||||
#ifdef CONFIG_FIT
|
||||
# define CONFIG_IMAGE_FORMAT_LEGACY
|
||||
#endif
|
||||
|
||||
/* UART */
|
||||
#ifdef CONFIG_MXC_UART
|
||||
# define CONFIG_MXC_UART_BASE UART4_BASE
|
||||
#endif
|
||||
|
||||
/* MMC */
|
||||
#ifdef CONFIG_FSL_USDHC
|
||||
# define CONFIG_SYS_MMC_ENV_DEV 0
|
||||
# define CONFIG_SYS_FSL_USDHC_NUM 2
|
||||
# define CONFIG_SYS_FSL_ESDHC_ADDR 0
|
||||
#endif
|
||||
|
||||
/* Ethernet */
|
||||
#ifdef CONFIG_FEC_MXC
|
||||
# define CONFIG_FEC_MXC_PHYADDR 3
|
||||
# define CONFIG_FEC_XCV_TYPE RGMII
|
||||
|
||||
# define CONFIG_MII
|
||||
# define CONFIG_PHYLIB
|
||||
# define CONFIG_PHY_MICREL
|
||||
# define CONFIG_PHY_MICREL_KSZ9021
|
||||
#endif
|
||||
|
||||
/* SPL */
|
||||
#ifdef CONFIG_SPL
|
||||
# define CONFIG_SPL_MMC_SUPPORT
|
||||
# include "imx6_spl.h"
|
||||
# ifdef CONFIG_SPL_BUILD
|
||||
# undef CONFIG_DM_GPIO
|
||||
# undef CONFIG_DM_MMC
|
||||
# endif
|
||||
#endif
|
||||
|
||||
#endif /* __IMX6QLD_ICORE_RQS_CONFIG_H */
|
||||
@ -1,194 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2016 Amarula Solutions B.V.
|
||||
* Copyright (C) 2016 Engicam S.r.l.
|
||||
*
|
||||
* Configuration settings for the Engicam GEAM6UL Starter Kits.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __IMX6UL_GEAM_CONFIG_H
|
||||
#define __IMX6UL_GEAM_CONFIG_H
|
||||
|
||||
#include <linux/sizes.h>
|
||||
#include "mx6_common.h"
|
||||
|
||||
/* Size of malloc() pool */
|
||||
#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M)
|
||||
|
||||
/* Total Size of Environment Sector */
|
||||
#define CONFIG_ENV_SIZE SZ_128K
|
||||
|
||||
/* Allow to overwrite serial and ethaddr */
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
|
||||
/* Environment */
|
||||
#ifndef CONFIG_ENV_IS_NOWHERE
|
||||
/* Environment in MMC */
|
||||
# if defined(CONFIG_ENV_IS_IN_MMC)
|
||||
# define CONFIG_ENV_OFFSET 0x100000
|
||||
/* Environment in NAND */
|
||||
# elif defined(CONFIG_ENV_IS_IN_NAND)
|
||||
# define CONFIG_ENV_OFFSET 0x400000
|
||||
# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
|
||||
# endif
|
||||
#endif
|
||||
|
||||
/* Default environment */
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"script=boot.scr\0" \
|
||||
"image=uImage\0" \
|
||||
"fit_image=fit.itb\0" \
|
||||
"console=ttymxc0\0" \
|
||||
"fdt_high=0xffffffff\0" \
|
||||
"fdt_addr=0x87800000\0" \
|
||||
"boot_fdt=try\0" \
|
||||
"mmcpart=1\0" \
|
||||
"nandroot=ubi0:rootfs rootfstype=ubifs\0" \
|
||||
"mmcautodetect=yes\0" \
|
||||
"mmcargs=setenv bootargs console=${console},${baudrate} " \
|
||||
"root=${mmcroot}\0" \
|
||||
"ubiargs=setenv bootargs console=${console},${baudrate} " \
|
||||
"ubi.mtd=5 root=${nandroot} ${mtdparts}\0" \
|
||||
"loadbootscript=" \
|
||||
"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
|
||||
"bootscript=echo Running bootscript from mmc ...; " \
|
||||
"source\0" \
|
||||
"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
|
||||
"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
|
||||
"loadfit=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${fit_image}\0" \
|
||||
"fitboot=echo Booting FIT image from mmc ...; " \
|
||||
"run mmcargs; " \
|
||||
"bootm ${loadaddr}\0" \
|
||||
"_mmcboot=run mmcargs; " \
|
||||
"run mmcargs; " \
|
||||
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
|
||||
"if run loadfdt; then " \
|
||||
"bootm ${loadaddr} - ${fdt_addr}; " \
|
||||
"else " \
|
||||
"if test ${boot_fdt} = try; then " \
|
||||
"bootm; " \
|
||||
"else " \
|
||||
"echo WARN: Cannot load the DT; " \
|
||||
"fi; " \
|
||||
"fi; " \
|
||||
"else " \
|
||||
"bootm; " \
|
||||
"fi\0" \
|
||||
"mmcboot=echo Booting from mmc ...; " \
|
||||
"if mmc rescan; then " \
|
||||
"if run loadbootscript; then " \
|
||||
"run bootscript; " \
|
||||
"else " \
|
||||
"if run loadfit; then " \
|
||||
"run fitboot; " \
|
||||
"else " \
|
||||
"if run loadimage; then " \
|
||||
"run _mmcboot; " \
|
||||
"fi; " \
|
||||
"fi; " \
|
||||
"fi; " \
|
||||
"fi\0" \
|
||||
"nandboot=echo Booting from nand ...; " \
|
||||
"if mtdparts; then " \
|
||||
"echo Starting nand boot ...; " \
|
||||
"else " \
|
||||
"mtdparts default; " \
|
||||
"fi; " \
|
||||
"run ubiargs; " \
|
||||
"nand read ${loadaddr} kernel 0x800000; " \
|
||||
"nand read ${fdt_addr} dtb 0x100000; " \
|
||||
"bootm ${loadaddr} - ${fdt_addr}\0"
|
||||
|
||||
#define CONFIG_BOOTCOMMAND "run $modeboot"
|
||||
|
||||
/* Miscellaneous configurable options */
|
||||
#define CONFIG_SYS_MEMTEST_START 0x80000000
|
||||
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x8000000)
|
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
|
||||
#define CONFIG_SYS_HZ 1000
|
||||
|
||||
/* Physical Memory Map */
|
||||
#define CONFIG_NR_DRAM_BANKS 1
|
||||
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
|
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
|
||||
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
|
||||
GENERATED_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
|
||||
CONFIG_SYS_INIT_SP_OFFSET)
|
||||
|
||||
/* FIT */
|
||||
#ifdef CONFIG_FIT
|
||||
# define CONFIG_IMAGE_FORMAT_LEGACY
|
||||
#endif
|
||||
|
||||
/* UART */
|
||||
#ifdef CONFIG_MXC_UART
|
||||
# define CONFIG_MXC_UART_BASE UART1_BASE
|
||||
#endif
|
||||
|
||||
/* MMC */
|
||||
#ifdef CONFIG_FSL_USDHC
|
||||
# define CONFIG_SYS_MMC_ENV_DEV 0
|
||||
# define CONFIG_SYS_FSL_USDHC_NUM 1
|
||||
# define CONFIG_SYS_FSL_ESDHC_ADDR 0
|
||||
#endif
|
||||
|
||||
/* NAND */
|
||||
#ifdef CONFIG_NAND_MXS
|
||||
# define CONFIG_SYS_MAX_NAND_DEVICE 1
|
||||
# define CONFIG_SYS_NAND_BASE 0x40000000
|
||||
# define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
# define CONFIG_SYS_NAND_ONFI_DETECTION
|
||||
# define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
|
||||
# define CONFIG_SYS_NAND_U_BOOT_OFFS 0x200000
|
||||
|
||||
/* MTD device */
|
||||
# define CONFIG_MTD_DEVICE
|
||||
# define CONFIG_CMD_MTDPARTS
|
||||
# define CONFIG_MTD_PARTITIONS
|
||||
# define MTDIDS_DEFAULT "nand0=gpmi-nand"
|
||||
# define MTDPARTS_DEFAULT "mtdparts=gpmi-nand:2m(spl),2m(uboot)," \
|
||||
"1m(env),8m(kernel),1m(dtb),-(rootfs)"
|
||||
|
||||
/* UBI */
|
||||
# define CONFIG_CMD_UBIFS
|
||||
# define CONFIG_RBTREE
|
||||
# define CONFIG_LZO
|
||||
|
||||
# define CONFIG_APBH_DMA
|
||||
# define CONFIG_APBH_DMA_BURST
|
||||
# define CONFIG_APBH_DMA_BURST8
|
||||
#endif
|
||||
|
||||
/* Ethernet */
|
||||
#ifdef CONFIG_FEC_MXC
|
||||
# define CONFIG_FEC_MXC_PHYADDR 0
|
||||
# define CONFIG_FEC_XCV_TYPE RMII
|
||||
|
||||
# define CONFIG_MII
|
||||
# define CONFIG_PHYLIB
|
||||
# define CONFIG_PHY_SMSC
|
||||
#endif
|
||||
|
||||
/* SPL */
|
||||
#ifdef CONFIG_SPL
|
||||
# ifdef CONFIG_NAND_MXS
|
||||
# define CONFIG_SPL_NAND_SUPPORT
|
||||
# else
|
||||
# define CONFIG_SPL_MMC_SUPPORT
|
||||
# endif
|
||||
|
||||
# include "imx6_spl.h"
|
||||
# ifdef CONFIG_SPL_BUILD
|
||||
# undef CONFIG_DM_GPIO
|
||||
# undef CONFIG_DM_MMC
|
||||
# endif
|
||||
#endif
|
||||
|
||||
#endif /* __IMX6UL_GEAM_CONFIG_H */
|
||||
@ -1,195 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2016 Amarula Solutions B.V.
|
||||
* Copyright (C) 2016 Engicam S.r.l.
|
||||
*
|
||||
* Configuration settings for the Engicam Is.IoT MX6UL Starter Kits.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __IMX6UL_ISIOT_CONFIG_H
|
||||
#define __IMX6UL_ISIOT_CONFIG_H
|
||||
|
||||
#include <linux/sizes.h>
|
||||
#include "mx6_common.h"
|
||||
|
||||
/* Size of malloc() pool */
|
||||
#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M)
|
||||
|
||||
/* Total Size of Environment Sector */
|
||||
#define CONFIG_ENV_SIZE SZ_128K
|
||||
|
||||
/* Allow to overwrite serial and ethaddr */
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
|
||||
/* Environment */
|
||||
#ifndef CONFIG_ENV_IS_NOWHERE
|
||||
/* Environment in MMC */
|
||||
# if defined(CONFIG_ENV_IS_IN_MMC)
|
||||
# define CONFIG_ENV_OFFSET 0x100000
|
||||
/* Environment in NAND */
|
||||
# elif defined(CONFIG_ENV_IS_IN_NAND)
|
||||
# define CONFIG_ENV_OFFSET 0x400000
|
||||
# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
|
||||
# endif
|
||||
#endif
|
||||
|
||||
/* Default environment */
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"script=boot.scr\0" \
|
||||
"image=uImage\0" \
|
||||
"fit_image=fit.itb\0" \
|
||||
"splashpos=m,m\0" \
|
||||
"console=ttymxc0\0" \
|
||||
"fdt_high=0xffffffff\0" \
|
||||
"fdt_addr=0x87800000\0" \
|
||||
"boot_fdt=try\0" \
|
||||
"mmcpart=1\0" \
|
||||
"nandroot=ubi0:rootfs rootfstype=ubifs\0" \
|
||||
"mmcautodetect=yes\0" \
|
||||
"mmcargs=setenv bootargs console=${console},${baudrate} " \
|
||||
"root=${mmcroot}\0" \
|
||||
"ubiargs=setenv bootargs console=${console},${baudrate} " \
|
||||
"ubi.mtd=5 root=${nandroot} ${mtdparts}\0" \
|
||||
"loadbootscript=" \
|
||||
"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
|
||||
"bootscript=echo Running bootscript from mmc ...; " \
|
||||
"source\0" \
|
||||
"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
|
||||
"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
|
||||
"loadfit=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${fit_image}\0" \
|
||||
"fitboot=echo Booting FIT image from mmc ...; " \
|
||||
"run mmcargs; " \
|
||||
"bootm ${loadaddr}\0" \
|
||||
"_mmcboot=run mmcargs; " \
|
||||
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
|
||||
"if run loadfdt; then " \
|
||||
"bootm ${loadaddr} - ${fdt_addr}; " \
|
||||
"else " \
|
||||
"if test ${boot_fdt} = try; then " \
|
||||
"bootm; " \
|
||||
"else " \
|
||||
"echo WARN: Cannot load the DT; " \
|
||||
"fi; " \
|
||||
"fi; " \
|
||||
"else " \
|
||||
"bootm; " \
|
||||
"fi\0" \
|
||||
"mmcboot=echo Booting from mmc ...; " \
|
||||
"if mmc rescan; then " \
|
||||
"if run loadbootscript; then " \
|
||||
"run bootscript; " \
|
||||
"else " \
|
||||
"if run loadfit; then " \
|
||||
"run fitboot; " \
|
||||
"else " \
|
||||
"if run loadimage; then " \
|
||||
"run _mmcboot; " \
|
||||
"fi; " \
|
||||
"fi; " \
|
||||
"fi; " \
|
||||
"fi\0" \
|
||||
"nandboot=echo Booting from nand ...; " \
|
||||
"if mtdparts; then " \
|
||||
"echo Starting nand boot ...; " \
|
||||
"else " \
|
||||
"mtdparts default; " \
|
||||
"fi; " \
|
||||
"run ubiargs; " \
|
||||
"nand read ${loadaddr} kernel 0x800000; " \
|
||||
"nand read ${fdt_addr} dtb 0x100000; " \
|
||||
"bootm ${loadaddr} - ${fdt_addr}\0"
|
||||
|
||||
#define CONFIG_BOOTCOMMAND "run $modeboot"
|
||||
|
||||
/* Miscellaneous configurable options */
|
||||
#define CONFIG_SYS_MEMTEST_START 0x80000000
|
||||
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x8000000)
|
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
|
||||
#define CONFIG_SYS_HZ 1000
|
||||
|
||||
/* Physical Memory Map */
|
||||
#define CONFIG_NR_DRAM_BANKS 1
|
||||
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
|
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
|
||||
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
|
||||
GENERATED_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
|
||||
CONFIG_SYS_INIT_SP_OFFSET)
|
||||
|
||||
/* FIT */
|
||||
#ifdef CONFIG_FIT
|
||||
# define CONFIG_IMAGE_FORMAT_LEGACY
|
||||
#endif
|
||||
|
||||
/* UART */
|
||||
#ifdef CONFIG_MXC_UART
|
||||
# define CONFIG_MXC_UART_BASE UART1_BASE
|
||||
#endif
|
||||
|
||||
/* MMC */
|
||||
#ifdef CONFIG_FSL_USDHC
|
||||
# define CONFIG_SYS_MMC_ENV_DEV 0
|
||||
# define CONFIG_SYS_FSL_USDHC_NUM 2
|
||||
# define CONFIG_SYS_FSL_ESDHC_ADDR 0
|
||||
#endif
|
||||
|
||||
/* NAND */
|
||||
#ifdef CONFIG_NAND_MXS
|
||||
# define CONFIG_SYS_MAX_NAND_DEVICE 1
|
||||
# define CONFIG_SYS_NAND_BASE 0x40000000
|
||||
# define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
# define CONFIG_SYS_NAND_ONFI_DETECTION
|
||||
# define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
|
||||
# define CONFIG_SYS_NAND_U_BOOT_OFFS 0x200000
|
||||
|
||||
/* MTD device */
|
||||
# define CONFIG_MTD_DEVICE
|
||||
# define CONFIG_CMD_MTDPARTS
|
||||
# define CONFIG_MTD_PARTITIONS
|
||||
# define MTDIDS_DEFAULT "nand0=gpmi-nand"
|
||||
# define MTDPARTS_DEFAULT "mtdparts=gpmi-nand:2m(spl),2m(uboot)," \
|
||||
"1m(env),8m(kernel),1m(dtb),-(rootfs)"
|
||||
|
||||
/* UBI */
|
||||
# define CONFIG_CMD_UBIFS
|
||||
# define CONFIG_RBTREE
|
||||
# define CONFIG_LZO
|
||||
|
||||
/* APBH DMA */
|
||||
# define CONFIG_APBH_DMA
|
||||
# define CONFIG_APBH_DMA_BURST
|
||||
# define CONFIG_APBH_DMA_BURST8
|
||||
#endif
|
||||
|
||||
/* Ethernet */
|
||||
#ifdef CONFIG_FEC_MXC
|
||||
# define CONFIG_FEC_MXC_PHYADDR 0
|
||||
# define CONFIG_FEC_XCV_TYPE RMII
|
||||
|
||||
# define CONFIG_MII
|
||||
# define CONFIG_PHYLIB
|
||||
# define CONFIG_PHY_SMSC
|
||||
#endif
|
||||
|
||||
/* SPL */
|
||||
#ifdef CONFIG_SPL
|
||||
# ifdef CONFIG_NAND_MXS
|
||||
# define CONFIG_SPL_NAND_SUPPORT
|
||||
# else
|
||||
# define CONFIG_SPL_MMC_SUPPORT
|
||||
# endif
|
||||
|
||||
# include "imx6_spl.h"
|
||||
# ifdef CONFIG_SPL_BUILD
|
||||
# undef CONFIG_DM_GPIO
|
||||
# undef CONFIG_DM_MMC
|
||||
# endif
|
||||
#endif
|
||||
|
||||
#endif /* __IMX6UL_ISIOT_CONFIG_H */
|
||||
@ -207,7 +207,7 @@
|
||||
#define CONFIG_APBH_DMA_BURST8
|
||||
#endif
|
||||
|
||||
#define CONFIG_ENV_OFFSET (8 * SZ_64K)
|
||||
#define CONFIG_ENV_OFFSET (12 * SZ_64K)
|
||||
#ifdef CONFIG_NAND_MXS
|
||||
#define CONFIG_SYS_FSL_USDHC_NUM 1
|
||||
#else
|
||||
|
||||
143
include/configs/pico-imx7d.h
Normal file
143
include/configs/pico-imx7d.h
Normal file
@ -0,0 +1,143 @@
|
||||
/*
|
||||
* Copyright (C) 2017 NXP Semiconductors
|
||||
*
|
||||
* Configuration settings for the i.MX7D Pico board.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __PICO_IMX7D_CONFIG_H
|
||||
#define __PICO_IMX7D_CONFIG_H
|
||||
|
||||
#include "mx7_common.h"
|
||||
|
||||
#define PHYS_SDRAM_SIZE SZ_1G
|
||||
|
||||
/* Size of malloc() pool */
|
||||
#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M)
|
||||
|
||||
#define CONFIG_MXC_UART_BASE UART5_IPS_BASE_ADDR
|
||||
|
||||
/* Network */
|
||||
#define CONFIG_FEC_MXC
|
||||
#define CONFIG_MII
|
||||
#define CONFIG_FEC_XCV_TYPE RGMII
|
||||
#define CONFIG_ETHPRIME "FEC"
|
||||
#define CONFIG_FEC_MXC_PHYADDR 1
|
||||
|
||||
#define CONFIG_PHYLIB
|
||||
#define CONFIG_PHY_ATHEROS
|
||||
|
||||
/* ENET1 */
|
||||
#define IMX_FEC_BASE ENET_IPS_BASE_ADDR
|
||||
|
||||
/* MMC Config */
|
||||
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
|
||||
|
||||
#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
|
||||
#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"script=boot.scr\0" \
|
||||
"image=zImage\0" \
|
||||
"console=ttymxc4\0" \
|
||||
"fdt_high=0xffffffff\0" \
|
||||
"initrd_high=0xffffffff\0" \
|
||||
"fdt_file=imx7d-pico.dtb\0" \
|
||||
"fdt_addr=0x83000000\0" \
|
||||
"ip_dyn=yes\0" \
|
||||
"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
|
||||
"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
|
||||
"finduuid=part uuid mmc 0:2 uuid\0" \
|
||||
"mmcargs=setenv bootargs console=${console},${baudrate} " \
|
||||
"root=PARTUUID=${uuid} rootwait rw\0" \
|
||||
"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
|
||||
"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
|
||||
"mmcboot=echo Booting from mmc ...; " \
|
||||
"run finduuid; " \
|
||||
"run mmcargs; " \
|
||||
"if run loadfdt; then " \
|
||||
"bootz ${loadaddr} - ${fdt_addr}; " \
|
||||
"else " \
|
||||
"echo WARN: Cannot load the DT; " \
|
||||
"fi;\0" \
|
||||
"netargs=setenv bootargs console=${console},${baudrate} " \
|
||||
"root=/dev/nfs " \
|
||||
"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
|
||||
"netboot=echo Booting from net ...; " \
|
||||
"run netargs; " \
|
||||
"if test ${ip_dyn} = yes; then " \
|
||||
"setenv get_cmd dhcp; " \
|
||||
"else " \
|
||||
"setenv get_cmd tftp; " \
|
||||
"fi; " \
|
||||
"${get_cmd} ${image}; " \
|
||||
"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
|
||||
"bootz ${loadaddr} - ${fdt_addr}; " \
|
||||
"else " \
|
||||
"echo WARN: Cannot load the DT; " \
|
||||
"fi;\0"
|
||||
|
||||
#define CONFIG_BOOTCOMMAND \
|
||||
"if mmc rescan; then " \
|
||||
"if run loadimage; then " \
|
||||
"run mmcboot; " \
|
||||
"else run netboot; " \
|
||||
"fi; " \
|
||||
"else run netboot; fi"
|
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x80000000
|
||||
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x20000000)
|
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
|
||||
#define CONFIG_SYS_HZ 1000
|
||||
|
||||
/* Physical Memory Map */
|
||||
#define CONFIG_NR_DRAM_BANKS 1
|
||||
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
|
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
|
||||
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET \
|
||||
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_ADDR \
|
||||
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
|
||||
|
||||
/* I2C configs */
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_MXC
|
||||
#define CONFIG_SYS_I2C_MXC_I2C1
|
||||
#define CONFIG_SYS_I2C_MXC_I2C2
|
||||
#define CONFIG_SYS_I2C_MXC_I2C3
|
||||
#define CONFIG_SYS_I2C_MXC_I2C4
|
||||
#define CONFIG_SYS_I2C_SPEED 100000
|
||||
|
||||
/* PMIC */
|
||||
#define CONFIG_POWER
|
||||
#define CONFIG_POWER_I2C
|
||||
#define CONFIG_POWER_PFUZE3000
|
||||
#define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08
|
||||
|
||||
/* FLASH and environment organization */
|
||||
#define CONFIG_ENV_SIZE SZ_8K
|
||||
#define CONFIG_ENV_IS_IN_MMC
|
||||
|
||||
#define CONFIG_ENV_OFFSET (8 * SZ_64K)
|
||||
#define CONFIG_SYS_FSL_USDHC_NUM 2
|
||||
|
||||
#define CONFIG_SYS_MMC_ENV_DEV 0
|
||||
#define CONFIG_SYS_MMC_ENV_PART 0
|
||||
|
||||
/* USB Configs */
|
||||
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
|
||||
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
|
||||
#define CONFIG_MXC_USB_FLAGS 0
|
||||
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
|
||||
|
||||
#define CONFIG_IMX_THERMAL
|
||||
|
||||
#define CONFIG_USB_FUNCTION_MASS_STORAGE
|
||||
|
||||
#endif
|
||||
@ -754,6 +754,10 @@ int pci_last_busno(void);
|
||||
extern void pci_mpc85xx_init (struct pci_controller *hose);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PCIE_IMX
|
||||
extern void imx_pcie_remove(void);
|
||||
#endif
|
||||
|
||||
#if !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT)
|
||||
/**
|
||||
* pci_write_bar32() - Write the address of a BAR including control bits
|
||||
|
||||
@ -2498,7 +2498,6 @@ CONFIG_SPL_NAND_ECC
|
||||
CONFIG_SPL_NAND_INIT
|
||||
CONFIG_SPL_NAND_LOAD
|
||||
CONFIG_SPL_NAND_MINIMAL
|
||||
CONFIG_SPL_NAND_MXS
|
||||
CONFIG_SPL_NAND_RAW_ONLY
|
||||
CONFIG_SPL_NAND_SIMPLE
|
||||
CONFIG_SPL_NAND_SOFTECC
|
||||
|
||||
Loading…
Reference in New Issue
Block a user