spi: stm32: Add ofdata_to_platdata() callback
Parse DT in ofdata_to_platdata() callback instead of probe(). Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
This commit is contained in:
Patrice Chotard
parent
b0e763b7b8
commit
81b2445af4
@ -97,11 +97,14 @@
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#define SPI_SIMPLEX_RX 2
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#define SPI_HALF_DUPLEX 3
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struct stm32_spi_priv {
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struct stm32_spi_plat {
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void __iomem *base;
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struct clk clk;
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struct reset_ctl rst_ctl;
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struct gpio_desc cs_gpios[MAX_CS_COUNT];
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};
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struct stm32_spi_priv {
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ulong bus_clk_rate;
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unsigned int fifo_size;
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unsigned int cur_bpw;
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@ -115,28 +118,32 @@ struct stm32_spi_priv {
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bool cs_high;
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};
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static void stm32_spi_write_txfifo(struct stm32_spi_priv *priv)
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static void stm32_spi_write_txfifo(struct udevice *bus)
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{
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struct stm32_spi_priv *priv = dev_get_priv(bus);
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struct stm32_spi_plat *plat = dev_get_plat(bus);
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void __iomem *base = plat->base;
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while ((priv->tx_len > 0) &&
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(readl(priv->base + STM32_SPI_SR) & SPI_SR_TXP)) {
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(readl(base + STM32_SPI_SR) & SPI_SR_TXP)) {
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u32 offs = priv->cur_xferlen - priv->tx_len;
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if (priv->tx_len >= sizeof(u32) &&
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IS_ALIGNED((uintptr_t)(priv->tx_buf + offs), sizeof(u32))) {
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const u32 *tx_buf32 = (const u32 *)(priv->tx_buf + offs);
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writel(*tx_buf32, priv->base + STM32_SPI_TXDR);
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writel(*tx_buf32, base + STM32_SPI_TXDR);
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priv->tx_len -= sizeof(u32);
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} else if (priv->tx_len >= sizeof(u16) &&
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IS_ALIGNED((uintptr_t)(priv->tx_buf + offs), sizeof(u16))) {
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const u16 *tx_buf16 = (const u16 *)(priv->tx_buf + offs);
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writew(*tx_buf16, priv->base + STM32_SPI_TXDR);
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writew(*tx_buf16, base + STM32_SPI_TXDR);
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priv->tx_len -= sizeof(u16);
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} else {
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const u8 *tx_buf8 = (const u8 *)(priv->tx_buf + offs);
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writeb(*tx_buf8, priv->base + STM32_SPI_TXDR);
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writeb(*tx_buf8, base + STM32_SPI_TXDR);
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priv->tx_len -= sizeof(u8);
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}
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}
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@ -144,9 +151,12 @@ static void stm32_spi_write_txfifo(struct stm32_spi_priv *priv)
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log_debug("%d bytes left\n", priv->tx_len);
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}
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static void stm32_spi_read_rxfifo(struct stm32_spi_priv *priv)
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static void stm32_spi_read_rxfifo(struct udevice *bus)
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{
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u32 sr = readl(priv->base + STM32_SPI_SR);
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struct stm32_spi_priv *priv = dev_get_priv(bus);
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struct stm32_spi_plat *plat = dev_get_plat(bus);
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void __iomem *base = plat->base;
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u32 sr = readl(base + STM32_SPI_SR);
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u32 rxplvl = (sr & SPI_SR_RXPLVL) >> SPI_SR_RXPLVL_SHIFT;
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while ((priv->rx_len > 0) &&
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@ -158,7 +168,7 @@ static void stm32_spi_read_rxfifo(struct stm32_spi_priv *priv)
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(priv->rx_len >= sizeof(u32) || (sr & SPI_SR_RXWNE))) {
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u32 *rx_buf32 = (u32 *)(priv->rx_buf + offs);
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*rx_buf32 = readl(priv->base + STM32_SPI_RXDR);
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*rx_buf32 = readl(base + STM32_SPI_RXDR);
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priv->rx_len -= sizeof(u32);
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} else if (IS_ALIGNED((uintptr_t)(priv->rx_buf + offs), sizeof(u16)) &&
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(priv->rx_len >= sizeof(u16) ||
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@ -166,38 +176,38 @@ static void stm32_spi_read_rxfifo(struct stm32_spi_priv *priv)
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(rxplvl >= 2 || priv->cur_bpw > 8)))) {
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u16 *rx_buf16 = (u16 *)(priv->rx_buf + offs);
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*rx_buf16 = readw(priv->base + STM32_SPI_RXDR);
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*rx_buf16 = readw(base + STM32_SPI_RXDR);
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priv->rx_len -= sizeof(u16);
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} else {
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u8 *rx_buf8 = (u8 *)(priv->rx_buf + offs);
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*rx_buf8 = readb(priv->base + STM32_SPI_RXDR);
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*rx_buf8 = readb(base + STM32_SPI_RXDR);
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priv->rx_len -= sizeof(u8);
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}
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sr = readl(priv->base + STM32_SPI_SR);
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sr = readl(base + STM32_SPI_SR);
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rxplvl = (sr & SPI_SR_RXPLVL) >> SPI_SR_RXPLVL_SHIFT;
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}
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log_debug("%d bytes left\n", priv->rx_len);
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}
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static int stm32_spi_enable(struct stm32_spi_priv *priv)
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static int stm32_spi_enable(void __iomem *base)
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{
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log_debug("\n");
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/* Enable the SPI hardware */
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setbits_le32(priv->base + STM32_SPI_CR1, SPI_CR1_SPE);
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setbits_le32(base + STM32_SPI_CR1, SPI_CR1_SPE);
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return 0;
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}
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static int stm32_spi_disable(struct stm32_spi_priv *priv)
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static int stm32_spi_disable(void __iomem *base)
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{
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log_debug("\n");
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/* Disable the SPI hardware */
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clrbits_le32(priv->base + STM32_SPI_CR1, SPI_CR1_SPE);
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clrbits_le32(base + STM32_SPI_CR1, SPI_CR1_SPE);
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return 0;
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}
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@ -205,45 +215,48 @@ static int stm32_spi_disable(struct stm32_spi_priv *priv)
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static int stm32_spi_claim_bus(struct udevice *slave)
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{
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struct udevice *bus = dev_get_parent(slave);
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struct stm32_spi_priv *priv = dev_get_priv(bus);
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struct stm32_spi_plat *plat = dev_get_plat(bus);
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void __iomem *base = plat->base;
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dev_dbg(slave, "\n");
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/* Enable the SPI hardware */
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return stm32_spi_enable(priv);
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return stm32_spi_enable(base);
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}
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static int stm32_spi_release_bus(struct udevice *slave)
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{
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struct udevice *bus = dev_get_parent(slave);
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struct stm32_spi_priv *priv = dev_get_priv(bus);
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struct stm32_spi_plat *plat = dev_get_plat(bus);
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void __iomem *base = plat->base;
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dev_dbg(slave, "\n");
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/* Disable the SPI hardware */
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return stm32_spi_disable(priv);
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return stm32_spi_disable(base);
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}
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static void stm32_spi_stopxfer(struct udevice *dev)
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{
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struct stm32_spi_priv *priv = dev_get_priv(dev);
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struct stm32_spi_plat *plat = dev_get_plat(dev);
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void __iomem *base = plat->base;
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u32 cr1, sr;
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int ret;
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dev_dbg(dev, "\n");
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cr1 = readl(priv->base + STM32_SPI_CR1);
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cr1 = readl(base + STM32_SPI_CR1);
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if (!(cr1 & SPI_CR1_SPE))
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return;
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/* Wait on EOT or suspend the flow */
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ret = readl_poll_timeout(priv->base + STM32_SPI_SR, sr,
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ret = readl_poll_timeout(base + STM32_SPI_SR, sr,
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!(sr & SPI_SR_EOT), 100000);
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if (ret < 0) {
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if (cr1 & SPI_CR1_CSTART) {
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writel(cr1 | SPI_CR1_CSUSP, priv->base + STM32_SPI_CR1);
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if (readl_poll_timeout(priv->base + STM32_SPI_SR,
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writel(cr1 | SPI_CR1_CSUSP, base + STM32_SPI_CR1);
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if (readl_poll_timeout(base + STM32_SPI_SR,
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sr, !(sr & SPI_SR_SUSP),
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100000) < 0)
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dev_err(dev, "Suspend request timeout\n");
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@ -251,11 +264,12 @@ static void stm32_spi_stopxfer(struct udevice *dev)
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}
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/* clear status flags */
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setbits_le32(priv->base + STM32_SPI_IFCR, SPI_IFCR_ALL);
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setbits_le32(base + STM32_SPI_IFCR, SPI_IFCR_ALL);
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}
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static int stm32_spi_set_cs(struct udevice *dev, unsigned int cs, bool enable)
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{
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struct stm32_spi_plat *plat = dev_get_plat(dev);
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struct stm32_spi_priv *priv = dev_get_priv(dev);
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dev_dbg(dev, "cs=%d enable=%d\n", cs, enable);
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@ -263,18 +277,20 @@ static int stm32_spi_set_cs(struct udevice *dev, unsigned int cs, bool enable)
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if (cs >= MAX_CS_COUNT)
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return -ENODEV;
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if (!dm_gpio_is_valid(&priv->cs_gpios[cs]))
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if (!dm_gpio_is_valid(&plat->cs_gpios[cs]))
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return -EINVAL;
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if (priv->cs_high)
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enable = !enable;
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return dm_gpio_set_value(&priv->cs_gpios[cs], enable ? 1 : 0);
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return dm_gpio_set_value(&plat->cs_gpios[cs], enable ? 1 : 0);
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}
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static int stm32_spi_set_mode(struct udevice *bus, uint mode)
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{
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struct stm32_spi_priv *priv = dev_get_priv(bus);
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struct stm32_spi_plat *plat = dev_get_plat(bus);
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void __iomem *base = plat->base;
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u32 cfg2_clrb = 0, cfg2_setb = 0;
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dev_dbg(bus, "mode=%d\n", mode);
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@ -295,7 +311,7 @@ static int stm32_spi_set_mode(struct udevice *bus, uint mode)
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cfg2_clrb |= SPI_CFG2_LSBFRST;
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if (cfg2_clrb || cfg2_setb)
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clrsetbits_le32(priv->base + STM32_SPI_CFG2,
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clrsetbits_le32(base + STM32_SPI_CFG2,
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cfg2_clrb, cfg2_setb);
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if (mode & SPI_CS_HIGH)
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@ -308,6 +324,8 @@ static int stm32_spi_set_mode(struct udevice *bus, uint mode)
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static int stm32_spi_set_fthlv(struct udevice *dev, u32 xfer_len)
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{
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struct stm32_spi_priv *priv = dev_get_priv(dev);
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struct stm32_spi_plat *plat = dev_get_plat(dev);
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void __iomem *base = plat->base;
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u32 fthlv, half_fifo;
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/* data packet should not exceed 1/2 of fifo space */
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@ -321,7 +339,7 @@ static int stm32_spi_set_fthlv(struct udevice *dev, u32 xfer_len)
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if (!fthlv)
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fthlv = 1;
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clrsetbits_le32(priv->base + STM32_SPI_CFG1, SPI_CFG1_FTHLV,
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clrsetbits_le32(base + STM32_SPI_CFG1, SPI_CFG1_FTHLV,
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(fthlv - 1) << SPI_CFG1_FTHLV_SHIFT);
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return 0;
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@ -330,6 +348,8 @@ static int stm32_spi_set_fthlv(struct udevice *dev, u32 xfer_len)
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static int stm32_spi_set_speed(struct udevice *bus, uint hz)
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{
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struct stm32_spi_priv *priv = dev_get_priv(bus);
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struct stm32_spi_plat *plat = dev_get_plat(bus);
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void __iomem *base = plat->base;
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u32 mbrdiv;
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long div;
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@ -353,7 +373,7 @@ static int stm32_spi_set_speed(struct udevice *bus, uint hz)
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if (!mbrdiv)
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return -EINVAL;
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clrsetbits_le32(priv->base + STM32_SPI_CFG1, SPI_CFG1_MBR,
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clrsetbits_le32(base + STM32_SPI_CFG1, SPI_CFG1_MBR,
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(mbrdiv - 1) << SPI_CFG1_MBR_SHIFT);
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priv->cur_hz = hz;
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@ -367,6 +387,8 @@ static int stm32_spi_xfer(struct udevice *slave, unsigned int bitlen,
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struct udevice *bus = dev_get_parent(slave);
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struct dm_spi_slave_plat *slave_plat;
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struct stm32_spi_priv *priv = dev_get_priv(bus);
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struct stm32_spi_plat *plat = dev_get_plat(bus);
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void __iomem *base = plat->base;
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u32 sr;
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u32 ifcr = 0;
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u32 xferlen;
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@ -376,7 +398,7 @@ static int stm32_spi_xfer(struct udevice *slave, unsigned int bitlen,
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xferlen = bitlen / 8;
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if (xferlen <= SPI_CR2_TSIZE)
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writel(xferlen, priv->base + STM32_SPI_CR2);
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writel(xferlen, base + STM32_SPI_CR2);
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else
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return -EMSGSIZE;
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@ -396,15 +418,15 @@ static int stm32_spi_xfer(struct udevice *slave, unsigned int bitlen,
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priv->cur_xferlen = xferlen;
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/* Disable the SPI hardware to unlock CFG1/CFG2 registers */
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stm32_spi_disable(priv);
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stm32_spi_disable(base);
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clrsetbits_le32(priv->base + STM32_SPI_CFG2, SPI_CFG2_COMM,
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clrsetbits_le32(base + STM32_SPI_CFG2, SPI_CFG2_COMM,
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mode << SPI_CFG2_COMM_SHIFT);
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stm32_spi_set_fthlv(bus, xferlen);
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/* Enable the SPI hardware */
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stm32_spi_enable(priv);
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stm32_spi_enable(base);
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}
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dev_dbg(bus, "priv->tx_len=%d priv->rx_len=%d\n",
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@ -416,12 +438,12 @@ static int stm32_spi_xfer(struct udevice *slave, unsigned int bitlen,
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/* Be sure to have data in fifo before starting data transfer */
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if (priv->tx_buf)
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stm32_spi_write_txfifo(priv);
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stm32_spi_write_txfifo(bus);
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setbits_le32(priv->base + STM32_SPI_CR1, SPI_CR1_CSTART);
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setbits_le32(base + STM32_SPI_CR1, SPI_CR1_CSTART);
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while (1) {
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sr = readl(priv->base + STM32_SPI_SR);
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sr = readl(base + STM32_SPI_SR);
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if (sr & SPI_SR_OVR) {
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dev_err(bus, "Overrun: RX data lost\n");
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@ -433,7 +455,7 @@ static int stm32_spi_xfer(struct udevice *slave, unsigned int bitlen,
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dev_warn(bus, "System too slow is limiting data throughput\n");
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if (priv->rx_buf && priv->rx_len > 0)
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stm32_spi_read_rxfifo(priv);
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stm32_spi_read_rxfifo(bus);
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ifcr |= SPI_SR_SUSP;
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}
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@ -443,23 +465,23 @@ static int stm32_spi_xfer(struct udevice *slave, unsigned int bitlen,
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if (sr & SPI_SR_TXP)
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if (priv->tx_buf && priv->tx_len > 0)
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stm32_spi_write_txfifo(priv);
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stm32_spi_write_txfifo(bus);
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if (sr & SPI_SR_RXP)
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if (priv->rx_buf && priv->rx_len > 0)
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stm32_spi_read_rxfifo(priv);
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stm32_spi_read_rxfifo(bus);
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if (sr & SPI_SR_EOT) {
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if (priv->rx_buf && priv->rx_len > 0)
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stm32_spi_read_rxfifo(priv);
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stm32_spi_read_rxfifo(bus);
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break;
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}
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writel(ifcr, priv->base + STM32_SPI_IFCR);
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writel(ifcr, base + STM32_SPI_IFCR);
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}
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/* clear status flags */
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setbits_le32(priv->base + STM32_SPI_IFCR, SPI_IFCR_ALL);
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setbits_le32(base + STM32_SPI_IFCR, SPI_IFCR_ALL);
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stm32_spi_stopxfer(bus);
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if (flags & SPI_XFER_END)
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@ -470,42 +492,72 @@ static int stm32_spi_xfer(struct udevice *slave, unsigned int bitlen,
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static int stm32_spi_get_fifo_size(struct udevice *dev)
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{
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struct stm32_spi_priv *priv = dev_get_priv(dev);
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struct stm32_spi_plat *plat = dev_get_plat(dev);
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void __iomem *base = plat->base;
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u32 count = 0;
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stm32_spi_enable(priv);
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stm32_spi_enable(base);
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while (readl(priv->base + STM32_SPI_SR) & SPI_SR_TXP)
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writeb(++count, priv->base + STM32_SPI_TXDR);
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while (readl(base + STM32_SPI_SR) & SPI_SR_TXP)
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writeb(++count, base + STM32_SPI_TXDR);
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stm32_spi_disable(priv);
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stm32_spi_disable(base);
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dev_dbg(dev, "%d x 8-bit fifo size\n", count);
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return count;
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}
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static int stm32_spi_of_to_plat(struct udevice *dev)
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{
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struct stm32_spi_plat *plat = dev_get_plat(dev);
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int ret;
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plat->base = dev_read_addr_ptr(dev);
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if (!plat->base) {
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dev_err(dev, "can't get registers base address\n");
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return -ENOENT;
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}
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ret = clk_get_by_index(dev, 0, &plat->clk);
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if (ret < 0)
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return ret;
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||||
|
||||
ret = reset_get_by_index(dev, 0, &plat->rst_ctl);
|
||||
if (ret < 0)
|
||||
goto clk_err;
|
||||
|
||||
ret = gpio_request_list_by_name(dev, "cs-gpios", plat->cs_gpios,
|
||||
ARRAY_SIZE(plat->cs_gpios), 0);
|
||||
if (ret < 0) {
|
||||
dev_err(dev, "Can't get %s cs gpios: %d", dev->name, ret);
|
||||
ret = -ENOENT;
|
||||
goto clk_err;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
clk_err:
|
||||
clk_free(&plat->clk);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int stm32_spi_probe(struct udevice *dev)
|
||||
{
|
||||
struct stm32_spi_plat *plat = dev_get_plat(dev);
|
||||
struct stm32_spi_priv *priv = dev_get_priv(dev);
|
||||
void __iomem *base = plat->base;
|
||||
unsigned long clk_rate;
|
||||
int ret;
|
||||
unsigned int i;
|
||||
|
||||
priv->base = dev_remap_addr(dev);
|
||||
if (!priv->base)
|
||||
return -EINVAL;
|
||||
|
||||
/* enable clock */
|
||||
ret = clk_get_by_index(dev, 0, &priv->clk);
|
||||
ret = clk_enable(&plat->clk);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
ret = clk_enable(&priv->clk);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
clk_rate = clk_get_rate(&priv->clk);
|
||||
clk_rate = clk_get_rate(&plat->clk);
|
||||
if (!clk_rate) {
|
||||
ret = -EINVAL;
|
||||
goto clk_err;
|
||||
@ -514,46 +566,34 @@ static int stm32_spi_probe(struct udevice *dev)
|
||||
priv->bus_clk_rate = clk_rate;
|
||||
|
||||
/* perform reset */
|
||||
ret = reset_get_by_index(dev, 0, &priv->rst_ctl);
|
||||
if (ret < 0)
|
||||
goto clk_err;
|
||||
|
||||
reset_assert(&priv->rst_ctl);
|
||||
reset_assert(&plat->rst_ctl);
|
||||
udelay(2);
|
||||
reset_deassert(&priv->rst_ctl);
|
||||
|
||||
ret = gpio_request_list_by_name(dev, "cs-gpios", priv->cs_gpios,
|
||||
ARRAY_SIZE(priv->cs_gpios), 0);
|
||||
if (ret < 0) {
|
||||
dev_err(dev, "Can't get cs gpios: %d", ret);
|
||||
goto reset_err;
|
||||
}
|
||||
reset_deassert(&plat->rst_ctl);
|
||||
|
||||
priv->fifo_size = stm32_spi_get_fifo_size(dev);
|
||||
|
||||
priv->cur_mode = SPI_FULL_DUPLEX;
|
||||
priv->cur_xferlen = 0;
|
||||
priv->cur_bpw = SPI_DEFAULT_WORDLEN;
|
||||
clrsetbits_le32(priv->base + STM32_SPI_CFG1, SPI_CFG1_DSIZE,
|
||||
clrsetbits_le32(base + STM32_SPI_CFG1, SPI_CFG1_DSIZE,
|
||||
priv->cur_bpw - 1);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(priv->cs_gpios); i++) {
|
||||
if (!dm_gpio_is_valid(&priv->cs_gpios[i]))
|
||||
for (i = 0; i < ARRAY_SIZE(plat->cs_gpios); i++) {
|
||||
if (!dm_gpio_is_valid(&plat->cs_gpios[i]))
|
||||
continue;
|
||||
|
||||
dm_gpio_set_dir_flags(&priv->cs_gpios[i],
|
||||
dm_gpio_set_dir_flags(&plat->cs_gpios[i],
|
||||
GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
|
||||
}
|
||||
|
||||
/* Ensure I2SMOD bit is kept cleared */
|
||||
clrbits_le32(priv->base + STM32_SPI_I2SCFGR, SPI_I2SCFGR_I2SMOD);
|
||||
clrbits_le32(base + STM32_SPI_I2SCFGR, SPI_I2SCFGR_I2SMOD);
|
||||
|
||||
/*
|
||||
* - SS input value high
|
||||
* - transmitter half duplex direction
|
||||
* - automatic communication suspend when RX-Fifo is full
|
||||
*/
|
||||
setbits_le32(priv->base + STM32_SPI_CR1,
|
||||
setbits_le32(base + STM32_SPI_CR1,
|
||||
SPI_CR1_SSI | SPI_CR1_HDDIR | SPI_CR1_MASRX);
|
||||
|
||||
/*
|
||||
@ -562,40 +602,38 @@ static int stm32_spi_probe(struct udevice *dev)
|
||||
* SS input value is determined by the SSI bit
|
||||
* - keep control of all associated GPIOs
|
||||
*/
|
||||
setbits_le32(priv->base + STM32_SPI_CFG2,
|
||||
setbits_le32(base + STM32_SPI_CFG2,
|
||||
SPI_CFG2_MASTER | SPI_CFG2_SSM | SPI_CFG2_AFCNTR);
|
||||
|
||||
return 0;
|
||||
|
||||
reset_err:
|
||||
reset_free(&priv->rst_ctl);
|
||||
|
||||
clk_err:
|
||||
clk_disable(&priv->clk);
|
||||
clk_free(&priv->clk);
|
||||
clk_disable(&plat->clk);
|
||||
clk_free(&plat->clk);
|
||||
|
||||
return ret;
|
||||
};
|
||||
|
||||
static int stm32_spi_remove(struct udevice *dev)
|
||||
{
|
||||
struct stm32_spi_priv *priv = dev_get_priv(dev);
|
||||
struct stm32_spi_plat *plat = dev_get_plat(dev);
|
||||
void __iomem *base = plat->base;
|
||||
int ret;
|
||||
|
||||
stm32_spi_stopxfer(dev);
|
||||
stm32_spi_disable(priv);
|
||||
stm32_spi_disable(base);
|
||||
|
||||
ret = reset_assert(&priv->rst_ctl);
|
||||
ret = reset_assert(&plat->rst_ctl);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
reset_free(&priv->rst_ctl);
|
||||
reset_free(&plat->rst_ctl);
|
||||
|
||||
ret = clk_disable(&priv->clk);
|
||||
ret = clk_disable(&plat->clk);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
clk_free(&priv->clk);
|
||||
clk_free(&plat->clk);
|
||||
|
||||
return ret;
|
||||
};
|
||||
@ -618,7 +656,9 @@ U_BOOT_DRIVER(stm32_spi) = {
|
||||
.id = UCLASS_SPI,
|
||||
.of_match = stm32_spi_ids,
|
||||
.ops = &stm32_spi_ops,
|
||||
.priv_auto = sizeof(struct stm32_spi_priv),
|
||||
.of_to_plat = stm32_spi_of_to_plat,
|
||||
.plat_auto = sizeof(struct stm32_spi_plat),
|
||||
.priv_auto = sizeof(struct stm32_spi_priv),
|
||||
.probe = stm32_spi_probe,
|
||||
.remove = stm32_spi_remove,
|
||||
};
|
||||
|
||||
Loading…
Reference in New Issue
Block a user