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Merge branch 'master' of git://git.denx.de/u-boot-arm

Browse Source 
Bringing in the MMC tree means that CONFIG_BOUNCE_BUFFER needed to be
added to include/configs/exynos5-dt.h now.

Conflicts:
	include/configs/exynos5250-dt.h

Signed-off-by: Tom Rini <trini@ti.com>
This commit is contained in:
Tom Rini 2014-01-10 10:56:00 -05:00
commit 7f673c99c2
261 changed files with 14936 additions and 6638 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
MAKEALL
View File

@ -380,6 +380,12 @@ LIST_ARM11="$(targets_by_cpu arm1136) \
LIST_ARMV7="$(targets_by_cpu armv7)"
#########################################################################
## ARMV8 Systems
#########################################################################
LIST_ARMV8="$(targets_by_cpu armv8)"
#########################################################################
## AT91 Systems
#########################################################################
@ -404,7 +410,11 @@ LIST_spear="$(targets_by_soc spear)"
## ARM groups
#########################################################################
LIST_arm="$(targets_by_arch arm)"
LIST_arm="$(targets_by_arch arm | \
for ARMV8_TARGET in $LIST_ARMV8; \
do sed "/$ARMV8_TARGET/d"; \
done) \
"
#########################################################################
## MIPS Systems (default = big endian)

41
Makefile
View File

@ -325,6 +325,17 @@ else
BOARD_SIZE_CHECK =
endif
# Statically apply RELA-style relocations (currently arm64 only)
ifneq ($(CONFIG_STATIC_RELA),)
# $(1) is u-boot ELF, $(2) is u-boot bin, $(3) is text base
DO_STATIC_RELA = \
start=$$($(NM) $(1) | grep __rel_dyn_start | cut -f 1 -d ' '); \
end=$$($(NM) $(1) | grep __rel_dyn_end | cut -f 1 -d ' '); \
$(obj)tools/relocate-rela $(2) $(3) $$start $$end
else
DO_STATIC_RELA =
endif
# Always append ALL so that arch config.mk's can add custom ones
ALL-y += $(obj)u-boot.srec $(obj)u-boot.bin $(obj)System.map
@ -338,15 +349,18 @@ ALL-$(CONFIG_OF_SEPARATE) += $(obj)u-boot.dtb $(obj)u-boot-dtb.bin
ifneq ($(CONFIG_SPL_TARGET),)
ALL-$(CONFIG_SPL) += $(obj)$(CONFIG_SPL_TARGET:"%"=%)
endif
ALL-$(CONFIG_REMAKE_ELF) += $(obj)u-boot.elf
# enable combined SPL/u-boot/dtb rules for tegra
ifneq ($(CONFIG_TEGRA),)
ifeq ($(CONFIG_SPL),y)
ifeq ($(CONFIG_OF_SEPARATE),y)
ALL-y += $(obj)u-boot-dtb-tegra.bin
else
ALL-y += $(obj)u-boot-nodtb-tegra.bin
endif
endif
endif
build := -f $(TOPDIR)/scripts/Makefile.build -C
@ -367,6 +381,7 @@ $(obj)u-boot.srec: $(obj)u-boot
$(obj)u-boot.bin: $(obj)u-boot
$(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
$(call DO_STATIC_RELA,$<,$@,$(CONFIG_SYS_TEXT_BASE))
$(BOARD_SIZE_CHECK)
$(obj)u-boot.ldr: $(obj)u-boot
@ -501,6 +516,18 @@ $(obj)u-boot-img-spl-at-end.bin: $(obj)spl/u-boot-spl.bin $(obj)u-boot.img
--gap-fill=0xff $(obj)u-boot.img $@
cat $(obj)spl/u-boot-spl.bin >> $@
# Create a new ELF from a raw binary file. This is useful for arm64
# where static relocation needs to be performed on the raw binary,
# but certain simulators only accept an ELF file (but don't do the
# relocation).
# FIXME refactor dts/Makefile to share target/arch detection
$(obj)u-boot.elf: $(obj)u-boot.bin
@$(OBJCOPY) -B aarch64 -I binary -O elf64-littleaarch64 \
$< $(obj)u-boot-elf.o
@$(LD) $(obj)u-boot-elf.o -o $@ \
--defsym=_start=$(CONFIG_SYS_TEXT_BASE) \
-Ttext=$(CONFIG_SYS_TEXT_BASE)
ifeq ($(CONFIG_SANDBOX),y)
GEN_UBOOT = \
cd $(LNDIR) && $(CC) $(SYMS) -T $(obj)u-boot.lds \
@ -687,12 +714,16 @@ tools: $(VERSION_FILE) $(TIMESTAMP_FILE)
$(MAKE) -C $@ all
endif # config.mk
# ARM relocations should all be R_ARM_RELATIVE.
# ARM relocations should all be R_ARM_RELATIVE (32-bit) or
# R_AARCH64_RELATIVE (64-bit).
checkarmreloc: $(obj)u-boot
@if test "R_ARM_RELATIVE" != \
"`$(CROSS_COMPILE)readelf -r $< | cut -d ' ' -f 4 | grep R_ARM | sort -u`"; \
then echo "$< contains relocations other than \
R_ARM_RELATIVE"; false; fi
@RELOC="`$(CROSS_COMPILE)readelf -r -W $< | cut -d ' ' -f 4 | \
grep R_A | sort -u`"; \
if test "$$RELOC" != "R_ARM_RELATIVE" -a \
"$$RELOC" != "R_AARCH64_RELATIVE"; then \
echo "$< contains unexpected relocations: $$RELOC"; \
false; \
fi
$(VERSION_FILE):
@mkdir -p $(dir $(VERSION_FILE))

7
arch/arm/config.mk
View File

@ -17,7 +17,8 @@ endif
LDFLAGS_FINAL += --gc-sections
PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections \
-fno-common -ffixed-r9 -msoft-float
-fno-common -ffixed-r9
PLATFORM_RELFLAGS += $(call cc-option, -msoft-float)
# Support generic board on ARM
__HAVE_ARCH_GENERIC_BOARD := y
@ -105,4 +106,8 @@ PLATFORM_CPPFLAGS += $(call cc-option, -mword-relocations)
endif
# limit ourselves to the sections we want in the .bin.
ifdef CONFIG_ARM64
OBJCFLAGS += -j .text -j .rodata -j .data -j .u_boot_list -j .rela.dyn
else
OBJCFLAGS += -j .text -j .rodata -j .data -j .u_boot_list -j .rel.dyn
endif

89
arch/arm/cpu/arm720t/tegra-common/cpu.c
View File

@ -49,33 +49,68 @@ int get_num_cpus(void)
* Timing tables for each SOC for all four oscillator options.
*/
struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = {
/* T20: 1 GHz */
/* n, m, p, cpcon */
{{ 1000, 13, 0, 12}, /* OSC 13M */
{ 625, 12, 0, 8}, /* OSC 19.2M */
{ 1000, 12, 0, 12}, /* OSC 12M */
{ 1000, 26, 0, 12}, /* OSC 26M */
/*
* T20: 1 GHz
*
* Register Field Bits Width
* ------------------------------
* PLLX_BASE p 22:20 3
* PLLX_BASE n 17: 8 10
* PLLX_BASE m 4: 0 5
* PLLX_MISC cpcon 11: 8 4
*/
{
{ .n = 1000, .m = 13, .p = 0, .cpcon = 12 }, /* OSC: 13.0 MHz */
{ .n = 625, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */
{ .n = 1000, .m = 12, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */
{ .n = 1000, .m = 26, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */
},
/* T25: 1.2 GHz */
{{ 923, 10, 0, 12},
{ 750, 12, 0, 8},
{ 600, 6, 0, 12},
{ 600, 13, 0, 12},
/*
* T25: 1.2 GHz
*
* Register Field Bits Width
* ------------------------------
* PLLX_BASE p 22:20 3
* PLLX_BASE n 17: 8 10
* PLLX_BASE m 4: 0 5
* PLLX_MISC cpcon 11: 8 4
*/
{
{ .n = 923, .m = 10, .p = 0, .cpcon = 12 }, /* OSC: 13.0 MHz */
{ .n = 750, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */
{ .n = 600, .m = 6, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */
{ .n = 600, .m = 13, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */
},
/* T30: 1.4 GHz */
{{ 862, 8, 0, 8},
{ 583, 8, 0, 4},
{ 700, 6, 0, 8},
{ 700, 13, 0, 8},
/*
* T30: 1.4 GHz
*
* Register Field Bits Width
* ------------------------------
* PLLX_BASE p 22:20 3
* PLLX_BASE n 17: 8 10
* PLLX_BASE m 4: 0 5
* PLLX_MISC cpcon 11: 8 4
*/
{
{ .n = 862, .m = 8, .p = 0, .cpcon = 8 }, /* OSC: 13.0 MHz */
{ .n = 583, .m = 8, .p = 0, .cpcon = 4 }, /* OSC: 19.2 MHz */
{ .n = 700, .m = 6, .p = 0, .cpcon = 8 }, /* OSC: 12.0 MHz */
{ .n = 700, .m = 13, .p = 0, .cpcon = 8 }, /* OSC: 26.0 MHz */
},
/* T114: 1.4 GHz */
{{ 862, 8, 0, 8},
{ 583, 8, 0, 4},
{ 696, 12, 0, 8},
{ 700, 13, 0, 8},
/*
* T114: 700 MHz
*
* Register Field Bits Width
* ------------------------------
* PLLX_BASE p 23:20 4
* PLLX_BASE n 15: 8 8
* PLLX_BASE m 7: 0 8
*/
{
{ .n = 108, .m = 1, .p = 1 }, /* OSC: 13.0 MHz */
{ .n = 73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz */
{ .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz */
{ .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz */
},
};
@ -100,6 +135,7 @@ void adjust_pllp_out_freqs(void)
int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm,
u32 divp, u32 cpcon)
{
int chip = tegra_get_chip();
u32 reg;
/* If PLLX is already enabled, just return */
@ -116,7 +152,10 @@ int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm,
writel(reg, &pll->pll_base);
/* Set cpcon to PLLX_MISC */
reg = (cpcon << PLL_CPCON_SHIFT);
if (chip == CHIPID_TEGRA20 || chip == CHIPID_TEGRA30)
reg = (cpcon << PLL_CPCON_SHIFT);
else
reg = 0;
/* Set dccon to PLLX_MISC if freq > 600MHz */
if (divn > 600)

8
arch/arm/cpu/armv7/am33xx/board.c
View File

@ -241,3 +241,11 @@ void s_init(void)
sdram_init();
#endif
}
#ifndef CONFIG_SYS_DCACHE_OFF
void enable_caches(void)
{
/* Enable D-cache. I-cache is already enabled in start.S */
dcache_enable();
}
#endif /* !CONFIG_SYS_DCACHE_OFF */

12
arch/arm/cpu/armv7/am33xx/clock.c
View File

@ -101,9 +101,15 @@ void do_setup_dpll(const struct dpll_regs *dpll_regs,
static void setup_dplls(void)
{
const struct dpll_params *params;
do_setup_dpll(&dpll_core_regs, &dpll_core);
do_setup_dpll(&dpll_mpu_regs, &dpll_mpu);
do_setup_dpll(&dpll_per_regs, &dpll_per);
params = get_dpll_core_params();
do_setup_dpll(&dpll_core_regs, params);
params = get_dpll_mpu_params();
do_setup_dpll(&dpll_mpu_regs, params);
params = get_dpll_per_params();
do_setup_dpll(&dpll_per_regs, params);
writel(0x300, &cmwkup->clkdcoldodpllper);
params = get_dpll_ddr_params();

15
arch/arm/cpu/armv7/am33xx/clock_am33xx.c
View File

@ -62,6 +62,21 @@ const struct dpll_params dpll_core = {
const struct dpll_params dpll_per = {
960, OSC-1, 5, -1, -1, -1, -1};
const struct dpll_params *get_dpll_mpu_params(void)
{
return &dpll_mpu;
}
const struct dpll_params *get_dpll_core_params(void)
{
return &dpll_core;
}
const struct dpll_params *get_dpll_per_params(void)
{
return &dpll_per;
}
void setup_clocks_for_console(void)
{
clrsetbits_le32(&cmwkup->wkclkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,

12
arch/arm/cpu/armv7/am33xx/clock_am43xx.c
View File

@ -18,6 +18,7 @@
struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER;
struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP;
struct cm_dpll *const cmdpll = (struct cm_dpll *)CM_DPLL;
const struct dpll_regs dpll_mpu_regs = {
.cm_clkmode_dpll = CM_WKUP + 0x560,
@ -47,15 +48,9 @@ const struct dpll_regs dpll_ddr_regs = {
.cm_idlest_dpll = CM_WKUP + 0x5A4,
.cm_clksel_dpll = CM_WKUP + 0x5AC,
.cm_div_m2_dpll = CM_WKUP + 0x5B0,
.cm_div_m4_dpll = CM_WKUP + 0x5B8,
};
const struct dpll_params dpll_mpu = {
-1, -1, -1, -1, -1, -1, -1};
const struct dpll_params dpll_core = {
-1, -1, -1, -1, -1, -1, -1};
const struct dpll_params dpll_per = {
-1, -1, -1, -1, -1, -1, -1};
void setup_clocks_for_console(void)
{
/* Do not add any spl_debug prints in this function */
@ -107,4 +102,7 @@ void enable_basic_clocks(void)
};
do_enable_clocks(clk_domains, clk_modules_explicit_en, 1);
/* Select the Master osc clk as Timer2 clock source */
writel(0x1, &cmdpll->clktimer2clk);
}

146
arch/arm/cpu/armv7/am33xx/ddr.c
View File

@ -36,6 +36,73 @@ static struct ddr_data_regs *ddr_data_reg[2] = {
static struct ddr_cmdtctrl *ioctrl_reg = {
(struct ddr_cmdtctrl *)DDR_CONTROL_BASE_ADDR};
static inline u32 get_mr(int nr, u32 cs, u32 mr_addr)
{
u32 mr;
mr_addr |= cs << EMIF_REG_CS_SHIFT;
writel(mr_addr, &emif_reg[nr]->emif_lpddr2_mode_reg_cfg);
mr = readl(&emif_reg[nr]->emif_lpddr2_mode_reg_data);
debug("get_mr: EMIF1 cs %d mr %08x val 0x%x\n", cs, mr_addr, mr);
if (((mr & 0x0000ff00) >> 8) == (mr & 0xff) &&
((mr & 0x00ff0000) >> 16) == (mr & 0xff) &&
((mr & 0xff000000) >> 24) == (mr & 0xff))
return mr & 0xff;
else
return mr;
}
static inline void set_mr(int nr, u32 cs, u32 mr_addr, u32 mr_val)
{
mr_addr |= cs << EMIF_REG_CS_SHIFT;
writel(mr_addr, &emif_reg[nr]->emif_lpddr2_mode_reg_cfg);
writel(mr_val, &emif_reg[nr]->emif_lpddr2_mode_reg_data);
}
static void configure_mr(int nr, u32 cs)
{
u32 mr_addr;
while (get_mr(nr, cs, LPDDR2_MR0) & LPDDR2_MR0_DAI_MASK)
;
set_mr(nr, cs, LPDDR2_MR10, 0x56);
set_mr(nr, cs, LPDDR2_MR1, 0x43);
set_mr(nr, cs, LPDDR2_MR2, 0x2);
mr_addr = LPDDR2_MR2 | EMIF_REG_REFRESH_EN_MASK;
set_mr(nr, cs, mr_addr, 0x2);
}
/*
* Configure EMIF4D5 registers and MR registers
*/
void config_sdram_emif4d5(const struct emif_regs *regs, int nr)
{
writel(0x0, &emif_reg[nr]->emif_pwr_mgmt_ctrl);
writel(0x0, &emif_reg[nr]->emif_pwr_mgmt_ctrl_shdw);
writel(0x1, &emif_reg[nr]->emif_iodft_tlgc);
writel(regs->zq_config, &emif_reg[nr]->emif_zq_config);
writel(regs->temp_alert_config, &emif_reg[nr]->emif_temp_alert_config);
writel(regs->emif_rd_wr_lvl_rmp_win,
&emif_reg[nr]->emif_rd_wr_lvl_rmp_win);
writel(regs->emif_rd_wr_lvl_rmp_ctl,
&emif_reg[nr]->emif_rd_wr_lvl_rmp_ctl);
writel(regs->emif_rd_wr_lvl_ctl, &emif_reg[nr]->emif_rd_wr_lvl_ctl);
writel(regs->emif_rd_wr_exec_thresh,
&emif_reg[nr]->emif_rd_wr_exec_thresh);
writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2) {
configure_mr(nr, 0);
configure_mr(nr, 1);
}
}
/**
* Configure SDRAM
*/
@ -72,15 +139,67 @@ void set_sdram_timings(const struct emif_regs *regs, int nr)
writel(regs->sdram_tim3, &emif_reg[nr]->emif_sdram_tim_3_shdw);
}
void __weak emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size)
{
}
/*
* Configure EXT PHY registers
*/
static void ext_phy_settings(const struct emif_regs *regs, int nr)
{
u32 *ext_phy_ctrl_base = 0;
u32 *emif_ext_phy_ctrl_base = 0;
const u32 *ext_phy_ctrl_const_regs;
u32 i = 0;
u32 size;
ext_phy_ctrl_base = (u32 *)&(regs->emif_ddr_ext_phy_ctrl_1);
emif_ext_phy_ctrl_base =
(u32 *)&(emif_reg[nr]->emif_ddr_ext_phy_ctrl_1);
/* Configure external phy control timing registers */
for (i = 0; i < EMIF_EXT_PHY_CTRL_TIMING_REG; i++) {
writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++);
/* Update shadow registers */
writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++);
}
/*
* external phy 6-24 registers do not change with
* ddr frequency
*/
emif_get_ext_phy_ctrl_const_regs(&ext_phy_ctrl_const_regs, &size);
if (!size)
return;
for (i = 0; i < size; i++) {
writel(ext_phy_ctrl_const_regs[i], emif_ext_phy_ctrl_base++);
/* Update shadow registers */
writel(ext_phy_ctrl_const_regs[i], emif_ext_phy_ctrl_base++);
}
}
/**
* Configure DDR PHY
*/
void config_ddr_phy(const struct emif_regs *regs, int nr)
{
/*
* disable initialization and refreshes for now until we
* finish programming EMIF regs.
*/
setbits_le32(&emif_reg[nr]->emif_sdram_ref_ctrl,
EMIF_REG_INITREF_DIS_MASK);
writel(regs->emif_ddr_phy_ctlr_1,
&emif_reg[nr]->emif_ddr_phy_ctrl_1);
writel(regs->emif_ddr_phy_ctlr_1,
&emif_reg[nr]->emif_ddr_phy_ctrl_1_shdw);
if (get_emif_rev((u32)emif_reg[nr]) == EMIF_4D5)
ext_phy_settings(regs, nr);
}
/**
@ -88,6 +207,9 @@ void config_ddr_phy(const struct emif_regs *regs, int nr)
*/
void config_cmd_ctrl(const struct cmd_control *cmd, int nr)
{
if (!cmd)
return;
writel(cmd->cmd0csratio, &ddr_cmd_reg[nr]->cm0csratio);
writel(cmd->cmd0iclkout, &ddr_cmd_reg[nr]->cm0iclkout);
@ -105,6 +227,9 @@ void config_ddr_data(const struct ddr_data *data, int nr)
{
int i;
if (!data)
return;
for (i = 0; i < DDR_DATA_REGS_NR; i++) {
writel(data->datardsratio0,
&(ddr_data_reg[nr]+i)->dt0rdsratio0);
@ -121,11 +246,20 @@ void config_ddr_data(const struct ddr_data *data, int nr)
}
}
void config_io_ctrl(unsigned long val)
void config_io_ctrl(const struct ctrl_ioregs *ioregs)
{
writel(val, &ioctrl_reg->cm0ioctl);
writel(val, &ioctrl_reg->cm1ioctl);
writel(val, &ioctrl_reg->cm2ioctl);
writel(val, &ioctrl_reg->dt0ioctl);
writel(val, &ioctrl_reg->dt1ioctl);
if (!ioregs)
return;
writel(ioregs->cm0ioctl, &ioctrl_reg->cm0ioctl);
writel(ioregs->cm1ioctl, &ioctrl_reg->cm1ioctl);
writel(ioregs->cm2ioctl, &ioctrl_reg->cm2ioctl);
writel(ioregs->dt0ioctl, &ioctrl_reg->dt0ioctl);
writel(ioregs->dt1ioctl, &ioctrl_reg->dt1ioctl);
#ifdef CONFIG_AM43XX
writel(ioregs->dt2ioctrl, &ioctrl_reg->dt2ioctrl);
writel(ioregs->dt3ioctrl, &ioctrl_reg->dt3ioctrl);
writel(ioregs->emif_sdram_config_ext,
&ioctrl_reg->emif_sdram_config_ext);
#endif
}

25
arch/arm/cpu/armv7/am33xx/emif4.c
View File

@ -48,6 +48,11 @@ static struct vtp_reg *vtpreg[2] = {
#ifdef CONFIG_AM33XX
static struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR;
#endif
#ifdef CONFIG_AM43XX
static struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR;
static struct cm_device_inst *cm_device =
(struct cm_device_inst *)CM_DEVICE_INST;
#endif
#ifdef CONFIG_TI81XX
void config_dmm(const struct dmm_lisa_map_regs *regs)
@ -87,7 +92,7 @@ void __weak ddr_pll_config(unsigned int ddrpll_m)
{
}
void config_ddr(unsigned int pll, unsigned int ioctrl,
void config_ddr(unsigned int pll, const struct ctrl_ioregs *ioregs,
const struct ddr_data *data, const struct cmd_control *ctrl,
const struct emif_regs *regs, int nr)
{
@ -99,7 +104,18 @@ void config_ddr(unsigned int pll, unsigned int ioctrl,
config_ddr_data(data, nr);
#ifdef CONFIG_AM33XX
config_io_ctrl(ioctrl);
config_io_ctrl(ioregs);
/* Set CKE to be controlled by EMIF/DDR PHY */
writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);
#endif
#ifdef CONFIG_AM43XX
writel(readl(&cm_device->cm_dll_ctrl) & ~0x1, &cm_device->cm_dll_ctrl);
while ((readl(&cm_device->cm_dll_ctrl) && CM_DLL_READYST) == 0)
;
writel(0x0, &ddrctrl->ddrioctrl);
config_io_ctrl(ioregs);
/* Set CKE to be controlled by EMIF/DDR PHY */
writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);
@ -108,6 +124,9 @@ void config_ddr(unsigned int pll, unsigned int ioctrl,
/* Program EMIF instance */
config_ddr_phy(regs, nr);
set_sdram_timings(regs, nr);
config_sdram(regs, nr);
if (get_emif_rev(EMIF1_BASE) == EMIF_4D5)
config_sdram_emif4d5(regs, nr);
else
config_sdram(regs, nr);
}
#endif

279
arch/arm/cpu/armv7/exynos/clock.c
View File

@ -96,7 +96,7 @@ static int exynos_get_pll_clk(int pllreg, unsigned int r, unsigned int k)
freq = CONFIG_SYS_CLK_FREQ;
if (pllreg == EPLL) {
if (pllreg == EPLL || pllreg == RPLL) {
k = k & 0xffff;
/* FOUT = (MDIV + K / 65536) * FIN / (PDIV * 2^SDIV) */
fout = (m + k / PLL_DIV_65536) * (freq / (p * (1 << s)));
@ -117,7 +117,7 @@ static int exynos_get_pll_clk(int pllreg, unsigned int r, unsigned int k)
div = PLL_DIV_1024;
else if (proid_is_exynos4412())
div = PLL_DIV_65535;
else if (proid_is_exynos5250())
else if (proid_is_exynos5250() || proid_is_exynos5420())
div = PLL_DIV_65536;
else
return 0;
@ -362,6 +362,43 @@ unsigned long clock_get_periph_rate(int peripheral)
return 0;
}
/* exynos5420: return pll clock frequency */
static unsigned long exynos5420_get_pll_clk(int pllreg)
{
struct exynos5420_clock *clk =
(struct exynos5420_clock *)samsung_get_base_clock();
unsigned long r, k = 0;
switch (pllreg) {
case APLL:
r = readl(&clk->apll_con0);
break;
case MPLL:
r = readl(&clk->mpll_con0);
break;
case EPLL:
r = readl(&clk->epll_con0);
k = readl(&clk->epll_con1);
break;
case VPLL:
r = readl(&clk->vpll_con0);
k = readl(&clk->vpll_con1);
break;
case BPLL:
r = readl(&clk->bpll_con0);
break;
case RPLL:
r = readl(&clk->rpll_con0);
k = readl(&clk->rpll_con1);
break;
default:
printf("Unsupported PLL (%d)\n", pllreg);
return 0;
}
return exynos_get_pll_clk(pllreg, r, k);
}
/* exynos4: return ARM clock frequency */
static unsigned long exynos4_get_arm_clk(void)
{
@ -485,6 +522,27 @@ static unsigned long exynos4x12_get_pwm_clk(void)
return pclk;
}
/* exynos5420: return pwm clock frequency */
static unsigned long exynos5420_get_pwm_clk(void)
{
struct exynos5420_clock *clk =
(struct exynos5420_clock *)samsung_get_base_clock();
unsigned long pclk, sclk;
unsigned int ratio;
/*
* CLK_DIV_PERIC0
* PWM_RATIO [31:28]
*/
ratio = readl(&clk->div_peric0);
ratio = (ratio >> 28) & 0xf;
sclk = get_pll_clk(MPLL);
pclk = sclk / (ratio + 1);
return pclk;
}
/* exynos4: return uart clock frequency */
static unsigned long exynos4_get_uart_clk(int dev_index)
{
@ -624,6 +682,53 @@ static unsigned long exynos5_get_uart_clk(int dev_index)
return uclk;
}
/* exynos5420: return uart clock frequency */
static unsigned long exynos5420_get_uart_clk(int dev_index)
{
struct exynos5420_clock *clk =
(struct exynos5420_clock *)samsung_get_base_clock();
unsigned long uclk, sclk;
unsigned int sel;
unsigned int ratio;
/*
* CLK_SRC_PERIC0
* UART0_SEL [6:4]
* UART1_SEL [10:8]
* UART2_SEL [14:12]
* UART3_SEL [18:16]
* generalised calculation as follows
* sel = (sel >> ((dev_index * 4) + 4)) & mask;
*/
sel = readl(&clk->src_peric0);
sel = (sel >> ((dev_index * 4) + 4)) & 0x7;
if (sel == 0x3)
sclk = get_pll_clk(MPLL);
else if (sel == 0x6)
sclk = get_pll_clk(EPLL);
else if (sel == 0x7)
sclk = get_pll_clk(RPLL);
else
return 0;
/*
* CLK_DIV_PERIC0
* UART0_RATIO [11:8]
* UART1_RATIO [15:12]
* UART2_RATIO [19:16]
* UART3_RATIO [23:20]
* generalised calculation as follows
* ratio = (ratio >> ((dev_index * 4) + 8)) & mask;
*/
ratio = readl(&clk->div_peric0);
ratio = (ratio >> ((dev_index * 4) + 8)) & 0xf;
uclk = sclk / (ratio + 1);
return uclk;
}
static unsigned long exynos4_get_mmc_clk(int dev_index)
{
struct exynos4_clock *clk =
@ -718,6 +823,47 @@ static unsigned long exynos5_get_mmc_clk(int dev_index)
return uclk;
}
static unsigned long exynos5420_get_mmc_clk(int dev_index)
{
struct exynos5420_clock *clk =
(struct exynos5420_clock *)samsung_get_base_clock();
unsigned long uclk, sclk;
unsigned int sel, ratio;
/*
* CLK_SRC_FSYS
* MMC0_SEL [10:8]
* MMC1_SEL [14:12]
* MMC2_SEL [18:16]
* generalised calculation as follows
* sel = (sel >> ((dev_index * 4) + 8)) & mask
*/
sel = readl(&clk->src_fsys);
sel = (sel >> ((dev_index * 4) + 8)) & 0x7;
if (sel == 0x3)
sclk = get_pll_clk(MPLL);
else if (sel == 0x6)
sclk = get_pll_clk(EPLL);
else
return 0;
/*
* CLK_DIV_FSYS1
* MMC0_RATIO [9:0]
* MMC1_RATIO [19:10]
* MMC2_RATIO [29:20]
* generalised calculation as follows
* ratio = (ratio >> (dev_index * 10)) & mask
*/
ratio = readl(&clk->div_fsys1);
ratio = (ratio >> (dev_index * 10)) & 0x3ff;
uclk = (sclk / (ratio + 1));
return uclk;
}
/* exynos4: set the mmc clock */
static void exynos4_set_mmc_clk(int dev_index, unsigned int div)
{
@ -804,6 +950,29 @@ static void exynos5_set_mmc_clk(int dev_index, unsigned int div)
writel(val, addr);
}
/* exynos5: set the mmc clock */
static void exynos5420_set_mmc_clk(int dev_index, unsigned int div)
{
struct exynos5420_clock *clk =
(struct exynos5420_clock *)samsung_get_base_clock();
unsigned int addr;
unsigned int val, shift;
/*
* CLK_DIV_FSYS1
* MMC0_RATIO [9:0]
* MMC1_RATIO [19:10]
* MMC2_RATIO [29:20]
*/
addr = (unsigned int)&clk->div_fsys1;
shift = dev_index * 10;
val = readl(addr);
val &= ~(0x3ff << shift);
val |= (div & 0x3ff) << shift;
writel(val, addr);
}
/* get_lcd_clk: return lcd clock frequency */
static unsigned long exynos4_get_lcd_clk(void)
{
@ -1324,6 +1493,71 @@ static int exynos5_set_spi_clk(enum periph_id periph_id,
return 0;
}
static int exynos5420_set_spi_clk(enum periph_id periph_id,
unsigned int rate)
{
struct exynos5420_clock *clk =
(struct exynos5420_clock *)samsung_get_base_clock();
int main;
unsigned int fine;
unsigned shift, pre_shift;
unsigned div_mask = 0xf, pre_div_mask = 0xff;
u32 *reg;
u32 *pre_reg;
main = clock_calc_best_scalar(4, 8, 400000000, rate, &fine);
if (main < 0) {
debug("%s: Cannot set clock rate for periph %d",
__func__, periph_id);
return -1;
}
main = main - 1;
fine = fine - 1;
switch (periph_id) {
case PERIPH_ID_SPI0:
reg = &clk->div_peric1;
shift = 20;
pre_reg = &clk->div_peric4;
pre_shift = 8;
break;
case PERIPH_ID_SPI1:
reg = &clk->div_peric1;
shift = 24;
pre_reg = &clk->div_peric4;
pre_shift = 16;
break;
case PERIPH_ID_SPI2:
reg = &clk->div_peric1;
shift = 28;
pre_reg = &clk->div_peric4;
pre_shift = 24;
break;
case PERIPH_ID_SPI3:
reg = &clk->div_isp1;
shift = 16;
pre_reg = &clk->div_isp1;
pre_shift = 0;
break;
case PERIPH_ID_SPI4:
reg = &clk->div_isp1;
shift = 20;
pre_reg = &clk->div_isp1;
pre_shift = 8;
break;
default:
debug("%s: Unsupported peripheral ID %d\n", __func__,
periph_id);
return -1;
}
clrsetbits_le32(reg, div_mask << shift, (main & div_mask) << shift);
clrsetbits_le32(pre_reg, pre_div_mask << pre_shift,
(fine & pre_div_mask) << pre_shift);
return 0;
}
static unsigned long exynos4_get_i2c_clk(void)
{
struct exynos4_clock *clk =
@ -1341,9 +1575,11 @@ static unsigned long exynos4_get_i2c_clk(void)
unsigned long get_pll_clk(int pllreg)
{
if (cpu_is_exynos5())
if (cpu_is_exynos5()) {
if (proid_is_exynos5420())
return exynos5420_get_pll_clk(pllreg);
return exynos5_get_pll_clk(pllreg);
else {
} else {
if (proid_is_exynos4412())
return exynos4x12_get_pll_clk(pllreg);
return exynos4_get_pll_clk(pllreg);
@ -1375,9 +1611,11 @@ unsigned long get_i2c_clk(void)
unsigned long get_pwm_clk(void)
{
if (cpu_is_exynos5())
if (cpu_is_exynos5()) {
if (proid_is_exynos5420())
return exynos5420_get_pwm_clk();
return clock_get_periph_rate(PERIPH_ID_PWM0);
else {
} else {
if (proid_is_exynos4412())
return exynos4x12_get_pwm_clk();
return exynos4_get_pwm_clk();
@ -1386,9 +1624,11 @@ unsigned long get_pwm_clk(void)
unsigned long get_uart_clk(int dev_index)
{
if (cpu_is_exynos5())
if (cpu_is_exynos5()) {
if (proid_is_exynos5420())
return exynos5420_get_uart_clk(dev_index);
return exynos5_get_uart_clk(dev_index);
else {
} else {
if (proid_is_exynos4412())
return exynos4x12_get_uart_clk(dev_index);
return exynos4_get_uart_clk(dev_index);
@ -1397,17 +1637,23 @@ unsigned long get_uart_clk(int dev_index)
unsigned long get_mmc_clk(int dev_index)
{
if (cpu_is_exynos5())
if (cpu_is_exynos5()) {
if (proid_is_exynos5420())
return exynos5420_get_mmc_clk(dev_index);
return exynos5_get_mmc_clk(dev_index);
else
} else {
return exynos4_get_mmc_clk(dev_index);
}
}
void set_mmc_clk(int dev_index, unsigned int div)
{
if (cpu_is_exynos5())
exynos5_set_mmc_clk(dev_index, div);
else {
if (cpu_is_exynos5()) {
if (proid_is_exynos5420())
exynos5420_set_mmc_clk(dev_index, div);
else
exynos5_set_mmc_clk(dev_index, div);
} else {
if (proid_is_exynos4412())
exynos4x12_set_mmc_clk(dev_index, div);
else
@ -1439,10 +1685,13 @@ void set_mipi_clk(void)
int set_spi_clk(int periph_id, unsigned int rate)
{
if (cpu_is_exynos5())
if (cpu_is_exynos5()) {
if (proid_is_exynos5420())
return exynos5420_set_spi_clk(periph_id, rate);
return exynos5_set_spi_clk(periph_id, rate);
else
} else {
return 0;
}
}
int set_i2s_clk_prescaler(unsigned int src_frq, unsigned int dst_frq,

17
arch/arm/cpu/armv7/exynos/clock_init.h
View File

@ -10,7 +10,11 @@
#define __EXYNOS_CLOCK_INIT_H
enum {
#ifdef CONFIG_EXYNOS5420
MEM_TIMINGS_MSR_COUNT = 5,
#else
MEM_TIMINGS_MSR_COUNT = 4,
#endif
};
/* These are the ratio's for configuring ARM clock */
@ -59,6 +63,18 @@ struct mem_timings {
unsigned bpll_mdiv;
unsigned bpll_pdiv;
unsigned bpll_sdiv;
unsigned kpll_mdiv;
unsigned kpll_pdiv;
unsigned kpll_sdiv;
unsigned dpll_mdiv;
unsigned dpll_pdiv;
unsigned dpll_sdiv;
unsigned ipll_mdiv;
unsigned ipll_pdiv;
unsigned ipll_sdiv;
unsigned spll_mdiv;
unsigned spll_pdiv;
unsigned spll_sdiv;
unsigned pclk_cdrex_ratio;
unsigned direct_cmd_msr[MEM_TIMINGS_MSR_COUNT];
@ -115,6 +131,7 @@ struct mem_timings {
uint8_t send_zq_init; /* 1 to send this command */
unsigned impedance; /* drive strength impedeance */
uint8_t gate_leveling_enable; /* check gate leveling is enabled */
uint8_t read_leveling_enable; /* check h/w read leveling is enabled */
};
/**

352
arch/arm/cpu/armv7/exynos/clock_init_exynos5.c
View File

@ -24,6 +24,24 @@
DECLARE_GLOBAL_DATA_PTR;
struct arm_clk_ratios arm_clk_ratios[] = {
#ifdef CONFIG_EXYNOS5420
{
.arm_freq_mhz = 900,
.apll_mdiv = 0x96,
.apll_pdiv = 0x2,
.apll_sdiv = 0x1,
.arm2_ratio = 0x0,
.apll_ratio = 0x3,
.pclk_dbg_ratio = 0x6,
.atb_ratio = 0x6,
.periph_ratio = 0x7,
.acp_ratio = 0x0,
.cpud_ratio = 0x2,
.arm_ratio = 0x0,
}
#else
{
.arm_freq_mhz = 600,
@ -115,8 +133,133 @@ struct arm_clk_ratios arm_clk_ratios[] = {
.cpud_ratio = 0x3,
.arm_ratio = 0x0,
}
#endif
};
struct mem_timings mem_timings[] = {
#ifdef CONFIG_EXYNOS5420
{
.mem_manuf = MEM_MANUF_SAMSUNG,
.mem_type = DDR_MODE_DDR3,
.frequency_mhz = 800,
/* MPLL @800MHz*/
.mpll_mdiv = 0xc8,
.mpll_pdiv = 0x3,
.mpll_sdiv = 0x1,
/* CPLL @666MHz */
.cpll_mdiv = 0xde,
.cpll_pdiv = 0x4,
.cpll_sdiv = 0x1,
/* EPLL @600MHz */
.epll_mdiv = 0x64,
.epll_pdiv = 0x2,
.epll_sdiv = 0x1,
/* VPLL @430MHz */
.vpll_mdiv = 0xd7,
.vpll_pdiv = 0x3,
.vpll_sdiv = 0x2,
/* BPLL @800MHz */
.bpll_mdiv = 0xc8,
.bpll_pdiv = 0x3,
.bpll_sdiv = 0x1,
/* KPLL @600MHz */
.kpll_mdiv = 0x190,
.kpll_pdiv = 0x4,
.kpll_sdiv = 0x2,
/* DPLL @600MHz */
.dpll_mdiv = 0x190,
.dpll_pdiv = 0x4,
.dpll_sdiv = 0x2,
/* IPLL @370MHz */
.ipll_mdiv = 0xb9,
.ipll_pdiv = 0x3,
.ipll_sdiv = 0x2,
/* SPLL @400MHz */
.spll_mdiv = 0xc8,
.spll_pdiv = 0x3,
.spll_sdiv = 0x2,
.direct_cmd_msr = {
0x00020018, 0x00030000, 0x00010046, 0x00000d70,
0x00000c70
},
.timing_ref = 0x000000bb,
.timing_row = 0x6836650f,
.timing_data = 0x3630580b,
.timing_power = 0x41000a26,
.phy0_dqs = 0x08080808,
.phy1_dqs = 0x08080808,
.phy0_dq = 0x08080808,
.phy1_dq = 0x08080808,
.phy0_tFS = 0x8,
.phy1_tFS = 0x8,
.phy0_pulld_dqs = 0xf,
.phy1_pulld_dqs = 0xf,
.lpddr3_ctrl_phy_reset = 0x1,
.ctrl_start_point = 0x10,
.ctrl_inc = 0x10,
.ctrl_start = 0x1,
.ctrl_dll_on = 0x1,
.ctrl_ref = 0x8,
.ctrl_force = 0x1a,
.ctrl_rdlat = 0x0b,
.ctrl_bstlen = 0x08,
.fp_resync = 0x8,
.iv_size = 0x7,
.dfi_init_start = 1,
.aref_en = 1,
.rd_fetch = 0x3,
.zq_mode_dds = 0x7,
.zq_mode_term = 0x1,
.zq_mode_noterm = 1,
/*
* Dynamic Clock: Always Running
* Memory Burst length: 8
* Number of chips: 1
* Memory Bus width: 32 bit
* Memory Type: DDR3
* Additional Latancy for PLL: 0 Cycle
*/
.memcontrol = DMC_MEMCONTROL_CLK_STOP_DISABLE |
DMC_MEMCONTROL_DPWRDN_DISABLE |
DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE |
DMC_MEMCONTROL_TP_DISABLE |
DMC_MEMCONTROL_DSREF_DISABLE |
DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(0) |
DMC_MEMCONTROL_MEM_TYPE_DDR3 |
DMC_MEMCONTROL_MEM_WIDTH_32BIT |
DMC_MEMCONTROL_NUM_CHIP_1 |
DMC_MEMCONTROL_BL_8 |
DMC_MEMCONTROL_PZQ_DISABLE |
DMC_MEMCONTROL_MRR_BYTE_7_0,
.memconfig = DMC_MEMCONFIG_CHIP_MAP_SPLIT |
DMC_MEMCONFIGX_CHIP_COL_10 |
DMC_MEMCONFIGX_CHIP_ROW_15 |
DMC_MEMCONFIGX_CHIP_BANK_8,
.prechconfig_tp_cnt = 0xff,
.dpwrdn_cyc = 0xff,
.dsref_cyc = 0xffff,
.concontrol = DMC_CONCONTROL_DFI_INIT_START_DISABLE |
DMC_CONCONTROL_TIMEOUT_LEVEL0 |
DMC_CONCONTROL_RD_FETCH_DISABLE |
DMC_CONCONTROL_EMPTY_DISABLE |
DMC_CONCONTROL_AREF_EN_DISABLE |
DMC_CONCONTROL_IO_PD_CON_DISABLE,
.dmc_channels = 1,
.chips_per_channel = 1,
.chips_to_configure = 1,
.send_zq_init = 1,
.gate_leveling_enable = 1,
.read_leveling_enable = 0,
}
#else
{
.mem_manuf = MEM_MANUF_ELPIDA,
.mem_type = DDR_MODE_DDR3,
@ -324,6 +467,7 @@ struct mem_timings mem_timings[] = {
.impedance = IMP_OUTPUT_DRV_40_OHM,
.gate_leveling_enable = 1,
}
#endif
};
/**
@ -399,7 +543,7 @@ struct mem_timings *clock_get_mem_timings(void)
return NULL;
}
void system_clock_init()
static void exynos5250_system_clock_init(void)
{
struct exynos5_clock *clk =
(struct exynos5_clock *)samsung_get_base_clock();
@ -436,19 +580,13 @@ void system_clock_init()
} while ((val | MUX_BPLL_SEL_MASK) != val);
/* PLL locktime */
writel(APLL_LOCK_VAL, &clk->apll_lock);
writel(MPLL_LOCK_VAL, &clk->mpll_lock);
writel(BPLL_LOCK_VAL, &clk->bpll_lock);
writel(CPLL_LOCK_VAL, &clk->cpll_lock);
writel(GPLL_LOCK_VAL, &clk->gpll_lock);
writel(EPLL_LOCK_VAL, &clk->epll_lock);
writel(VPLL_LOCK_VAL, &clk->vpll_lock);
writel(mem->apll_pdiv * PLL_LOCK_FACTOR, &clk->apll_lock);
writel(mem->mpll_pdiv * PLL_LOCK_FACTOR, &clk->mpll_lock);
writel(mem->bpll_pdiv * PLL_LOCK_FACTOR, &clk->bpll_lock);
writel(mem->cpll_pdiv * PLL_LOCK_FACTOR, &clk->cpll_lock);
writel(mem->gpll_pdiv * PLL_X_LOCK_FACTOR, &clk->gpll_lock);
writel(mem->epll_pdiv * PLL_X_LOCK_FACTOR, &clk->epll_lock);
writel(mem->vpll_pdiv * PLL_X_LOCK_FACTOR, &clk->vpll_lock);
writel(CLK_REG_DISABLE, &clk->pll_div2_sel);
@ -640,6 +778,192 @@ void system_clock_init()
writel(val, &clk->div_fsys2);
}
static void exynos5420_system_clock_init(void)
{
struct exynos5420_clock *clk =
(struct exynos5420_clock *)samsung_get_base_clock();
struct mem_timings *mem;
struct arm_clk_ratios *arm_clk_ratio;
u32 val;
mem = clock_get_mem_timings();
arm_clk_ratio = get_arm_ratios();
/* PLL locktime */
writel(arm_clk_ratio->apll_pdiv * PLL_LOCK_FACTOR, &clk->apll_lock);
writel(mem->mpll_pdiv * PLL_LOCK_FACTOR, &clk->mpll_lock);
writel(mem->bpll_pdiv * PLL_LOCK_FACTOR, &clk->bpll_lock);
writel(mem->cpll_pdiv * PLL_LOCK_FACTOR, &clk->cpll_lock);
writel(mem->dpll_pdiv * PLL_LOCK_FACTOR, &clk->dpll_lock);
writel(mem->epll_pdiv * PLL_X_LOCK_FACTOR, &clk->epll_lock);
writel(mem->vpll_pdiv * PLL_LOCK_FACTOR, &clk->vpll_lock);
writel(mem->ipll_pdiv * PLL_LOCK_FACTOR, &clk->ipll_lock);
writel(mem->spll_pdiv * PLL_LOCK_FACTOR, &clk->spll_lock);
writel(mem->kpll_pdiv * PLL_LOCK_FACTOR, &clk->kpll_lock);
setbits_le32(&clk->src_cpu, MUX_HPM_SEL_MASK);
writel(0, &clk->src_top6);
writel(0, &clk->src_cdrex);
writel(SRC_KFC_HPM_SEL, &clk->src_kfc);
writel(HPM_RATIO, &clk->div_cpu1);
writel(CLK_DIV_CPU0_VAL, &clk->div_cpu0);
/* switch A15 clock source to OSC clock before changing APLL */
clrbits_le32(&clk->src_cpu, APLL_FOUT);
/* Set APLL */
writel(APLL_CON1_VAL, &clk->apll_con1);
val = set_pll(arm_clk_ratio->apll_mdiv,
arm_clk_ratio->apll_pdiv,
arm_clk_ratio->apll_sdiv);
writel(val, &clk->apll_con0);
while ((readl(&clk->apll_con0) & PLL_LOCKED) == 0)
;
/* now it is safe to switch to APLL */
setbits_le32(&clk->src_cpu, APLL_FOUT);
writel(SRC_KFC_HPM_SEL, &clk->src_kfc);
writel(CLK_DIV_KFC_VAL, &clk->div_kfc0);
/* switch A7 clock source to OSC clock before changing KPLL */
clrbits_le32(&clk->src_kfc, KPLL_FOUT);
/* Set KPLL*/
writel(KPLL_CON1_VAL, &clk->kpll_con1);
val = set_pll(mem->kpll_mdiv, mem->kpll_pdiv, mem->kpll_sdiv);
writel(val, &clk->kpll_con0);
while ((readl(&clk->kpll_con0) & PLL_LOCKED) == 0)
;
/* now it is safe to switch to KPLL */
setbits_le32(&clk->src_kfc, KPLL_FOUT);
/* Set MPLL */
writel(MPLL_CON1_VAL, &clk->mpll_con1);
val = set_pll(mem->mpll_mdiv, mem->mpll_pdiv, mem->mpll_sdiv);
writel(val, &clk->mpll_con0);
while ((readl(&clk->mpll_con0) & PLL_LOCKED) == 0)
;
/* Set DPLL */
writel(DPLL_CON1_VAL, &clk->dpll_con1);
val = set_pll(mem->dpll_mdiv, mem->dpll_pdiv, mem->dpll_sdiv);
writel(val, &clk->dpll_con0);
while ((readl(&clk->dpll_con0) & PLL_LOCKED) == 0)
;
/* Set EPLL */
writel(EPLL_CON2_VAL, &clk->epll_con2);
writel(EPLL_CON1_VAL, &clk->epll_con1);
val = set_pll(mem->epll_mdiv, mem->epll_pdiv, mem->epll_sdiv);
writel(val, &clk->epll_con0);
while ((readl(&clk->epll_con0) & PLL_LOCKED) == 0)
;
/* Set CPLL */
writel(CPLL_CON1_VAL, &clk->cpll_con1);
val = set_pll(mem->cpll_mdiv, mem->cpll_pdiv, mem->cpll_sdiv);
writel(val, &clk->cpll_con0);
while ((readl(&clk->cpll_con0) & PLL_LOCKED) == 0)
;
/* Set IPLL */
writel(IPLL_CON1_VAL, &clk->ipll_con1);
val = set_pll(mem->ipll_mdiv, mem->ipll_pdiv, mem->ipll_sdiv);
writel(val, &clk->ipll_con0);
while ((readl(&clk->ipll_con0) & PLL_LOCKED) == 0)
;
/* Set VPLL */
writel(VPLL_CON1_VAL, &clk->vpll_con1);
val = set_pll(mem->vpll_mdiv, mem->vpll_pdiv, mem->vpll_sdiv);
writel(val, &clk->vpll_con0);
while ((readl(&clk->vpll_con0) & PLL_LOCKED) == 0)
;
/* Set BPLL */
writel(BPLL_CON1_VAL, &clk->bpll_con1);
val = set_pll(mem->bpll_mdiv, mem->bpll_pdiv, mem->bpll_sdiv);
writel(val, &clk->bpll_con0);
while ((readl(&clk->bpll_con0) & PLL_LOCKED) == 0)
;
/* Set SPLL */
writel(SPLL_CON1_VAL, &clk->spll_con1);
val = set_pll(mem->spll_mdiv, mem->spll_pdiv, mem->spll_sdiv);
writel(val, &clk->spll_con0);
while ((readl(&clk->spll_con0) & PLL_LOCKED) == 0)
;
writel(CLK_DIV_CDREX0_VAL, &clk->div_cdrex0);
writel(CLK_DIV_CDREX1_VAL, &clk->div_cdrex1);
writel(CLK_SRC_TOP0_VAL, &clk->src_top0);
writel(CLK_SRC_TOP1_VAL, &clk->src_top1);
writel(CLK_SRC_TOP2_VAL, &clk->src_top2);
writel(CLK_SRC_TOP7_VAL, &clk->src_top7);
writel(CLK_DIV_TOP0_VAL, &clk->div_top0);
writel(CLK_DIV_TOP1_VAL, &clk->div_top1);
writel(CLK_DIV_TOP2_VAL, &clk->div_top2);
writel(0, &clk->src_top10);
writel(0, &clk->src_top11);
writel(0, &clk->src_top12);
writel(CLK_SRC_TOP3_VAL, &clk->src_top3);
writel(CLK_SRC_TOP4_VAL, &clk->src_top4);
writel(CLK_SRC_TOP5_VAL, &clk->src_top5);
/* DISP1 BLK CLK SELECTION */
writel(CLK_SRC_DISP1_0_VAL, &clk->src_disp10);
writel(CLK_DIV_DISP1_0_VAL, &clk->div_disp10);
/* AUDIO BLK */
writel(AUDIO0_SEL_EPLL, &clk->src_mau);
writel(DIV_MAU_VAL, &clk->div_mau);
/* FSYS */
writel(CLK_SRC_FSYS0_VAL, &clk->src_fsys);
writel(CLK_DIV_FSYS0_VAL, &clk->div_fsys0);
writel(CLK_DIV_FSYS1_VAL, &clk->div_fsys1);
writel(CLK_DIV_FSYS2_VAL, &clk->div_fsys2);
writel(CLK_SRC_ISP_VAL, &clk->src_isp);
writel(CLK_DIV_ISP0_VAL, &clk->div_isp0);
writel(CLK_DIV_ISP1_VAL, &clk->div_isp1);
writel(CLK_SRC_PERIC0_VAL, &clk->src_peric0);
writel(CLK_SRC_PERIC1_VAL, &clk->src_peric1);
writel(CLK_DIV_PERIC0_VAL, &clk->div_peric0);
writel(CLK_DIV_PERIC1_VAL, &clk->div_peric1);
writel(CLK_DIV_PERIC2_VAL, &clk->div_peric2);
writel(CLK_DIV_PERIC3_VAL, &clk->div_peric3);
writel(CLK_DIV_PERIC4_VAL, &clk->div_peric4);
writel(CLK_DIV_CPERI1_VAL, &clk->div_cperi1);
writel(CLK_DIV2_RATIO, &clk->clkdiv2_ratio);
writel(CLK_DIV4_RATIO, &clk->clkdiv4_ratio);
writel(CLK_DIV_G2D, &clk->div_g2d);
writel(CLK_SRC_TOP6_VAL, &clk->src_top6);
writel(CLK_SRC_CDREX_VAL, &clk->src_cdrex);
writel(CLK_SRC_KFC_VAL, &clk->src_kfc);
}
void system_clock_init(void)
{
if (proid_is_exynos5420())
exynos5420_system_clock_init();
else
exynos5250_system_clock_init();
}
void clock_init_dp_clock(void)
{
struct exynos5_clock *clk =

60
arch/arm/cpu/armv7/exynos/dmc_common.c
View File

@ -1,5 +1,5 @@
/*
* Mem setup common file for different types of DDR present on SMDK5250 boards.
* Mem setup common file for different types of DDR present on Exynos boards.
*
* Copyright (C) 2012 Samsung Electronics
*
@ -15,9 +15,9 @@
#define ZQ_INIT_TIMEOUT 10000
int dmc_config_zq(struct mem_timings *mem,
struct exynos5_phy_control *phy0_ctrl,
struct exynos5_phy_control *phy1_ctrl)
int dmc_config_zq(struct mem_timings *mem, uint32_t *phy0_con16,
uint32_t *phy1_con16, uint32_t *phy0_con17,
uint32_t *phy1_con17)
{
unsigned long val = 0;
int i;
@ -31,19 +31,19 @@ int dmc_config_zq(struct mem_timings *mem,
val |= mem->zq_mode_dds << PHY_CON16_ZQ_MODE_DDS_SHIFT;
val |= mem->zq_mode_term << PHY_CON16_ZQ_MODE_TERM_SHIFT;
val |= ZQ_CLK_DIV_EN;
writel(val, &phy0_ctrl->phy_con16);
writel(val, &phy1_ctrl->phy_con16);
writel(val, phy0_con16);
writel(val, phy1_con16);
/* Disable termination */
if (mem->zq_mode_noterm)
val |= PHY_CON16_ZQ_MODE_NOTERM_MASK;
writel(val, &phy0_ctrl->phy_con16);
writel(val, &phy1_ctrl->phy_con16);
writel(val, phy0_con16);
writel(val, phy1_con16);
/* ZQ_MANUAL_START: Enable */
val |= ZQ_MANUAL_STR;
writel(val, &phy0_ctrl->phy_con16);
writel(val, &phy1_ctrl->phy_con16);
writel(val, phy0_con16);
writel(val, phy1_con16);
/* ZQ_MANUAL_START: Disable */
val &= ~ZQ_MANUAL_STR;
@ -53,47 +53,47 @@ int dmc_config_zq(struct mem_timings *mem,
* we are looping for the ZQ_init to complete.
*/
i = ZQ_INIT_TIMEOUT;
while ((readl(&phy0_ctrl->phy_con17) & ZQ_DONE) != ZQ_DONE && i > 0) {
while ((readl(phy0_con17) & ZQ_DONE) != ZQ_DONE && i > 0) {
sdelay(100);
i--;
}
if (!i)
return -1;
writel(val, &phy0_ctrl->phy_con16);
writel(val, phy0_con16);
i = ZQ_INIT_TIMEOUT;
while ((readl(&phy1_ctrl->phy_con17) & ZQ_DONE) != ZQ_DONE && i > 0) {
while ((readl(phy1_con17) & ZQ_DONE) != ZQ_DONE && i > 0) {
sdelay(100);
i--;
}
if (!i)
return -1;
writel(val, &phy1_ctrl->phy_con16);
writel(val, phy1_con16);
return 0;
}
void update_reset_dll(struct exynos5_dmc *dmc, enum ddr_mode mode)
void update_reset_dll(uint32_t *phycontrol0, enum ddr_mode mode)
{
unsigned long val;
if (mode == DDR_MODE_DDR3) {
val = MEM_TERM_EN | PHY_TERM_EN | DMC_CTRL_SHGATE;
writel(val, &dmc->phycontrol0);
writel(val, phycontrol0);
}
/* Update DLL Information: Force DLL Resyncronization */
val = readl(&dmc->phycontrol0);
val = readl(phycontrol0);
val |= FP_RSYNC;
writel(val, &dmc->phycontrol0);
writel(val, phycontrol0);
/* Reset Force DLL Resyncronization */
val = readl(&dmc->phycontrol0);
val = readl(phycontrol0);
val &= ~FP_RSYNC;
writel(val, &dmc->phycontrol0);
writel(val, phycontrol0);
}
void dmc_config_mrs(struct mem_timings *mem, struct exynos5_dmc *dmc)
void dmc_config_mrs(struct mem_timings *mem, uint32_t *directcmd)
{
int channel, chip;
@ -107,7 +107,7 @@ void dmc_config_mrs(struct mem_timings *mem, struct exynos5_dmc *dmc)
mask |= chip << DIRECT_CMD_CHIP_SHIFT;
/* Sending NOP command */
writel(DIRECT_CMD_NOP | mask, &dmc->directcmd);
writel(DIRECT_CMD_NOP | mask, directcmd);
/*
* TODO(alim.akhtar@samsung.com): Do we need these
@ -119,14 +119,14 @@ void dmc_config_mrs(struct mem_timings *mem, struct exynos5_dmc *dmc)
/* Sending EMRS/MRS commands */
for (i = 0; i < MEM_TIMINGS_MSR_COUNT; i++) {
writel(mem->direct_cmd_msr[i] | mask,
&dmc->directcmd);
directcmd);
sdelay(0x10000);
}
if (mem->send_zq_init) {
/* Sending ZQINIT command */
writel(DIRECT_CMD_ZQINIT | mask,
&dmc->directcmd);
directcmd);
sdelay(10000);
}
@ -134,7 +134,7 @@ void dmc_config_mrs(struct mem_timings *mem, struct exynos5_dmc *dmc)
}
}
void dmc_config_prech(struct mem_timings *mem, struct exynos5_dmc *dmc)
void dmc_config_prech(struct mem_timings *mem, uint32_t *directcmd)
{
int channel, chip;
@ -146,20 +146,12 @@ void dmc_config_prech(struct mem_timings *mem, struct exynos5_dmc *dmc)
mask |= chip << DIRECT_CMD_CHIP_SHIFT;
/* PALL (all banks precharge) CMD */
writel(DIRECT_CMD_PALL | mask, &dmc->directcmd);
writel(DIRECT_CMD_PALL | mask, directcmd);
sdelay(0x10000);
}
}
}
void dmc_config_memory(struct mem_timings *mem, struct exynos5_dmc *dmc)
{
writel(mem->memconfig, &dmc->memconfig0);
writel(mem->memconfig, &dmc->memconfig1);
writel(DMC_MEMBASECONFIG0_VAL, &dmc->membaseconfig0);
writel(DMC_MEMBASECONFIG1_VAL, &dmc->membaseconfig1);
}
void mem_ctrl_init(int reset)
{
struct spl_machine_param *param = spl_get_machine_params();

439
arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c
View File

@ -1,5 +1,5 @@
/*
* DDR3 mem setup file for SMDK5250 board based on EXYNOS5
* DDR3 mem setup file for board based on EXYNOS5
*
* Copyright (C) 2012 Samsung Electronics
*
@ -11,12 +11,14 @@
#include <asm/arch/clock.h>
#include <asm/arch/cpu.h>
#include <asm/arch/dmc.h>
#include <asm/arch/power.h>
#include "common_setup.h"
#include "exynos5_setup.h"
#include "clock_init.h"
#define RDLVL_COMPLETE_TIMEOUT 10000
#define TIMEOUT 10000
#ifdef CONFIG_EXYNOS5250
static void reset_phy_ctrl(void)
{
struct exynos5_clock *clk =
@ -57,7 +59,8 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
writel(val, &phy1_ctrl->phy_con42);
/* ZQ Calibration */
if (dmc_config_zq(mem, phy0_ctrl, phy1_ctrl))
if (dmc_config_zq(mem, &phy0_ctrl->phy_con16, &phy1_ctrl->phy_con16,
&phy0_ctrl->phy_con17, &phy1_ctrl->phy_con17))
return SETUP_ERR_ZQ_CALIBRATION_FAILURE;
/* DQ Signal */
@ -68,7 +71,7 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
| (mem->dfi_init_start << CONCONTROL_DFI_INIT_START_SHIFT),
&dmc->concontrol);
update_reset_dll(dmc, DDR_MODE_DDR3);
update_reset_dll(&dmc->phycontrol0, DDR_MODE_DDR3);
/* DQS Signal */
writel(mem->phy0_dqs, &phy0_ctrl->phy_con4);
@ -93,7 +96,7 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
writel(val | (mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT),
&phy1_ctrl->phy_con12);
update_reset_dll(dmc, DDR_MODE_DDR3);
update_reset_dll(&dmc->phycontrol0, DDR_MODE_DDR3);
writel(mem->concontrol | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT),
&dmc->concontrol);
@ -124,10 +127,10 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
writel(mem->timing_power, &dmc->timingpower);
/* Send PALL command */
dmc_config_prech(mem, dmc);
dmc_config_prech(mem, &dmc->directcmd);
/* Send NOP, MRS and ZQINIT commands */
dmc_config_mrs(mem, dmc);
dmc_config_mrs(mem, &dmc->directcmd);
if (mem->gate_leveling_enable) {
val = PHY_CON0_RESET_VAL;
@ -174,7 +177,7 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
writel(val, &phy1_ctrl->phy_con1);
writel(CTRL_RDLVL_GATE_ENABLE, &dmc->rdlvl_config);
i = RDLVL_COMPLETE_TIMEOUT;
i = TIMEOUT;
while ((readl(&dmc->phystatus) &
(RDLVL_COMPLETE_CHO | RDLVL_COMPLETE_CH1)) !=
(RDLVL_COMPLETE_CHO | RDLVL_COMPLETE_CH1) && i > 0) {
@ -202,11 +205,11 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
writel(val, &phy0_ctrl->phy_con12);
writel(val, &phy1_ctrl->phy_con12);
update_reset_dll(dmc, DDR_MODE_DDR3);
update_reset_dll(&dmc->phycontrol0, DDR_MODE_DDR3);
}
/* Send PALL command */
dmc_config_prech(mem, dmc);
dmc_config_prech(mem, &dmc->directcmd);
writel(mem->memcontrol, &dmc->memcontrol);
@ -215,3 +218,419 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
| (mem->aref_en << CONCONTROL_AREF_EN_SHIFT), &dmc->concontrol);
return 0;
}
#endif
#ifdef CONFIG_EXYNOS5420
int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
int reset)
{
struct exynos5420_clock *clk =
(struct exynos5420_clock *)samsung_get_base_clock();
struct exynos5420_power *power =
(struct exynos5420_power *)samsung_get_base_power();
struct exynos5420_phy_control *phy0_ctrl, *phy1_ctrl;
struct exynos5420_dmc *drex0, *drex1;
struct exynos5420_tzasc *tzasc0, *tzasc1;
uint32_t val, n_lock_r, n_lock_w_phy0, n_lock_w_phy1;
int chip;
int i;
phy0_ctrl = (struct exynos5420_phy_control *)samsung_get_base_dmc_phy();
phy1_ctrl = (struct exynos5420_phy_control *)(samsung_get_base_dmc_phy()
+ DMC_OFFSET);
drex0 = (struct exynos5420_dmc *)samsung_get_base_dmc_ctrl();
drex1 = (struct exynos5420_dmc *)(samsung_get_base_dmc_ctrl()
+ DMC_OFFSET);
tzasc0 = (struct exynos5420_tzasc *)samsung_get_base_dmc_tzasc();
tzasc1 = (struct exynos5420_tzasc *)(samsung_get_base_dmc_tzasc()
+ DMC_OFFSET);
/* Enable PAUSE for DREX */
setbits_le32(&clk->pause, ENABLE_BIT);
/* Enable BYPASS mode */
setbits_le32(&clk->bpll_con1, BYPASS_EN);
writel(MUX_BPLL_SEL_FOUTBPLL, &clk->src_cdrex);
do {
val = readl(&clk->mux_stat_cdrex);
val &= BPLL_SEL_MASK;
} while (val != FOUTBPLL);
clrbits_le32(&clk->bpll_con1, BYPASS_EN);
/* Specify the DDR memory type as DDR3 */
val = readl(&phy0_ctrl->phy_con0);
val &= ~(PHY_CON0_CTRL_DDR_MODE_MASK << PHY_CON0_CTRL_DDR_MODE_SHIFT);
val |= (DDR_MODE_DDR3 << PHY_CON0_CTRL_DDR_MODE_SHIFT);
writel(val, &phy0_ctrl->phy_con0);
val = readl(&phy1_ctrl->phy_con0);
val &= ~(PHY_CON0_CTRL_DDR_MODE_MASK << PHY_CON0_CTRL_DDR_MODE_SHIFT);
val |= (DDR_MODE_DDR3 << PHY_CON0_CTRL_DDR_MODE_SHIFT);
writel(val, &phy1_ctrl->phy_con0);
/* Set Read Latency and Burst Length for PHY0 and PHY1 */
val = (mem->ctrl_bstlen << PHY_CON42_CTRL_BSTLEN_SHIFT) |
(mem->ctrl_rdlat << PHY_CON42_CTRL_RDLAT_SHIFT);
writel(val, &phy0_ctrl->phy_con42);
writel(val, &phy1_ctrl->phy_con42);
val = readl(&phy0_ctrl->phy_con26);
val &= ~(T_WRDATA_EN_MASK << T_WRDATA_EN_OFFSET);
val |= (T_WRDATA_EN_DDR3 << T_WRDATA_EN_OFFSET);
writel(val, &phy0_ctrl->phy_con26);
val = readl(&phy1_ctrl->phy_con26);
val &= ~(T_WRDATA_EN_MASK << T_WRDATA_EN_OFFSET);
val |= (T_WRDATA_EN_DDR3 << T_WRDATA_EN_OFFSET);
writel(val, &phy1_ctrl->phy_con26);
/*
* Set Driver strength for CK, CKE, CS & CA to 0x7
* Set Driver strength for Data Slice 0~3 to 0x7
*/
val = (0x7 << CA_CK_DRVR_DS_OFFSET) | (0x7 << CA_CKE_DRVR_DS_OFFSET) |
(0x7 << CA_CS_DRVR_DS_OFFSET) | (0x7 << CA_ADR_DRVR_DS_OFFSET);
val |= (0x7 << DA_3_DS_OFFSET) | (0x7 << DA_2_DS_OFFSET) |
(0x7 << DA_1_DS_OFFSET) | (0x7 << DA_0_DS_OFFSET);
writel(val, &phy0_ctrl->phy_con39);
writel(val, &phy1_ctrl->phy_con39);
/* ZQ Calibration */
if (dmc_config_zq(mem, &phy0_ctrl->phy_con16, &phy1_ctrl->phy_con16,
&phy0_ctrl->phy_con17, &phy1_ctrl->phy_con17))
return SETUP_ERR_ZQ_CALIBRATION_FAILURE;
clrbits_le32(&phy0_ctrl->phy_con16, ZQ_CLK_DIV_EN);
clrbits_le32(&phy1_ctrl->phy_con16, ZQ_CLK_DIV_EN);
/* DQ Signal */
val = readl(&phy0_ctrl->phy_con14);
val |= mem->phy0_pulld_dqs;
writel(val, &phy0_ctrl->phy_con14);
val = readl(&phy1_ctrl->phy_con14);
val |= mem->phy1_pulld_dqs;
writel(val, &phy1_ctrl->phy_con14);
val = MEM_TERM_EN | PHY_TERM_EN;
writel(val, &drex0->phycontrol0);
writel(val, &drex1->phycontrol0);
writel(mem->concontrol |
(mem->dfi_init_start << CONCONTROL_DFI_INIT_START_SHIFT) |
(mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT),
&drex0->concontrol);
writel(mem->concontrol |
(mem->dfi_init_start << CONCONTROL_DFI_INIT_START_SHIFT) |
(mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT),
&drex1->concontrol);
do {
val = readl(&drex0->phystatus);
} while ((val & DFI_INIT_COMPLETE) != DFI_INIT_COMPLETE);
do {
val = readl(&drex1->phystatus);
} while ((val & DFI_INIT_COMPLETE) != DFI_INIT_COMPLETE);
clrbits_le32(&drex0->concontrol, DFI_INIT_START);
clrbits_le32(&drex1->concontrol, DFI_INIT_START);
update_reset_dll(&drex0->phycontrol0, DDR_MODE_DDR3);
update_reset_dll(&drex1->phycontrol0, DDR_MODE_DDR3);
/*
* Set Base Address:
* 0x2000_0000 ~ 0x5FFF_FFFF
* 0x6000_0000 ~ 0x9FFF_FFFF
*/
/* MEMBASECONFIG0 */
val = DMC_MEMBASECONFIGX_CHIP_BASE(DMC_CHIP_BASE_0) |
DMC_MEMBASECONFIGX_CHIP_MASK(DMC_CHIP_MASK);
writel(val, &tzasc0->membaseconfig0);
writel(val, &tzasc1->membaseconfig0);
/* MEMBASECONFIG1 */
val = DMC_MEMBASECONFIGX_CHIP_BASE(DMC_CHIP_BASE_1) |
DMC_MEMBASECONFIGX_CHIP_MASK(DMC_CHIP_MASK);
writel(val, &tzasc0->membaseconfig1);
writel(val, &tzasc1->membaseconfig1);
/*
* Memory Channel Inteleaving Size
* Ares Channel interleaving = 128 bytes
*/
/* MEMCONFIG0/1 */
writel(mem->memconfig, &tzasc0->memconfig0);
writel(mem->memconfig, &tzasc1->memconfig0);
writel(mem->memconfig, &tzasc0->memconfig1);
writel(mem->memconfig, &tzasc1->memconfig1);
/* Precharge Configuration */
writel(mem->prechconfig_tp_cnt << PRECHCONFIG_TP_CNT_SHIFT,
&drex0->prechconfig0);
writel(mem->prechconfig_tp_cnt << PRECHCONFIG_TP_CNT_SHIFT,
&drex1->prechconfig0);
/*
* TimingRow, TimingData, TimingPower and Timingaref
* values as per Memory AC parameters
*/
writel(mem->timing_ref, &drex0->timingref);
writel(mem->timing_ref, &drex1->timingref);
writel(mem->timing_row, &drex0->timingrow0);
writel(mem->timing_row, &drex1->timingrow0);
writel(mem->timing_data, &drex0->timingdata0);
writel(mem->timing_data, &drex1->timingdata0);
writel(mem->timing_power, &drex0->timingpower0);
writel(mem->timing_power, &drex1->timingpower0);
if (reset) {
/*
* Send NOP, MRS and ZQINIT commands
* Sending MRS command will reset the DRAM. We should not be
* reseting the DRAM after resume, this will lead to memory
* corruption as DRAM content is lost after DRAM reset
*/
dmc_config_mrs(mem, &drex0->directcmd);
dmc_config_mrs(mem, &drex1->directcmd);
} else {
/*
* During Suspend-Resume & S/W-Reset, as soon as PMU releases
* pad retention, CKE goes high. This causes memory contents
* not to be retained during DRAM initialization. Therfore,
* there is a new control register(0x100431e8[28]) which lets us
* release pad retention and retain the memory content until the
* initialization is complete.
*/
writel(PAD_RETENTION_DRAM_COREBLK_VAL,
&power->pad_retention_dram_coreblk_option);
do {
val = readl(&power->pad_retention_dram_status);
} while (val != 0x1);
/*
* CKE PAD retention disables DRAM self-refresh mode.
* Send auto refresh command for DRAM refresh.
*/
for (i = 0; i < 128; i++) {
for (chip = 0; chip < mem->chips_to_configure; chip++) {
writel(DIRECT_CMD_REFA |
(chip << DIRECT_CMD_CHIP_SHIFT),
&drex0->directcmd);
writel(DIRECT_CMD_REFA |
(chip << DIRECT_CMD_CHIP_SHIFT),
&drex1->directcmd);
}
}
}
if (mem->gate_leveling_enable) {
writel(PHY_CON0_RESET_VAL, &phy0_ctrl->phy_con0);
writel(PHY_CON0_RESET_VAL, &phy1_ctrl->phy_con0);
setbits_le32(&phy0_ctrl->phy_con0, P0_CMD_EN);
setbits_le32(&phy1_ctrl->phy_con0, P0_CMD_EN);
val = PHY_CON2_RESET_VAL;
val |= INIT_DESKEW_EN;
writel(val, &phy0_ctrl->phy_con2);
writel(val, &phy1_ctrl->phy_con2);
val = readl(&phy0_ctrl->phy_con1);
val |= (RDLVL_PASS_ADJ_VAL << RDLVL_PASS_ADJ_OFFSET);
writel(val, &phy0_ctrl->phy_con1);
val = readl(&phy1_ctrl->phy_con1);
val |= (RDLVL_PASS_ADJ_VAL << RDLVL_PASS_ADJ_OFFSET);
writel(val, &phy1_ctrl->phy_con1);
n_lock_r = readl(&phy0_ctrl->phy_con13);
n_lock_w_phy0 = (n_lock_r & CTRL_LOCK_COARSE_MASK) >> 2;
n_lock_r = readl(&phy0_ctrl->phy_con12);
n_lock_r &= ~CTRL_DLL_ON;
n_lock_r |= n_lock_w_phy0;
writel(n_lock_r, &phy0_ctrl->phy_con12);
n_lock_r = readl(&phy1_ctrl->phy_con13);
n_lock_w_phy1 = (n_lock_r & CTRL_LOCK_COARSE_MASK) >> 2;
n_lock_r = readl(&phy1_ctrl->phy_con12);
n_lock_r &= ~CTRL_DLL_ON;
n_lock_r |= n_lock_w_phy1;
writel(n_lock_r, &phy1_ctrl->phy_con12);
val = (0x3 << DIRECT_CMD_BANK_SHIFT) | 0x4;
for (chip = 0; chip < mem->chips_to_configure; chip++) {
writel(val | (chip << DIRECT_CMD_CHIP_SHIFT),
&drex0->directcmd);
writel(val | (chip << DIRECT_CMD_CHIP_SHIFT),
&drex1->directcmd);
}
setbits_le32(&phy0_ctrl->phy_con2, RDLVL_GATE_EN);
setbits_le32(&phy1_ctrl->phy_con2, RDLVL_GATE_EN);
setbits_le32(&phy0_ctrl->phy_con0, CTRL_SHGATE);
setbits_le32(&phy1_ctrl->phy_con0, CTRL_SHGATE);
val = readl(&phy0_ctrl->phy_con1);
val &= ~(CTRL_GATEDURADJ_MASK);
writel(val, &phy0_ctrl->phy_con1);
val = readl(&phy1_ctrl->phy_con1);
val &= ~(CTRL_GATEDURADJ_MASK);
writel(val, &phy1_ctrl->phy_con1);
writel(CTRL_RDLVL_GATE_ENABLE, &drex0->rdlvl_config);
i = TIMEOUT;
while (((readl(&drex0->phystatus) & RDLVL_COMPLETE_CHO) !=
RDLVL_COMPLETE_CHO) && (i > 0)) {
/*
* TODO(waihong): Comment on how long this take to
* timeout
*/
sdelay(100);
i--;
}
if (!i)
return SETUP_ERR_RDLV_COMPLETE_TIMEOUT;
writel(CTRL_RDLVL_GATE_DISABLE, &drex0->rdlvl_config);
writel(CTRL_RDLVL_GATE_ENABLE, &drex1->rdlvl_config);
i = TIMEOUT;
while (((readl(&drex1->phystatus) & RDLVL_COMPLETE_CHO) !=
RDLVL_COMPLETE_CHO) && (i > 0)) {
/*
* TODO(waihong): Comment on how long this take to
* timeout
*/
sdelay(100);
i--;
}
if (!i)
return SETUP_ERR_RDLV_COMPLETE_TIMEOUT;
writel(CTRL_RDLVL_GATE_DISABLE, &drex1->rdlvl_config);
writel(0, &phy0_ctrl->phy_con14);
writel(0, &phy1_ctrl->phy_con14);
val = (0x3 << DIRECT_CMD_BANK_SHIFT);
for (chip = 0; chip < mem->chips_to_configure; chip++) {
writel(val | (chip << DIRECT_CMD_CHIP_SHIFT),
&drex0->directcmd);
writel(val | (chip << DIRECT_CMD_CHIP_SHIFT),
&drex1->directcmd);
}
if (mem->read_leveling_enable) {
/* Set Read DQ Calibration */
val = (0x3 << DIRECT_CMD_BANK_SHIFT) | 0x4;
for (chip = 0; chip < mem->chips_to_configure; chip++) {
writel(val | (chip << DIRECT_CMD_CHIP_SHIFT),
&drex0->directcmd);
writel(val | (chip << DIRECT_CMD_CHIP_SHIFT),
&drex1->directcmd);
}
val = readl(&phy0_ctrl->phy_con1);
val |= READ_LEVELLING_DDR3;
writel(val, &phy0_ctrl->phy_con1);
val = readl(&phy1_ctrl->phy_con1);
val |= READ_LEVELLING_DDR3;
writel(val, &phy1_ctrl->phy_con1);
val = readl(&phy0_ctrl->phy_con2);
val |= (RDLVL_EN | RDLVL_INCR_ADJ);
writel(val, &phy0_ctrl->phy_con2);
val = readl(&phy1_ctrl->phy_con2);
val |= (RDLVL_EN | RDLVL_INCR_ADJ);
writel(val, &phy1_ctrl->phy_con2);
setbits_le32(&drex0->rdlvl_config,
CTRL_RDLVL_DATA_ENABLE);
i = TIMEOUT;
while (((readl(&drex0->phystatus) & RDLVL_COMPLETE_CHO)
!= RDLVL_COMPLETE_CHO) && (i > 0)) {
/*
* TODO(waihong): Comment on how long this take
* to timeout
*/
sdelay(100);
i--;
}
if (!i)
return SETUP_ERR_RDLV_COMPLETE_TIMEOUT;
clrbits_le32(&drex0->rdlvl_config,
CTRL_RDLVL_DATA_ENABLE);
setbits_le32(&drex1->rdlvl_config,
CTRL_RDLVL_DATA_ENABLE);
i = TIMEOUT;
while (((readl(&drex1->phystatus) & RDLVL_COMPLETE_CHO)
!= RDLVL_COMPLETE_CHO) && (i > 0)) {
/*
* TODO(waihong): Comment on how long this take
* to timeout
*/
sdelay(100);
i--;
}
if (!i)
return SETUP_ERR_RDLV_COMPLETE_TIMEOUT;
clrbits_le32(&drex1->rdlvl_config,
CTRL_RDLVL_DATA_ENABLE);
val = (0x3 << DIRECT_CMD_BANK_SHIFT);
for (chip = 0; chip < mem->chips_to_configure; chip++) {
writel(val | (chip << DIRECT_CMD_CHIP_SHIFT),
&drex0->directcmd);
writel(val | (chip << DIRECT_CMD_CHIP_SHIFT),
&drex1->directcmd);
}
update_reset_dll(&drex0->phycontrol0, DDR_MODE_DDR3);
update_reset_dll(&drex1->phycontrol0, DDR_MODE_DDR3);
}
/* Common Settings for Leveling */
val = PHY_CON12_RESET_VAL;
writel((val + n_lock_w_phy0), &phy0_ctrl->phy_con12);
writel((val + n_lock_w_phy1), &phy1_ctrl->phy_con12);
setbits_le32(&phy0_ctrl->phy_con2, DLL_DESKEW_EN);
setbits_le32(&phy1_ctrl->phy_con2, DLL_DESKEW_EN);
}
/* Send PALL command */
dmc_config_prech(mem, &drex0->directcmd);
dmc_config_prech(mem, &drex1->directcmd);
writel(mem->memcontrol, &drex0->memcontrol);
writel(mem->memcontrol, &drex1->memcontrol);
/*
* Set DMC Concontrol: Enable auto-refresh counter, provide
* read data fetch cycles and enable DREX auto set powerdown
* for input buffer of I/O in none read memory state.
*/
writel(mem->concontrol | (mem->aref_en << CONCONTROL_AREF_EN_SHIFT) |
(mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT)|
DMC_CONCONTROL_IO_PD_CON(0x2),
&drex0->concontrol);
writel(mem->concontrol | (mem->aref_en << CONCONTROL_AREF_EN_SHIFT) |
(mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT)|
DMC_CONCONTROL_IO_PD_CON(0x2),
&drex1->concontrol);
/*
* Enable Clock Gating Control for DMC
* this saves around 25 mw dmc power as compared to the power
* consumption without these bits enabled
*/
setbits_le32(&drex0->cgcontrol, DMC_INTERNAL_CG);
setbits_le32(&drex1->cgcontrol, DMC_INTERNAL_CG);
return 0;
}
#endif

778
arch/arm/cpu/armv7/exynos/exynos5_setup.h
View File

@ -12,42 +12,16 @@
#include <config.h>
#include <asm/arch/dmc.h>
/* APLL_CON1 */
#define APLL_CON1_VAL (0x00203800)
#define NOT_AVAILABLE 0
#define DATA_MASK 0xFFFFF
/* MPLL_CON1 */
#define MPLL_CON1_VAL (0x00203800)
/* CPLL_CON1 */
#define CPLL_CON1_VAL (0x00203800)
/* GPLL_CON1 */
#define GPLL_CON1_VAL (0x00203800)
/* EPLL_CON1, CON2 */
#define EPLL_CON1_VAL 0x00000000
#define EPLL_CON2_VAL 0x00000080
/* VPLL_CON1, CON2 */
#define VPLL_CON1_VAL 0x00000000
#define VPLL_CON2_VAL 0x00000080
/* BPLL_CON1 */
#define BPLL_CON1_VAL 0x00203800
#define ENABLE_BIT 0x1
#define DISABLE_BIT 0x0
#define CA_SWAP_EN (1 << 0)
/* Set PLL */
#define set_pll(mdiv, pdiv, sdiv) (1<<31 | mdiv<<16 | pdiv<<8 | sdiv)
/* CLK_SRC_CPU */
/* 0 = MOUTAPLL, 1 = SCLKMPLL */
#define MUX_HPM_SEL 0
#define MUX_CPU_SEL 0
#define MUX_APLL_SEL 1
#define CLK_SRC_CPU_VAL ((MUX_HPM_SEL << 20) \
| (MUX_CPU_SEL << 16) \
| (MUX_APLL_SEL))
/* MEMCONTROL register bit fields */
#define DMC_MEMCONTROL_CLK_STOP_DISABLE (0 << 0)
#define DMC_MEMCONTROL_DPWRDN_DISABLE (0 << 1)
@ -78,6 +52,7 @@
/* MEMCONFIG0 register bit fields */
#define DMC_MEMCONFIGX_CHIP_MAP_INTERLEAVED (1 << 12)
#define DMC_MEMCONFIG_CHIP_MAP_SPLIT (2 << 12)
#define DMC_MEMCONFIGX_CHIP_COL_10 (3 << 8)
#define DMC_MEMCONFIGX_CHIP_ROW_14 (2 << 4)
#define DMC_MEMCONFIGX_CHIP_ROW_15 (3 << 4)
@ -90,6 +65,17 @@
DMC_MEMBASECONFIGX_CHIP_MASK(0x780) \
)
/*
* As we use channel interleaving, therefore value of the base address
* register must be set as half of the bus base address
* RAM start addess is 0x2000_0000 which means chip_base is 0x20, so
* we need to set half 0x10 to the membaseconfigx registers
* see exynos5420 UM section 17.17.3.21 for more.
*/
#define DMC_CHIP_BASE_0 0x10
#define DMC_CHIP_BASE_1 0x50
#define DMC_CHIP_MASK 0x7C0
#define DMC_MEMBASECONFIG0_VAL DMC_MEMBASECONFIG_VAL(0x40)
#define DMC_MEMBASECONFIG1_VAL DMC_MEMBASECONFIG_VAL(0x80)
@ -113,29 +99,24 @@
/* COJCONTROL register bit fields */
#define DMC_CONCONTROL_IO_PD_CON_DISABLE (0 << 3)
#define DMC_CONCONTROL_IO_PD_CON_ENABLE (1 << 3)
#define DMC_CONCONTROL_AREF_EN_DISABLE (0 << 5)
#define DMC_CONCONTROL_AREF_EN_ENABLE (1 << 5)
#define DMC_CONCONTROL_EMPTY_DISABLE (0 << 8)
#define DMC_CONCONTROL_EMPTY_ENABLE (1 << 8)
#define DMC_CONCONTROL_RD_FETCH_DISABLE (0x0 << 12)
#define DMC_CONCONTROL_TIMEOUT_LEVEL0 (0xFFF << 16)
#define DMC_CONCONTROL_DFI_INIT_START_DISABLE (0 << 28)
/* CLK_DIV_CPU0_VAL */
#define CLK_DIV_CPU0_VAL ((ARM2_RATIO << 28) \
| (APLL_RATIO << 24) \
| (PCLK_DBG_RATIO << 20) \
| (ATB_RATIO << 16) \
| (PERIPH_RATIO << 12) \
| (ACP_RATIO << 8) \
| (CPUD_RATIO << 4) \
| (ARM_RATIO))
#define DMC_CONCONTROL_VAL 0x1FFF2101
#define DREX_CONCONTROL_VAL DMC_CONCONTROL_VAL \
| DMC_CONCONTROL_AREF_EN_ENABLE \
| DMC_CONCONTROL_IO_PD_CON_ENABLE
/* CLK_FSYS */
#define CLK_SRC_FSYS0_VAL 0x66666
#define CLK_DIV_FSYS0_VAL 0x0BB00000
#define DMC_CONCONTROL_IO_PD_CON(x) (x << 6)
/* CLK_DIV_CPU1 */
/* CLK_DIV_CPU1 */
#define HPM_RATIO 0x2
#define COPY_RATIO 0x0
@ -164,10 +145,367 @@
/* CLK_DIV_SYSLFT */
#define CLK_DIV_SYSLFT_VAL 0x00000311
#define MUX_APLL_SEL_MASK (1 << 0)
#define MUX_MPLL_SEL_MASK (1 << 8)
#define MPLL_SEL_MOUT_MPLLFOUT (2 << 8)
#define MUX_CPLL_SEL_MASK (1 << 8)
#define MUX_EPLL_SEL_MASK (1 << 12)
#define MUX_VPLL_SEL_MASK (1 << 16)
#define MUX_GPLL_SEL_MASK (1 << 28)
#define MUX_BPLL_SEL_MASK (1 << 0)
#define MUX_HPM_SEL_MASK (1 << 20)
#define HPM_SEL_SCLK_MPLL (1 << 21)
#define PLL_LOCKED (1 << 29)
#define APLL_CON0_LOCKED (1 << 29)
#define MPLL_CON0_LOCKED (1 << 29)
#define BPLL_CON0_LOCKED (1 << 29)
#define CPLL_CON0_LOCKED (1 << 29)
#define EPLL_CON0_LOCKED (1 << 29)
#define GPLL_CON0_LOCKED (1 << 29)
#define VPLL_CON0_LOCKED (1 << 29)
#define CLK_REG_DISABLE 0x0
#define TOP2_VAL 0x0110000
/* SCLK_SRC_ISP - set SPI0/1 to 6 = SCLK_MPLL_USER */
#define SPI0_ISP_SEL 6
#define SPI1_ISP_SEL 6
#define SCLK_SRC_ISP_VAL (SPI1_ISP_SEL << 4) \
| (SPI0_ISP_SEL << 0)
/* SCLK_DIV_ISP - set SPI0/1 to 0xf = divide by 16 */
#define SPI0_ISP_RATIO 0xf
#define SPI1_ISP_RATIO 0xf
#define SCLK_DIV_ISP_VAL (SPI1_ISP_RATIO << 12) \
| (SPI0_ISP_RATIO << 0)
/* CLK_DIV_FSYS2 */
#define MMC2_RATIO_MASK 0xf
#define MMC2_RATIO_VAL 0x3
#define MMC2_RATIO_OFFSET 0
#define MMC2_PRE_RATIO_MASK 0xff
#define MMC2_PRE_RATIO_VAL 0x9
#define MMC2_PRE_RATIO_OFFSET 8
#define MMC3_RATIO_MASK 0xf
#define MMC3_RATIO_VAL 0x1
#define MMC3_RATIO_OFFSET 16
#define MMC3_PRE_RATIO_MASK 0xff
#define MMC3_PRE_RATIO_VAL 0x0
#define MMC3_PRE_RATIO_OFFSET 24
/* CLK_SRC_LEX */
#define CLK_SRC_LEX_VAL 0x0
/* CLK_DIV_LEX */
#define CLK_DIV_LEX_VAL 0x10
/* CLK_DIV_R0X */
#define CLK_DIV_R0X_VAL 0x10
/* CLK_DIV_L0X */
#define CLK_DIV_R1X_VAL 0x10
/* CLK_DIV_ISP2 */
#define CLK_DIV_ISP2_VAL 0x1
/* CLK_SRC_KFC */
#define SRC_KFC_HPM_SEL (1 << 15)
/* CLK_SRC_KFC */
#define CLK_SRC_KFC_VAL 0x00008001
/* CLK_DIV_KFC */
#define CLK_DIV_KFC_VAL 0x03300110
/* CLK_DIV2_RATIO */
#define CLK_DIV2_RATIO 0x10111150
/* CLK_DIV4_RATIO */
#define CLK_DIV4_RATIO 0x00000003
/* CLK_DIV_G2D */
#define CLK_DIV_G2D 0x00000010
/*
* DIV_DISP1_0
* For DP, divisor should be 2
*/
#define CLK_DIV_DISP1_0_FIMD1 (2 << 0)
/* CLK_GATE_IP_DISP1 */
#define CLK_GATE_DP1_ALLOW (1 << 4)
/* AUDIO CLK SEL */
#define AUDIO0_SEL_EPLL (0x6 << 28)
#define AUDIO0_RATIO 0x5
#define PCM0_RATIO 0x3
#define DIV_MAU_VAL (PCM0_RATIO << 24 | AUDIO0_RATIO << 20)
/* CLK_SRC_CDREX */
#define MUX_MCLK_CDR_MSPLL (1 << 4)
#define MUX_BPLL_SEL_FOUTBPLL (1 << 0)
#define BPLL_SEL_MASK 0x7
#define FOUTBPLL 2
#define DDR3PHY_CTRL_PHY_RESET (1 << 0)
#define DDR3PHY_CTRL_PHY_RESET_OFF (0 << 0)
#define PHY_CON0_RESET_VAL 0x17020a40
#define P0_CMD_EN (1 << 14)
#define BYTE_RDLVL_EN (1 << 13)
#define CTRL_SHGATE (1 << 8)
#define PHY_CON1_RESET_VAL 0x09210100
#define RDLVL_PASS_ADJ_VAL 0x6
#define RDLVL_PASS_ADJ_OFFSET 16
#define CTRL_GATEDURADJ_MASK (0xf << 20)
#define READ_LEVELLING_DDR3 0x0100
#define PHY_CON2_RESET_VAL 0x00010004
#define INIT_DESKEW_EN (1 << 6)
#define DLL_DESKEW_EN (1 << 12)
#define RDLVL_GATE_EN (1 << 24)
#define RDLVL_EN (1 << 25)
#define RDLVL_INCR_ADJ (0x1 << 16)
/* DREX_PAUSE */
#define DREX_PAUSE_EN (1 << 0)
#define BYPASS_EN (1 << 22)
/* MEMMORY VAL */
#define PHY_CON0_VAL 0x17021A00
#define PHY_CON12_RESET_VAL 0x10100070
#define PHY_CON12_VAL 0x10107F50
#define CTRL_START (1 << 6)
#define CTRL_DLL_ON (1 << 5)
#define CTRL_FORCE_MASK (0x7F << 8)
#define CTRL_LOCK_COARSE_MASK (0x7F << 10)
#define CTRL_OFFSETD_RESET_VAL 0x8
#define CTRL_OFFSETD_VAL 0x7F
#define CTRL_OFFSETR0 0x7F
#define CTRL_OFFSETR1 0x7F
#define CTRL_OFFSETR2 0x7F
#define CTRL_OFFSETR3 0x7F
#define PHY_CON4_VAL (CTRL_OFFSETR0 << 0 | \
CTRL_OFFSETR1 << 8 | \
CTRL_OFFSETR2 << 16 | \
CTRL_OFFSETR3 << 24)
#define PHY_CON4_RESET_VAL 0x08080808
#define CTRL_OFFSETW0 0x7F
#define CTRL_OFFSETW1 0x7F
#define CTRL_OFFSETW2 0x7F
#define CTRL_OFFSETW3 0x7F
#define PHY_CON6_VAL (CTRL_OFFSETW0 << 0 | \
CTRL_OFFSETW1 << 8 | \
CTRL_OFFSETW2 << 16 | \
CTRL_OFFSETW3 << 24)
#define PHY_CON6_RESET_VAL 0x08080808
#define PHY_CON14_RESET_VAL 0x001F0000
#define CTRL_PULLD_DQS 0xF
#define CTRL_PULLD_DQS_OFFSET 0
/* ZQ Configurations */
#define PHY_CON16_RESET_VAL 0x08000304
#define ZQ_CLK_EN (1 << 27)
#define ZQ_CLK_DIV_EN (1 << 18)
#define ZQ_MANUAL_STR (1 << 1)
#define ZQ_DONE (1 << 0)
#define ZQ_MODE_DDS_OFFSET 24
#define CTRL_RDLVL_GATE_ENABLE 1
#define CTRL_RDLVL_GATE_DISABLE 0
#define CTRL_RDLVL_DATA_ENABLE 2
/* Direct Command */
#define DIRECT_CMD_NOP 0x07000000
#define DIRECT_CMD_PALL 0x01000000
#define DIRECT_CMD_ZQINIT 0x0a000000
#define DIRECT_CMD_CHANNEL_SHIFT 28
#define DIRECT_CMD_CHIP_SHIFT 20
#define DIRECT_CMD_BANK_SHIFT 16
#define DIRECT_CMD_REFA (5 << 24)
#define DIRECT_CMD_MRS1 0x71C00
#define DIRECT_CMD_MRS2 0x10BFC
#define DIRECT_CMD_MRS3 0x0050C
#define DIRECT_CMD_MRS4 0x00868
#define DIRECT_CMD_MRS5 0x00C04
/* Drive Strength */
#define IMPEDANCE_48_OHM 4
#define IMPEDANCE_40_OHM 5
#define IMPEDANCE_34_OHM 6
#define IMPEDANCE_30_OHM 7
#define PHY_CON39_VAL_48_OHM 0x09240924
#define PHY_CON39_VAL_40_OHM 0x0B6D0B6D
#define PHY_CON39_VAL_34_OHM 0x0DB60DB6
#define PHY_CON39_VAL_30_OHM 0x0FFF0FFF
#define CTRL_BSTLEN_OFFSET 8
#define CTRL_RDLAT_OFFSET 0
#define CMD_DEFAULT_LPDDR3 0xF
#define CMD_DEFUALT_OFFSET 0
#define T_WRDATA_EN 0x7
#define T_WRDATA_EN_DDR3 0x8
#define T_WRDATA_EN_OFFSET 16
#define T_WRDATA_EN_MASK 0x1f
#define PHY_CON31_VAL 0x0C183060
#define PHY_CON32_VAL 0x60C18306
#define PHY_CON33_VAL 0x00000030
#define PHY_CON31_RESET_VAL 0x0
#define PHY_CON32_RESET_VAL 0x0
#define PHY_CON33_RESET_VAL 0x0
#define SL_DLL_DYN_CON_EN (1 << 1)
#define FP_RESYNC (1 << 3)
#define CTRL_START (1 << 6)
#define DMC_AREF_EN (1 << 5)
#define DMC_CONCONTROL_EMPTY (1 << 8)
#define DFI_INIT_START (1 << 28)
#define DMC_MEMCONTROL_VAL 0x00312700
#define CLK_STOP_EN (1 << 0)
#define DPWRDN_EN (1 << 1)
#define DSREF_EN (1 << 5)
#define MEMBASECONFIG_CHIP_MASK_VAL 0x7E0
#define MEMBASECONFIG_CHIP_MASK_OFFSET 0
#define MEMBASECONFIG0_CHIP_BASE_VAL 0x20
#define MEMBASECONFIG1_CHIP_BASE_VAL 0x40
#define CHIP_BASE_OFFSET 16
#define MEMCONFIG_VAL 0x1323
#define PRECHCONFIG_DEFAULT_VAL 0xFF000000
#define PWRDNCONFIG_DEFAULT_VAL 0xFFFF00FF
#define TIMINGAREF_VAL 0x5d
#define TIMINGROW_VAL 0x345A8692
#define TIMINGDATA_VAL 0x3630065C
#define TIMINGPOWER_VAL 0x50380336
#define DFI_INIT_COMPLETE (1 << 3)
#define BRBRSVCONTROL_VAL 0x00000033
#define BRBRSVCONFIG_VAL 0x88778877
/* Clock Gating Control (CGCONTROL) register */
#define MEMIF_CG_EN (1 << 3) /* Memory interface clock gating */
#define SCG_CG_EN (1 << 2) /* Scheduler clock gating */
#define BUSIF_WR_CG_EN (1 << 1) /* Bus interface write channel clock gating */
#define BUSIF_RD_CG_EN (1 << 0) /* Bus interface read channel clock gating */
#define DMC_INTERNAL_CG (MEMIF_CG_EN | SCG_CG_EN | \
BUSIF_WR_CG_EN | BUSIF_RD_CG_EN)
/* DMC PHY Control0 register */
#define PHY_CONTROL0_RESET_VAL 0x0
#define MEM_TERM_EN (1 << 31) /* Termination enable for memory */
#define PHY_TERM_EN (1 << 30) /* Termination enable for PHY */
#define DMC_CTRL_SHGATE (1 << 29) /* Duration of DQS gating signal */
#define FP_RSYNC (1 << 3) /* Force DLL resyncronization */
/* Driver strength for CK, CKE, CS & CA */
#define IMP_OUTPUT_DRV_40_OHM 0x5
#define IMP_OUTPUT_DRV_30_OHM 0x7
#define DA_3_DS_OFFSET 25
#define DA_2_DS_OFFSET 22
#define DA_1_DS_OFFSET 19
#define DA_0_DS_OFFSET 16
#define CA_CK_DRVR_DS_OFFSET 9
#define CA_CKE_DRVR_DS_OFFSET 6
#define CA_CS_DRVR_DS_OFFSET 3
#define CA_ADR_DRVR_DS_OFFSET 0
#define PHY_CON42_CTRL_BSTLEN_SHIFT 8
#define PHY_CON42_CTRL_RDLAT_SHIFT 0
/*
* Definitions that differ with SoC's.
* Below is the part defining macros for smdk5250.
* Else part introduces macros for smdk5420.
*/
#ifndef CONFIG_SMDK5420
/* APLL_CON1 */
#define APLL_CON1_VAL (0x00203800)
/* MPLL_CON1 */
#define MPLL_CON1_VAL (0x00203800)
/* CPLL_CON1 */
#define CPLL_CON1_VAL (0x00203800)
/* DPLL_CON1 */
#define DPLL_CON1_VAL (NOT_AVAILABLE)
/* GPLL_CON1 */
#define GPLL_CON1_VAL (0x00203800)
/* EPLL_CON1, CON2 */
#define EPLL_CON1_VAL 0x00000000
#define EPLL_CON2_VAL 0x00000080
/* VPLL_CON1, CON2 */
#define VPLL_CON1_VAL 0x00000000
#define VPLL_CON2_VAL 0x00000080
/* RPLL_CON1, CON2 */
#define RPLL_CON1_VAL NOT_AVAILABLE
#define RPLL_CON2_VAL NOT_AVAILABLE
/* BPLL_CON1 */
#define BPLL_CON1_VAL 0x00203800
/* SPLL_CON1 */
#define SPLL_CON1_VAL NOT_AVAILABLE
/* IPLL_CON1 */
#define IPLL_CON1_VAL NOT_AVAILABLE
/* KPLL_CON1 */
#define KPLL_CON1_VAL NOT_AVAILABLE
/* CLK_SRC_ISP */
#define CLK_SRC_ISP_VAL NOT_AVAILABLE
#define CLK_DIV_ISP0_VAL 0x31
#define CLK_DIV_ISP1_VAL 0x0
/* CLK_FSYS */
#define CLK_SRC_FSYS0_VAL 0x66666
#define CLK_DIV_FSYS0_VAL 0x0BB00000
#define CLK_DIV_FSYS1_VAL NOT_AVAILABLE
#define CLK_DIV_FSYS2_VAL NOT_AVAILABLE
/* CLK_SRC_CPU */
/* 0 = MOUTAPLL, 1 = SCLKMPLL */
#define MUX_HPM_SEL 0
#define MUX_CPU_SEL 0
#define MUX_APLL_SEL 1
#define CLK_SRC_CPU_VAL ((MUX_HPM_SEL << 20) \
| (MUX_CPU_SEL << 16) \
| (MUX_APLL_SEL))
/* CLK_SRC_CDREX */
#define CLK_SRC_CDREX_VAL 0x1
/* CLK_DIV_CDREX */
#define CLK_DIV_CDREX0_VAL NOT_AVAILABLE
#define CLK_DIV_CDREX1_VAL NOT_AVAILABLE
/* CLK_DIV_CPU0_VAL */
#define CLK_DIV_CPU0_VAL NOT_AVAILABLE
#define MCLK_CDREX2_RATIO 0x0
#define ACLK_EFCON_RATIO 0x1
#define MCLK_DPHY_RATIO 0x1
@ -247,6 +585,11 @@
| (MUX_ACLK_300_DISP1_SUB_SEL << 6) \
| (MUX_ACLK_200_DISP1_SUB_SEL << 4))
#define CLK_SRC_TOP4_VAL NOT_AVAILABLE
#define CLK_SRC_TOP5_VAL NOT_AVAILABLE
#define CLK_SRC_TOP6_VAL NOT_AVAILABLE
#define CLK_SRC_TOP7_VAL NOT_AVAILABLE
/* CLK_DIV_TOP0 */
#define ACLK_300_DISP1_RATIO 0x2
#define ACLK_400_G3D_RATIO 0x0
@ -279,40 +622,11 @@
| (ACLK_400_IOP_RATIO << 16) \
| (ACLK_300_GSCL_RATIO << 12))
/* APLL_LOCK */
#define APLL_LOCK_VAL (0x546)
/* MPLL_LOCK */
#define MPLL_LOCK_VAL (0x546)
/* CPLL_LOCK */
#define CPLL_LOCK_VAL (0x546)
/* GPLL_LOCK */
#define GPLL_LOCK_VAL (0x546)
/* EPLL_LOCK */
#define EPLL_LOCK_VAL (0x3A98)
/* VPLL_LOCK */
#define VPLL_LOCK_VAL (0x3A98)
/* BPLL_LOCK */
#define BPLL_LOCK_VAL (0x546)
#define CLK_DIV_TOP2_VAL NOT_AVAILABLE
#define MUX_APLL_SEL_MASK (1 << 0)
#define MUX_MPLL_SEL_MASK (1 << 8)
#define MPLL_SEL_MOUT_MPLLFOUT (2 << 8)
#define MUX_CPLL_SEL_MASK (1 << 8)
#define MUX_EPLL_SEL_MASK (1 << 12)
#define MUX_VPLL_SEL_MASK (1 << 16)
#define MUX_GPLL_SEL_MASK (1 << 28)
#define MUX_BPLL_SEL_MASK (1 << 0)
#define MUX_HPM_SEL_MASK (1 << 20)
#define HPM_SEL_SCLK_MPLL (1 << 21)
#define APLL_CON0_LOCKED (1 << 29)
#define MPLL_CON0_LOCKED (1 << 29)
#define BPLL_CON0_LOCKED (1 << 29)
#define CPLL_CON0_LOCKED (1 << 29)
#define EPLL_CON0_LOCKED (1 << 29)
#define GPLL_CON0_LOCKED (1 << 29)
#define VPLL_CON0_LOCKED (1 << 29)
#define CLK_REG_DISABLE 0x0
#define TOP2_VAL 0x0110000
/* PLL Lock Value Factor */
#define PLL_LOCK_FACTOR 250
#define PLL_X_LOCK_FACTOR 3000
/* CLK_SRC_PERIC0 */
#define PWM_SEL 6
@ -336,18 +650,6 @@
| (SPI1_SEL << 20) \
| (SPI0_SEL << 16))
/* SCLK_SRC_ISP - set SPI0/1 to 6 = SCLK_MPLL_USER */
#define SPI0_ISP_SEL 6
#define SPI1_ISP_SEL 6
#define SCLK_SRC_ISP_VAL (SPI1_ISP_SEL << 4) \
| (SPI0_ISP_SEL << 0)
/* SCLK_DIV_ISP - set SPI0/1 to 0xf = divide by 16 */
#define SPI0_ISP_RATIO 0xf
#define SPI1_ISP_RATIO 0xf
#define SCLK_DIV_ISP_VAL (SPI1_ISP_RATIO << 12) \
| (SPI0_ISP_RATIO << 0)
/* CLK_DIV_PERIL0 */
#define UART5_RATIO 7
#define UART4_RATIO 7
@ -380,105 +682,201 @@
#define PWM_RATIO 8
#define CLK_DIV_PERIC3_VAL (PWM_RATIO << 0)
/* CLK_DIV_FSYS2 */
#define MMC2_RATIO_MASK 0xf
#define MMC2_RATIO_VAL 0x3
#define MMC2_RATIO_OFFSET 0
#define MMC2_PRE_RATIO_MASK 0xff
#define MMC2_PRE_RATIO_VAL 0x9
#define MMC2_PRE_RATIO_OFFSET 8
#define MMC3_RATIO_MASK 0xf
#define MMC3_RATIO_VAL 0x1
#define MMC3_RATIO_OFFSET 16
#define MMC3_PRE_RATIO_MASK 0xff
#define MMC3_PRE_RATIO_VAL 0x0
#define MMC3_PRE_RATIO_OFFSET 24
/* CLK_SRC_LEX */
#define CLK_SRC_LEX_VAL 0x0
/* CLK_DIV_LEX */
#define CLK_DIV_LEX_VAL 0x10
/* CLK_DIV_R0X */
#define CLK_DIV_R0X_VAL 0x10
/* CLK_DIV_L0X */
#define CLK_DIV_R1X_VAL 0x10
/* CLK_DIV_ISP0 */
#define CLK_DIV_ISP0_VAL 0x31
/* CLK_DIV_ISP1 */
#define CLK_DIV_ISP1_VAL 0x0
/* CLK_DIV_ISP2 */
#define CLK_DIV_ISP2_VAL 0x1
/* CLK_DIV_PERIC4 */
#define CLK_DIV_PERIC4_VAL NOT_AVAILABLE
/* CLK_SRC_DISP1_0 */
#define CLK_SRC_DISP1_0_VAL 0x6
#define CLK_DIV_DISP1_0_VAL NOT_AVAILABLE
/*
* DIV_DISP1_0
* For DP, divisor should be 2
*/
#define CLK_DIV_DISP1_0_FIMD1 (2 << 0)
#define APLL_FOUT (1 << 0)
#define KPLL_FOUT NOT_AVAILABLE
/* CLK_GATE_IP_DISP1 */
#define CLK_GATE_DP1_ALLOW (1 << 4)
#define CLK_DIV_CPERI1_VAL NOT_AVAILABLE
#define DDR3PHY_CTRL_PHY_RESET (1 << 0)
#define DDR3PHY_CTRL_PHY_RESET_OFF (0 << 0)
#else
#define PAD_RETENTION_DRAM_COREBLK_VAL 0x10000000
#define PHY_CON0_RESET_VAL 0x17020a40
#define P0_CMD_EN (1 << 14)
#define BYTE_RDLVL_EN (1 << 13)
#define CTRL_SHGATE (1 << 8)
/* APLL_CON1 */
#define APLL_CON1_VAL (0x0020F300)
#define PHY_CON1_RESET_VAL 0x09210100
#define CTRL_GATEDURADJ_MASK (0xf << 20)
/* MPLL_CON1 */
#define MPLL_CON1_VAL (0x0020F300)
#define PHY_CON2_RESET_VAL 0x00010004
#define INIT_DESKEW_EN (1 << 6)
#define RDLVL_GATE_EN (1 << 24)
/*ZQ Configurations */
#define PHY_CON16_RESET_VAL 0x08000304
/* CPLL_CON1 */
#define CPLL_CON1_VAL 0x0020f300
#define ZQ_CLK_DIV_EN (1 << 18)
#define ZQ_MANUAL_STR (1 << 1)
#define ZQ_DONE (1 << 0)
/* DPLL_CON1 */
#define DPLL_CON1_VAL (0x0020F300)
#define CTRL_RDLVL_GATE_ENABLE 1
#define CTRL_RDLVL_GATE_DISABLE 1
/* GPLL_CON1 */
#define GPLL_CON1_VAL (NOT_AVAILABLE)
/* Direct Command */
#define DIRECT_CMD_NOP 0x07000000
#define DIRECT_CMD_PALL 0x01000000
#define DIRECT_CMD_ZQINIT 0x0a000000
#define DIRECT_CMD_CHANNEL_SHIFT 28
#define DIRECT_CMD_CHIP_SHIFT 20
/* DMC PHY Control0 register */
#define PHY_CONTROL0_RESET_VAL 0x0
#define MEM_TERM_EN (1 << 31) /* Termination enable for memory */
#define PHY_TERM_EN (1 << 30) /* Termination enable for PHY */
#define DMC_CTRL_SHGATE (1 << 29) /* Duration of DQS gating signal */
#define FP_RSYNC (1 << 3) /* Force DLL resyncronization */
/* EPLL_CON1, CON2 */
#define EPLL_CON1_VAL 0x00000000
#define EPLL_CON2_VAL 0x00000080
/* Driver strength for CK, CKE, CS & CA */
#define IMP_OUTPUT_DRV_40_OHM 0x5
#define IMP_OUTPUT_DRV_30_OHM 0x7
#define CA_CK_DRVR_DS_OFFSET 9
#define CA_CKE_DRVR_DS_OFFSET 6
#define CA_CS_DRVR_DS_OFFSET 3
#define CA_ADR_DRVR_DS_OFFSET 0
/* VPLL_CON1, CON2 */
#define VPLL_CON1_VAL 0x0020f300
#define VPLL_CON2_VAL NOT_AVAILABLE
#define PHY_CON42_CTRL_BSTLEN_SHIFT 8
#define PHY_CON42_CTRL_RDLAT_SHIFT 0
/* RPLL_CON1, CON2 */
#define RPLL_CON1_VAL 0x00000000
#define RPLL_CON2_VAL 0x00000080
/* BPLL_CON1 */
#define BPLL_CON1_VAL 0x0020f300
/* SPLL_CON1 */
#define SPLL_CON1_VAL 0x0020f300
/* IPLL_CON1 */
#define IPLL_CON1_VAL 0x00000080
/* KPLL_CON1 */
#define KPLL_CON1_VAL 0x200000
/* CLK_SRC_ISP */
#define CLK_SRC_ISP_VAL 0x33366000
#define CLK_DIV_ISP0_VAL 0x13131300
#define CLK_DIV_ISP1_VAL 0xbb110202
/* CLK_FSYS */
#define CLK_SRC_FSYS0_VAL 0x33033300
#define CLK_DIV_FSYS0_VAL 0x0
#define CLK_DIV_FSYS1_VAL 0x04f13c4f
#define CLK_DIV_FSYS2_VAL 0x041d0000
/* CLK_SRC_CPU */
/* 0 = MOUTAPLL, 1 = SCLKMPLL */
#define MUX_HPM_SEL 1
#define MUX_CPU_SEL 0
#define MUX_APLL_SEL 1
#define CLK_SRC_CPU_VAL ((MUX_HPM_SEL << 20) \
| (MUX_CPU_SEL << 16) \
| (MUX_APLL_SEL))
/* CLK_SRC_CDREX */
#define CLK_SRC_CDREX_VAL 0x00000011
/* CLK_DIV_CDREX */
#define CLK_DIV_CDREX0_VAL 0x30010100
#define CLK_DIV_CDREX1_VAL 0x300
#define CLK_DIV_CDREX_VAL 0x17010100
/* CLK_DIV_CPU0_VAL */
#define CLK_DIV_CPU0_VAL 0x01440020
/* CLK_SRC_TOP */
#define CLK_SRC_TOP0_VAL 0x12221222
#define CLK_SRC_TOP1_VAL 0x00100200
#define CLK_SRC_TOP2_VAL 0x11101000
#define CLK_SRC_TOP3_VAL 0x11111111
#define CLK_SRC_TOP4_VAL 0x11110111
#define CLK_SRC_TOP5_VAL 0x11111100
#define CLK_SRC_TOP6_VAL 0x11110111
#define CLK_SRC_TOP7_VAL 0x00022200
/* CLK_DIV_TOP */
#define CLK_DIV_TOP0_VAL 0x23712311
#define CLK_DIV_TOP1_VAL 0x13100B00
#define CLK_DIV_TOP2_VAL 0x11101100
/* PLL Lock Value Factor */
#define PLL_LOCK_FACTOR 200
#define PLL_X_LOCK_FACTOR 3000
/* CLK_SRC_PERIC0 */
#define SPDIF_SEL 1
#define PWM_SEL 3
#define UART4_SEL 3
#define UART3_SEL 3
#define UART2_SEL 3
#define UART1_SEL 3
#define UART0_SEL 3
/* SRC_CLOCK = SCLK_RPLL */
#define CLK_SRC_PERIC0_VAL ((SPDIF_SEL << 28) \
| (PWM_SEL << 24) \
| (UART4_SEL << 20) \
| (UART3_SEL << 16) \
| (UART2_SEL << 12) \
| (UART1_SEL << 8) \
| (UART0_SEL << 4))
/* CLK_SRC_PERIC1 */
/* SRC_CLOCK = SCLK_EPLL */
#define SPI0_SEL 6
#define SPI1_SEL 6
#define SPI2_SEL 6
#define AUDIO0_SEL 6
#define AUDIO1_SEL 6
#define AUDIO2_SEL 6
#define CLK_SRC_PERIC1_VAL ((SPI2_SEL << 28) \
| (SPI1_SEL << 24) \
| (SPI0_SEL << 20) \
| (AUDIO2_SEL << 16) \
| (AUDIO2_SEL << 12) \
| (AUDIO2_SEL << 8))
/* CLK_DIV_PERIC0 */
#define PWM_RATIO 8
#define UART4_RATIO 9
#define UART3_RATIO 9
#define UART2_RATIO 9
#define UART1_RATIO 9
#define UART0_RATIO 9
#define CLK_DIV_PERIC0_VAL ((PWM_RATIO << 28) \
| (UART4_RATIO << 24) \
| (UART3_RATIO << 20) \
| (UART2_RATIO << 16) \
| (UART1_RATIO << 12) \
| (UART0_RATIO << 8))
/* CLK_DIV_PERIC1 */
#define SPI2_RATIO 0x1
#define SPI1_RATIO 0x1
#define SPI0_RATIO 0x1
#define CLK_DIV_PERIC1_VAL ((SPI2_RATIO << 28) \
| (SPI1_RATIO << 24) \
| (SPI0_RATIO << 20))
/* CLK_DIV_PERIC2 */
#define PCM2_RATIO 0x3
#define PCM1_RATIO 0x3
#define CLK_DIV_PERIC2_VAL ((PCM2_RATIO << 24) \
| (PCM1_RATIO << 16))
/* CLK_DIV_PERIC3 */
#define AUDIO2_RATIO 0x5
#define AUDIO1_RATIO 0x5
#define AUDIO0_RATIO 0x5
#define CLK_DIV_PERIC3_VAL ((AUDIO2_RATIO << 28) \
| (AUDIO1_RATIO << 24) \
| (AUDIO0_RATIO << 20))
/* CLK_DIV_PERIC4 */
#define SPI2_PRE_RATIO 0x2
#define SPI1_PRE_RATIO 0x2
#define SPI0_PRE_RATIO 0x2
#define CLK_DIV_PERIC4_VAL ((SPI2_PRE_RATIO << 24) \
| (SPI1_PRE_RATIO << 16) \
| (SPI0_PRE_RATIO << 8))
/* CLK_SRC_DISP1_0 */
#define CLK_SRC_DISP1_0_VAL 0x10666600
#define CLK_DIV_DISP1_0_VAL 0x01050211
#define APLL_FOUT (1 << 0)
#define KPLL_FOUT (1 << 0)
#define CLK_DIV_CPERI1_VAL 0x3f3f0000
#endif
struct mem_timings;
@ -490,7 +888,7 @@ enum {
};
/*
* Memory variant specific initialization code
* Memory variant specific initialization code for DDR3
*
* @param mem Memory timings for this memory type.
* @param mem_iv_size Memory interleaving size is a configurable parameter
@ -503,49 +901,45 @@ enum {
int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
int reset);
/* Memory variant specific initialization code for LPDDR3 */
void lpddr3_mem_ctrl_init(void);
/*
* Configure ZQ I/O interface
*
* @param mem Memory timings for this memory type.
* @param phy0_ctrl Pointer to struct containing PHY0 control reg
* @param phy1_ctrl Pointer to struct containing PHY1 control reg
* @param phy0_con16 Register address for dmc_phy0->phy_con16
* @param phy1_con16 Register address for dmc_phy1->phy_con16
* @param phy0_con17 Register address for dmc_phy0->phy_con17
* @param phy1_con17 Register address for dmc_phy1->phy_con17
* @return 0 if ok, -1 on error
*/
int dmc_config_zq(struct mem_timings *mem,
struct exynos5_phy_control *phy0_ctrl,
struct exynos5_phy_control *phy1_ctrl);
int dmc_config_zq(struct mem_timings *mem, uint32_t *phy0_con16,
uint32_t *phy1_con16, uint32_t *phy0_con17,
uint32_t *phy1_con17);
/*
* Send NOP and MRS/EMRS Direct commands
*
* @param mem Memory timings for this memory type.
* @param dmc Pointer to struct of DMC registers
* @param directcmd Register address for dmc_phy->directcmd
*/
void dmc_config_mrs(struct mem_timings *mem, struct exynos5_dmc *dmc);
void dmc_config_mrs(struct mem_timings *mem, uint32_t *directcmd);
/*
* Send PALL Direct commands
*
* @param mem Memory timings for this memory type.
* @param dmc Pointer to struct of DMC registers
* @param directcmd Register address for dmc_phy->directcmd
*/
void dmc_config_prech(struct mem_timings *mem, struct exynos5_dmc *dmc);
/*
* Configure the memconfig and membaseconfig registers
*
* @param mem Memory timings for this memory type.
* @param exynos5_dmc Pointer to struct of DMC registers
*/
void dmc_config_memory(struct mem_timings *mem, struct exynos5_dmc *dmc);
void dmc_config_prech(struct mem_timings *mem, uint32_t *directcmd);
/*
* Reset the DLL. This function is common between DDR3 and LPDDR2.
* However, the reset value is different. So we are passing a flag
* ddr_mode to distinguish between LPDDR2 and DDR3.
*
* @param exynos5_dmc Pointer to struct of DMC registers
* @param phycontrol0 Register address for dmc_phy->phycontrol0
* @param ddr_mode Type of DDR memory
*/
void update_reset_dll(struct exynos5_dmc *, enum ddr_mode);
void update_reset_dll(uint32_t *phycontrol0, enum ddr_mode);
#endif

260
arch/arm/cpu/armv7/exynos/pinmux.c
View File

@ -46,6 +46,42 @@ static void exynos5_uart_config(int peripheral)
}
}
static void exynos5420_uart_config(int peripheral)
{
struct exynos5420_gpio_part1 *gpio1 =
(struct exynos5420_gpio_part1 *)samsung_get_base_gpio_part1();
struct s5p_gpio_bank *bank;
int i, start, count;
switch (peripheral) {
case PERIPH_ID_UART0:
bank = &gpio1->a0;
start = 0;
count = 4;
break;
case PERIPH_ID_UART1:
bank = &gpio1->a0;
start = 4;
count = 4;
break;
case PERIPH_ID_UART2:
bank = &gpio1->a1;
start = 0;
count = 4;
break;
case PERIPH_ID_UART3:
bank = &gpio1->a1;
start = 4;
count = 2;
break;
}
for (i = start; i < start + count; i++) {
s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
}
}
static int exynos5_mmc_config(int peripheral, int flags)
{
struct exynos5_gpio_part1 *gpio1 =
@ -101,6 +137,75 @@ static int exynos5_mmc_config(int peripheral, int flags)
return 0;
}
static int exynos5420_mmc_config(int peripheral, int flags)
{
struct exynos5420_gpio_part3 *gpio3 =
(struct exynos5420_gpio_part3 *)samsung_get_base_gpio_part3();
struct s5p_gpio_bank *bank = NULL, *bank_ext = NULL;
int i, start;
switch (peripheral) {
case PERIPH_ID_SDMMC0:
bank = &gpio3->c0;
bank_ext = &gpio3->c3;
start = 0;
break;
case PERIPH_ID_SDMMC1:
bank = &gpio3->c1;
bank_ext = &gpio3->d1;
start = 4;
break;
case PERIPH_ID_SDMMC2:
bank = &gpio3->c2;
bank_ext = NULL;
start = 0;
break;
default:
start = 0;
debug("%s: invalid peripheral %d", __func__, peripheral);
return -1;
}
if ((flags & PINMUX_FLAG_8BIT_MODE) && !bank_ext) {
debug("SDMMC device %d does not support 8bit mode",
peripheral);
return -1;
}
if (flags & PINMUX_FLAG_8BIT_MODE) {
for (i = start; i <= (start + 3); i++) {
s5p_gpio_cfg_pin(bank_ext, i, GPIO_FUNC(0x2));
s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_UP);
s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X);
}
}
for (i = 0; i < 3; i++) {
/*
* MMC0 is intended to be used for eMMC. The
* card detect pin is used as a VDDEN signal to
* power on the eMMC. The 5420 iROM makes
* this same assumption.
*/
if ((peripheral == PERIPH_ID_SDMMC0) && (i == 2)) {
s5p_gpio_set_value(bank, i, 1);
s5p_gpio_cfg_pin(bank, i, GPIO_OUTPUT);
} else {
s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
}
s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
}
for (i = 3; i <= 6; i++) {
s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
s5p_gpio_set_pull(bank, i, GPIO_PULL_UP);
s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
}
return 0;
}
static void exynos5_sromc_config(int flags)
{
struct exynos5_gpio_part1 *gpio1 =
@ -216,6 +321,59 @@ static void exynos5_i2c_config(int peripheral, int flags)
}
}
static void exynos5420_i2c_config(int peripheral)
{
struct exynos5420_gpio_part1 *gpio1 =
(struct exynos5420_gpio_part1 *)samsung_get_base_gpio_part1();
switch (peripheral) {
case PERIPH_ID_I2C0:
s5p_gpio_cfg_pin(&gpio1->b3, 0, GPIO_FUNC(0x2));
s5p_gpio_cfg_pin(&gpio1->b3, 1, GPIO_FUNC(0x2));
break;
case PERIPH_ID_I2C1:
s5p_gpio_cfg_pin(&gpio1->b3, 2, GPIO_FUNC(0x2));
s5p_gpio_cfg_pin(&gpio1->b3, 3, GPIO_FUNC(0x2));
break;
case PERIPH_ID_I2C2:
s5p_gpio_cfg_pin(&gpio1->a0, 6, GPIO_FUNC(0x3));
s5p_gpio_cfg_pin(&gpio1->a0, 7, GPIO_FUNC(0x3));
break;
case PERIPH_ID_I2C3:
s5p_gpio_cfg_pin(&gpio1->a1, 2, GPIO_FUNC(0x3));
s5p_gpio_cfg_pin(&gpio1->a1, 3, GPIO_FUNC(0x3));
break;
case PERIPH_ID_I2C4:
s5p_gpio_cfg_pin(&gpio1->a2, 0, GPIO_FUNC(0x3));
s5p_gpio_cfg_pin(&gpio1->a2, 1, GPIO_FUNC(0x3));
break;
case PERIPH_ID_I2C5:
s5p_gpio_cfg_pin(&gpio1->a2, 2, GPIO_FUNC(0x3));
s5p_gpio_cfg_pin(&gpio1->a2, 3, GPIO_FUNC(0x3));
break;
case PERIPH_ID_I2C6:
s5p_gpio_cfg_pin(&gpio1->b1, 3, GPIO_FUNC(0x4));
s5p_gpio_cfg_pin(&gpio1->b1, 4, GPIO_FUNC(0x4));
break;
case PERIPH_ID_I2C7:
s5p_gpio_cfg_pin(&gpio1->b2, 2, GPIO_FUNC(0x3));
s5p_gpio_cfg_pin(&gpio1->b2, 3, GPIO_FUNC(0x3));
break;
case PERIPH_ID_I2C8:
s5p_gpio_cfg_pin(&gpio1->b3, 4, GPIO_FUNC(0x2));
s5p_gpio_cfg_pin(&gpio1->b3, 5, GPIO_FUNC(0x2));
break;
case PERIPH_ID_I2C9:
s5p_gpio_cfg_pin(&gpio1->b3, 6, GPIO_FUNC(0x2));
s5p_gpio_cfg_pin(&gpio1->b3, 7, GPIO_FUNC(0x2));
break;
case PERIPH_ID_I2C10:
s5p_gpio_cfg_pin(&gpio1->b4, 0, GPIO_FUNC(0x2));
s5p_gpio_cfg_pin(&gpio1->b4, 1, GPIO_FUNC(0x2));
break;
}
}
static void exynos5_i2s_config(int peripheral)
{
int i;
@ -279,6 +437,58 @@ void exynos5_spi_config(int peripheral)
}
}
void exynos5420_spi_config(int peripheral)
{
int cfg, pin, i;
struct s5p_gpio_bank *bank = NULL;
struct exynos5420_gpio_part1 *gpio1 =
(struct exynos5420_gpio_part1 *)samsung_get_base_gpio_part1();
struct exynos5420_gpio_part4 *gpio4 =
(struct exynos5420_gpio_part4 *)samsung_get_base_gpio_part4();
switch (peripheral) {
case PERIPH_ID_SPI0:
bank = &gpio1->a2;
cfg = GPIO_FUNC(0x2);
pin = 0;
break;
case PERIPH_ID_SPI1:
bank = &gpio1->a2;
cfg = GPIO_FUNC(0x2);
pin = 4;
break;
case PERIPH_ID_SPI2:
bank = &gpio1->b1;
cfg = GPIO_FUNC(0x5);
pin = 1;
break;
case PERIPH_ID_SPI3:
bank = &gpio4->f1;
cfg = GPIO_FUNC(0x2);
pin = 0;
break;
case PERIPH_ID_SPI4:
cfg = 0;
pin = 0;
break;
default:
cfg = 0;
pin = 0;
debug("%s: invalid peripheral %d", __func__, peripheral);
return;
}
if (peripheral != PERIPH_ID_SPI4) {
for (i = pin; i < pin + 4; i++)
s5p_gpio_cfg_pin(bank, i, cfg);
} else {
for (i = 0; i < 2; i++) {
s5p_gpio_cfg_pin(&gpio4->f0, i + 2, GPIO_FUNC(0x4));
s5p_gpio_cfg_pin(&gpio4->e0, i + 4, GPIO_FUNC(0x4));
}
}
}
static int exynos5_pinmux_config(int peripheral, int flags)
{
switch (peripheral) {
@ -325,6 +535,48 @@ static int exynos5_pinmux_config(int peripheral, int flags)
return 0;
}
static int exynos5420_pinmux_config(int peripheral, int flags)
{
switch (peripheral) {
case PERIPH_ID_UART0:
case PERIPH_ID_UART1:
case PERIPH_ID_UART2:
case PERIPH_ID_UART3:
exynos5420_uart_config(peripheral);
break;
case PERIPH_ID_SDMMC0:
case PERIPH_ID_SDMMC1:
case PERIPH_ID_SDMMC2:
case PERIPH_ID_SDMMC3:
return exynos5420_mmc_config(peripheral, flags);
case PERIPH_ID_SPI0:
case PERIPH_ID_SPI1:
case PERIPH_ID_SPI2:
case PERIPH_ID_SPI3:
case PERIPH_ID_SPI4:
exynos5420_spi_config(peripheral);
break;
case PERIPH_ID_I2C0:
case PERIPH_ID_I2C1:
case PERIPH_ID_I2C2:
case PERIPH_ID_I2C3:
case PERIPH_ID_I2C4:
case PERIPH_ID_I2C5:
case PERIPH_ID_I2C6:
case PERIPH_ID_I2C7:
case PERIPH_ID_I2C8:
case PERIPH_ID_I2C9:
case PERIPH_ID_I2C10:
exynos5420_i2c_config(peripheral);
break;
default:
debug("%s: invalid peripheral %d", __func__, peripheral);
return -1;
}
return 0;
}
static void exynos4_i2c_config(int peripheral, int flags)
{
struct exynos4_gpio_part1 *gpio1 =
@ -475,13 +727,17 @@ static int exynos4_pinmux_config(int peripheral, int flags)
int exynos_pinmux_config(int peripheral, int flags)
{
if (cpu_is_exynos5()) {
return exynos5_pinmux_config(peripheral, flags);
if (proid_is_exynos5420())
return exynos5420_pinmux_config(peripheral, flags);
else if (proid_is_exynos5250())
return exynos5_pinmux_config(peripheral, flags);
} else if (cpu_is_exynos4()) {
return exynos4_pinmux_config(peripheral, flags);
} else {
debug("pinmux functionality not supported\n");
return -1;
}
return -1;
}
#ifdef CONFIG_OF_CONTROL

12
arch/arm/cpu/armv7/mx5/clock.c
View File

@ -749,6 +749,18 @@ void enable_nfc_clk(unsigned char enable)
MXC_CCM_CCGR5_EMI_ENFC(cg));
}
#ifdef CONFIG_FSL_IIM
void enable_efuse_prog_supply(bool enable)
{
if (enable)
setbits_le32(&mxc_ccm->cgpr,
MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE);
else
clrbits_le32(&mxc_ccm->cgpr,
MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE);
}
#endif
/* Config main_bus_clock for periphs */
static int config_periph_clk(u32 ref, u32 freq)
{

23
arch/arm/cpu/armv7/mx6/clock.c
View File

@ -94,7 +94,7 @@ static u32 decode_pll(enum pll_clocks pll, u32 infreq)
div = __raw_readl(&imx_ccm->analog_pll_enet);
div &= BM_ANADIG_PLL_ENET_DIV_SELECT;
return (div == 3 ? 125000000 : 25000000 * (div << 1));
return 25000000 * (div + (div >> 1) + 1);
default:
return 0;
}
@ -310,7 +310,18 @@ static u32 get_mmdc_ch0_clk(void)
return freq / (podf + 1);
}
#else
static u32 get_mmdc_ch0_clk(void)
{
u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
u32 mmdc_ch0_podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >>
MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET;
return get_periph_clk() / (mmdc_ch0_podf + 1);
}
#endif
#ifdef CONFIG_FEC_MXC
int enable_fec_anatop_clock(void)
{
u32 reg = 0;
@ -339,16 +350,6 @@ int enable_fec_anatop_clock(void)
return 0;
}
#else
static u32 get_mmdc_ch0_clk(void)
{
u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
u32 mmdc_ch0_podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >>
MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET;
return get_periph_clk() / (mmdc_ch0_podf + 1);
}
#endif
static u32 get_usdhc_clk(u32 port)

112
arch/arm/cpu/armv7/mx6/soc.c
View File

@ -19,6 +19,14 @@
#include <asm/arch/mxc_hdmi.h>
#include <asm/arch/crm_regs.h>
#define VDDPU_MASK (0x1f << 9)
enum ldo_reg {
LDO_ARM,
LDO_SOC,
LDO_PU,
};
struct scu_regs {
u32 ctrl;
u32 config;
@ -93,6 +101,20 @@ void init_aips(void)
writel(0x00000000, &aips2->opacr4);
}
static void clear_ldo_ramp(void)
{
struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
int reg;
/* ROM may modify LDO ramp up time according to fuse setting, so in
* order to be in the safe side we neeed to reset these settings to
* match the reset value: 0'b00
*/
reg = readl(&anatop->ana_misc2);
reg &= ~(0x3f << 24);
writel(reg, &anatop->ana_misc2);
}
/*
* Set the VDDSOC
*
@ -101,10 +123,11 @@ void init_aips(void)
* Possible values are from 0.725V to 1.450V in steps of
* 0.025V (25mV).
*/
void set_vddsoc(u32 mv)
static int set_ldo_voltage(enum ldo_reg ldo, u32 mv)
{
struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
u32 val, reg = readl(&anatop->reg_core);
u32 val, step, old, reg = readl(&anatop->reg_core);
u8 shift;
if (mv < 725)
val = 0x00; /* Power gated off */
@ -113,12 +136,37 @@ void set_vddsoc(u32 mv)
else
val = (mv - 700) / 25;
/*
* Mask out the REG_CORE[22:18] bits (REG2_TRIG)
* and set them to the calculated value (0.7V + val * 0.25V)
*/
reg = (reg & ~(0x1F << 18)) | (val << 18);
clear_ldo_ramp();
switch (ldo) {
case LDO_SOC:
shift = 18;
break;
case LDO_PU:
shift = 9;
break;
case LDO_ARM:
shift = 0;
break;
default:
return -EINVAL;
}
old = (reg & (0x1F << shift)) >> shift;
step = abs(val - old);
if (step == 0)
return 0;
reg = (reg & ~(0x1F << shift)) | (val << shift);
writel(reg, &anatop->reg_core);
/*
* The LDO ramp-up is based on 64 clock cycles of 24 MHz = 2.6 us per
* step
*/
udelay(3 * step);
return 0;
}
static void imx_set_wdog_powerdown(bool enable)
@ -131,13 +179,50 @@ static void imx_set_wdog_powerdown(bool enable)
writew(enable, &wdog2->wmcr);
}
static void imx_set_vddpu_power_down(void)
{
struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
struct gpc_regs *gpc = (struct gpc_regs *)GPC_BASE_ADDR;
u32 reg;
/*
* Disable the brown out detection since we are going to be
* disabling the LDO.
*/
reg = readl(&anatop->ana_misc2);
reg &= ~ANADIG_ANA_MISC2_REG1_BO_EN;
writel(reg, &anatop->ana_misc2);
/* need to power down xPU in GPC before turning off PU LDO */
reg = readl(&gpc->gpu_ctrl);
writel(reg | 0x1, &gpc->gpu_ctrl);
reg = readl(&gpc->ctrl);
writel(reg | 0x1, &gpc->ctrl);
while (readl(&gpc->ctrl) & 0x1)
;
/* Mask the ANATOP brown out interrupt in the GPC. */
reg = readl(&gpc->imr4);
reg |= 0x80000000;
writel(reg, &gpc->imr4);
/* disable VDDPU */
writel(VDDPU_MASK, &anatop->reg_core_clr);
/* Clear the BO interrupt in the ANATOP. */
reg = readl(&anatop->ana_misc1);
reg |= 0x80000000;
writel(reg, &anatop->ana_misc1);
}
int arch_cpu_init(void)
{
init_aips();
set_vddsoc(1200); /* Set VDDSOC to 1.2V */
imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
imx_set_vddpu_power_down();
#ifdef CONFIG_APBH_DMA
/* Start APBH DMA */
@ -147,9 +232,18 @@ int arch_cpu_init(void)
return 0;
}
int board_postclk_init(void)
{
set_ldo_voltage(LDO_SOC, 1175); /* Set VDDSOC to 1.175V */
return 0;
}
#ifndef CONFIG_SYS_DCACHE_OFF
void enable_caches(void)
{
/* Avoid random hang when download by usb */
invalidate_dcache_all();
/* Enable D-cache. I-cache is already enabled in start.S */
dcache_enable();
}

1
arch/arm/cpu/armv7/omap-common/abb.c
View File

@ -11,6 +11,7 @@
#include <common.h>
#include <asm/omap_common.h>
#include <asm/arch/clock.h>
#include <asm/io.h>
#include <asm/arch/sys_proto.h>

14
arch/arm/cpu/armv7/omap-common/emif-common.c
View File

@ -50,20 +50,6 @@ inline u32 emif_num(u32 base)
return 0;
}
/*
* Get SDRAM type connected to EMIF.
* Assuming similar SDRAM parts are connected to both EMIF's
* which is typically the case. So it is sufficient to get
* SDRAM type from EMIF1.
*/
u32 emif_sdram_type()
{
struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE;
return (readl(&emif->emif_sdram_config) &
EMIF_REG_SDRAM_TYPE_MASK) >> EMIF_REG_SDRAM_TYPE_SHIFT;
}
static inline u32 get_mr(u32 base, u32 cs, u32 mr_addr)
{
u32 mr;

24
arch/arm/cpu/armv7/omap5/hw_data.c
View File

@ -39,17 +39,6 @@ static const struct dpll_params mpu_dpll_params_1_5ghz[NUM_SYS_CLKS] = {
{625, 15, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
};
/* OPP NOM FREQUENCY for ES2.0, OPP HIGH for ES1.0 */
static const struct dpll_params mpu_dpll_params_1100mhz[NUM_SYS_CLKS] = {
{275, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
{1375, 20, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
{1375, 23, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
{550, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{1375, 47, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
};
/* OPP NOM FREQUENCY for ES1.0 */
static const struct dpll_params mpu_dpll_params_800mhz[NUM_SYS_CLKS] = {
{200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
@ -83,6 +72,7 @@ static const struct dpll_params mpu_dpll_params_499mhz[NUM_SYS_CLKS] = {
{493, 37, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
};
/* OPP NOM FREQUENCY for OMAP5 ES2.0, and DRA7 ES1.0 */
static const struct dpll_params mpu_dpll_params_1ghz[NUM_SYS_CLKS] = {
{250, 2, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
{500, 9, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
@ -169,13 +159,13 @@ static const struct dpll_params per_dpll_params_768mhz_es2[NUM_SYS_CLKS] = {
};
static const struct dpll_params per_dpll_params_768mhz_dra7xx[NUM_SYS_CLKS] = {
{32, 0, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 12 MHz */
{32, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 12 MHz */
{96, 4, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 20 MHz */
{160, 6, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 16.8 MHz */
{20, 0, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 19.2 MHz */
{192, 12, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 26 MHz */
{160, 6, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 16.8 MHz */
{20, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 19.2 MHz */
{192, 12, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{10, 0, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 38.4 MHz */
{10, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 38.4 MHz */
};
static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = {
@ -272,7 +262,7 @@ struct dplls omap5_dplls_es1 = {
};
struct dplls omap5_dplls_es2 = {
.mpu = mpu_dpll_params_1100mhz,
.mpu = mpu_dpll_params_1ghz,
.core = core_dpll_params_2128mhz_ddr532_es2,
.per = per_dpll_params_768mhz_es2,
.iva = iva_dpll_params_2330mhz,

6
arch/arm/cpu/armv7/zynq/slcr.c
View File

@ -101,6 +101,12 @@ void zynq_slcr_devcfg_enable(void)
zynq_slcr_lock();
}
u32 zynq_slcr_get_boot_mode(void)
{
/* Get the bootmode register value */
return readl(&slcr_base->boot_mode);
}
u32 zynq_slcr_get_idcode(void)
{
return (readl(&slcr_base->pss_idcode) & SLCR_IDCODE_MASK) >>

17
arch/arm/cpu/armv8/Makefile Normal file
View File

@ -0,0 +1,17 @@
#
# (C) Copyright 2000-2003
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# SPDX-License-Identifier: GPL-2.0+
#
extra-y := start.o
obj-y += cpu.o
obj-y += generic_timer.o
obj-y += cache_v8.o
obj-y += exceptions.o
obj-y += cache.o
obj-y += tlb.o
obj-y += gic.o
obj-y += transition.o

136
arch/arm/cpu/armv8/cache.S Normal file
View File

@ -0,0 +1,136 @@
/*
* (C) Copyright 2013
* David Feng <fenghua@phytium.com.cn>
*
* This file is based on sample code from ARMv8 ARM.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <asm-offsets.h>
#include <config.h>
#include <version.h>
#include <asm/macro.h>
#include <linux/linkage.h>
/*
* void __asm_flush_dcache_level(level)
*
* clean and invalidate one level cache.
*
* x0: cache level
* x1~x9: clobbered
*/
ENTRY(__asm_flush_dcache_level)
lsl x1, x0, #1
msr csselr_el1, x1 /* select cache level */
isb /* sync change of cssidr_el1 */
mrs x6, ccsidr_el1 /* read the new cssidr_el1 */
and x2, x6, #7 /* x2 <- log2(cache line size)-4 */
add x2, x2, #4 /* x2 <- log2(cache line size) */
mov x3, #0x3ff
and x3, x3, x6, lsr #3 /* x3 <- max number of #ways */
add w4, w3, w3
sub w4, w4, 1 /* round up log2(#ways + 1) */
clz w5, w4 /* bit position of #ways */
mov x4, #0x7fff
and x4, x4, x6, lsr #13 /* x4 <- max number of #sets */
/* x1 <- cache level << 1 */
/* x2 <- line length offset */
/* x3 <- number of cache ways - 1 */
/* x4 <- number of cache sets - 1 */
/* x5 <- bit position of #ways */
loop_set:
mov x6, x3 /* x6 <- working copy of #ways */
loop_way:
lsl x7, x6, x5
orr x9, x1, x7 /* map way and level to cisw value */
lsl x7, x4, x2
orr x9, x9, x7 /* map set number to cisw value */
dc cisw, x9 /* clean & invalidate by set/way */
subs x6, x6, #1 /* decrement the way */
b.ge loop_way
subs x4, x4, #1 /* decrement the set */
b.ge loop_set
ret
ENDPROC(__asm_flush_dcache_level)
/*
* void __asm_flush_dcache_all(void)
*
* clean and invalidate all data cache by SET/WAY.
*/
ENTRY(__asm_flush_dcache_all)
dsb sy
mrs x10, clidr_el1 /* read clidr_el1 */
lsr x11, x10, #24
and x11, x11, #0x7 /* x11 <- loc */
cbz x11, finished /* if loc is 0, exit */
mov x15, lr
mov x0, #0 /* start flush at cache level 0 */
/* x0 <- cache level */
/* x10 <- clidr_el1 */
/* x11 <- loc */
/* x15 <- return address */
loop_level:
lsl x1, x0, #1
add x1, x1, x0 /* x0 <- tripled cache level */
lsr x1, x10, x1
and x1, x1, #7 /* x1 <- cache type */
cmp x1, #2
b.lt skip /* skip if no cache or icache */
bl __asm_flush_dcache_level
skip:
add x0, x0, #1 /* increment cache level */
cmp x11, x0
b.gt loop_level
mov x0, #0
msr csselr_el1, x0 /* resotre csselr_el1 */
dsb sy
isb
mov lr, x15
finished:
ret
ENDPROC(__asm_flush_dcache_all)
/*
* void __asm_flush_dcache_range(start, end)
*
* clean & invalidate data cache in the range
*
* x0: start address
* x1: end address
*/
ENTRY(__asm_flush_dcache_range)
mrs x3, ctr_el0
lsr x3, x3, #16
and x3, x3, #0xf
mov x2, #4
lsl x2, x2, x3 /* cache line size */
/* x2 <- minimal cache line size in cache system */
sub x3, x2, #1
bic x0, x0, x3
1: dc civac, x0 /* clean & invalidate data or unified cache */
add x0, x0, x2
cmp x0, x1
b.lo 1b
dsb sy
ret
ENDPROC(__asm_flush_dcache_range)
/*
* void __asm_invalidate_icache_all(void)
*
* invalidate all tlb entries.
*/
ENTRY(__asm_invalidate_icache_all)
ic ialluis
isb sy
ret
ENDPROC(__asm_invalidate_icache_all)

219
arch/arm/cpu/armv8/cache_v8.c Normal file
View File

@ -0,0 +1,219 @@
/*
* (C) Copyright 2013
* David Feng <fenghua@phytium.com.cn>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/system.h>
#include <asm/armv8/mmu.h>
DECLARE_GLOBAL_DATA_PTR;
#ifndef CONFIG_SYS_DCACHE_OFF
static void set_pgtable_section(u64 section, u64 memory_type)
{
u64 *page_table = (u64 *)gd->arch.tlb_addr;
u64 value;
value = (section << SECTION_SHIFT) | PMD_TYPE_SECT | PMD_SECT_AF;
value |= PMD_ATTRINDX(memory_type);
page_table[section] = value;
}
/* to activate the MMU we need to set up virtual memory */
static void mmu_setup(void)
{
int i, j, el;
bd_t *bd = gd->bd;
/* Setup an identity-mapping for all spaces */
for (i = 0; i < (PGTABLE_SIZE >> 3); i++)
set_pgtable_section(i, MT_DEVICE_NGNRNE);
/* Setup an identity-mapping for all RAM space */
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
ulong start = bd->bi_dram[i].start;
ulong end = bd->bi_dram[i].start + bd->bi_dram[i].size;
for (j = start >> SECTION_SHIFT;
j < end >> SECTION_SHIFT; j++) {
set_pgtable_section(j, MT_NORMAL);
}
}
/* load TTBR0 */
el = current_el();
if (el == 1)
asm volatile("msr ttbr0_el1, %0"
: : "r" (gd->arch.tlb_addr) : "memory");
else if (el == 2)
asm volatile("msr ttbr0_el2, %0"
: : "r" (gd->arch.tlb_addr) : "memory");
else
asm volatile("msr ttbr0_el3, %0"
: : "r" (gd->arch.tlb_addr) : "memory");
/* enable the mmu */
set_sctlr(get_sctlr() | CR_M);
}
/*
* Performs a invalidation of the entire data cache at all levels
*/
void invalidate_dcache_all(void)
{
__asm_flush_dcache_all();
}
/*
* Performs a clean & invalidation of the entire data cache at all levels
*/
void flush_dcache_all(void)
{
__asm_flush_dcache_all();
}
/*
* Invalidates range in all levels of D-cache/unified cache
*/
void invalidate_dcache_range(unsigned long start, unsigned long stop)
{
__asm_flush_dcache_range(start, stop);
}
/*
* Flush range(clean & invalidate) from all levels of D-cache/unified cache
*/
void flush_dcache_range(unsigned long start, unsigned long stop)
{
__asm_flush_dcache_range(start, stop);
}
void dcache_enable(void)
{
/* The data cache is not active unless the mmu is enabled */
if (!(get_sctlr() & CR_M)) {
invalidate_dcache_all();
__asm_invalidate_tlb_all();
mmu_setup();
}
set_sctlr(get_sctlr() | CR_C);
}
void dcache_disable(void)
{
uint32_t sctlr;
sctlr = get_sctlr();
/* if cache isn't enabled no need to disable */
if (!(sctlr & CR_C))
return;
set_sctlr(sctlr & ~(CR_C|CR_M));
flush_dcache_all();
__asm_invalidate_tlb_all();
}
int dcache_status(void)
{
return (get_sctlr() & CR_C) != 0;
}
#else /* CONFIG_SYS_DCACHE_OFF */
void invalidate_dcache_all(void)
{
}
void flush_dcache_all(void)
{
}
void invalidate_dcache_range(unsigned long start, unsigned long stop)
{
}
void flush_dcache_range(unsigned long start, unsigned long stop)
{
}
void dcache_enable(void)
{
}
void dcache_disable(void)
{
}
int dcache_status(void)
{
return 0;
}
#endif /* CONFIG_SYS_DCACHE_OFF */
#ifndef CONFIG_SYS_ICACHE_OFF
void icache_enable(void)
{
set_sctlr(get_sctlr() | CR_I);
}
void icache_disable(void)
{
set_sctlr(get_sctlr() & ~CR_I);
}
int icache_status(void)
{
return (get_sctlr() & CR_I) != 0;
}
void invalidate_icache_all(void)
{
__asm_invalidate_icache_all();
}
#else /* CONFIG_SYS_ICACHE_OFF */
void icache_enable(void)
{
}
void icache_disable(void)
{
}
int icache_status(void)
{
return 0;
}
void invalidate_icache_all(void)
{
}
#endif /* CONFIG_SYS_ICACHE_OFF */
/*
* Enable dCache & iCache, whether cache is actually enabled
* depend on CONFIG_SYS_DCACHE_OFF and CONFIG_SYS_ICACHE_OFF
*/
void enable_caches(void)
{
icache_enable();
dcache_enable();
}
/*
* Flush range from all levels of d-cache/unified-cache
*/
void flush_cache(unsigned long start, unsigned long size)
{
flush_dcache_range(start, start + size);
}

15
arch/arm/cpu/armv8/config.mk Normal file
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@ -0,0 +1,15 @@
#
# (C) Copyright 2002
# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
#
# SPDX-License-Identifier: GPL-2.0+
#
PLATFORM_RELFLAGS += -fno-common -ffixed-x18
# SEE README.arm-unaligned-accesses
PF_NO_UNALIGNED := $(call cc-option, -mstrict-align)
PLATFORM_NO_UNALIGNED := $(PF_NO_UNALIGNED)
PF_CPPFLAGS_ARMV8 := $(call cc-option, -march=armv8-a)
PLATFORM_CPPFLAGS += $(PF_CPPFLAGS_ARMV8)
PLATFORM_CPPFLAGS += $(PF_NO_UNALIGNED)

43
arch/arm/cpu/armv8/cpu.c Normal file
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@ -0,0 +1,43 @@
/*
* (C) Copyright 2008 Texas Insturments
*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
*
* (C) Copyright 2002
* Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <command.h>
#include <asm/system.h>
#include <linux/compiler.h>
int cleanup_before_linux(void)
{
/*
* this function is called just before we call linux
* it prepares the processor for linux
*
* disable interrupt and turn off caches etc ...
*/
disable_interrupts();
/*
* Turn off I-cache and invalidate it
*/
icache_disable();
invalidate_icache_all();
/*
* turn off D-cache
* dcache_disable() in turn flushes the d-cache and disables MMU
*/
dcache_disable();
invalidate_dcache_all();
return 0;
}

113
arch/arm/cpu/armv8/exceptions.S Normal file
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@ -0,0 +1,113 @@
/*
* (C) Copyright 2013
* David Feng <fenghua@phytium.com.cn>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <asm-offsets.h>
#include <config.h>
#include <version.h>
#include <asm/ptrace.h>
#include <asm/macro.h>
#include <linux/linkage.h>
/*
* Enter Exception.
* This will save the processor state that is ELR/X0~X30
* to the stack frame.
*/
.macro exception_entry
stp x29, x30, [sp, #-16]!
stp x27, x28, [sp, #-16]!
stp x25, x26, [sp, #-16]!
stp x23, x24, [sp, #-16]!
stp x21, x22, [sp, #-16]!
stp x19, x20, [sp, #-16]!
stp x17, x18, [sp, #-16]!
stp x15, x16, [sp, #-16]!
stp x13, x14, [sp, #-16]!
stp x11, x12, [sp, #-16]!
stp x9, x10, [sp, #-16]!
stp x7, x8, [sp, #-16]!
stp x5, x6, [sp, #-16]!
stp x3, x4, [sp, #-16]!
stp x1, x2, [sp, #-16]!
/* Could be running at EL3/EL2/EL1 */
switch_el x11, 3f, 2f, 1f
3: mrs x1, esr_el3
mrs x2, elr_el3
b 0f
2: mrs x1, esr_el2
mrs x2, elr_el2
b 0f
1: mrs x1, esr_el1
mrs x2, elr_el1
0:
stp x2, x0, [sp, #-16]!
mov x0, sp
.endm
/*
* Exception vectors.
*/
.align 11
.globl vectors
vectors:
.align 7
b _do_bad_sync /* Current EL Synchronous Thread */
.align 7
b _do_bad_irq /* Current EL IRQ Thread */
.align 7
b _do_bad_fiq /* Current EL FIQ Thread */
.align 7
b _do_bad_error /* Current EL Error Thread */
.align 7
b _do_sync /* Current EL Synchronous Handler */
.align 7
b _do_irq /* Current EL IRQ Handler */
.align 7
b _do_fiq /* Current EL FIQ Handler */
.align 7
b _do_error /* Current EL Error Handler */
_do_bad_sync:
exception_entry
bl do_bad_sync
_do_bad_irq:
exception_entry
bl do_bad_irq
_do_bad_fiq:
exception_entry
bl do_bad_fiq
_do_bad_error:
exception_entry
bl do_bad_error
_do_sync:
exception_entry
bl do_sync
_do_irq:
exception_entry
bl do_irq
_do_fiq:
exception_entry
bl do_fiq
_do_error:
exception_entry
bl do_error

31
arch/arm/cpu/armv8/generic_timer.c Normal file
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@ -0,0 +1,31 @@
/*
* (C) Copyright 2013
* David Feng <fenghua@phytium.com.cn>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <command.h>
#include <asm/system.h>
/*
* Generic timer implementation of get_tbclk()
*/
unsigned long get_tbclk(void)
{
unsigned long cntfrq;
asm volatile("mrs %0, cntfrq_el0" : "=r" (cntfrq));
return cntfrq;
}
/*
* Generic timer implementation of timer_read_counter()
*/
unsigned long timer_read_counter(void)
{
unsigned long cntpct;
isb();
asm volatile("mrs %0, cntpct_el0" : "=r" (cntpct));
return cntpct;
}

106
arch/arm/cpu/armv8/gic.S Normal file
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@ -0,0 +1,106 @@
/*
* GIC Initialization Routines.
*
* (C) Copyright 2013
* David Feng <fenghua@phytium.com.cn>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <asm-offsets.h>
#include <config.h>
#include <linux/linkage.h>
#include <asm/macro.h>
#include <asm/gic.h>
/*************************************************************************
*
* void gic_init(void) __attribute__((weak));
*
* Currently, this routine only initialize secure copy of GIC
* with Security Extensions at EL3.
*
*************************************************************************/
WEAK(gic_init)
branch_if_slave x0, 2f
/* Initialize Distributor and SPIs */
ldr x1, =GICD_BASE
mov w0, #0x3 /* EnableGrp0 | EnableGrp1 */
str w0, [x1, GICD_CTLR] /* Secure GICD_CTLR */
ldr w0, [x1, GICD_TYPER]
and w2, w0, #0x1f /* ITLinesNumber */
cbz w2, 2f /* No SPIs */
add x1, x1, (GICD_IGROUPRn + 4)
mov w0, #~0 /* Config SPIs as Grp1 */
1: str w0, [x1], #0x4
sub w2, w2, #0x1
cbnz w2, 1b
/* Initialize SGIs and PPIs */
2: ldr x1, =GICD_BASE
mov w0, #~0 /* Config SGIs and PPIs as Grp1 */
str w0, [x1, GICD_IGROUPRn] /* GICD_IGROUPR0 */
mov w0, #0x1 /* Enable SGI 0 */
str w0, [x1, GICD_ISENABLERn]
/* Initialize Cpu Interface */
ldr x1, =GICC_BASE
mov w0, #0x1e7 /* Disable IRQ/FIQ Bypass & */
/* Enable Ack Group1 Interrupt & */
/* EnableGrp0 & EnableGrp1 */
str w0, [x1, GICC_CTLR] /* Secure GICC_CTLR */
mov w0, #0x1 << 7 /* Non-Secure access to GICC_PMR */
str w0, [x1, GICC_PMR]
ret
ENDPROC(gic_init)
/*************************************************************************
*
* void gic_send_sgi(u64 sgi) __attribute__((weak));
*
*************************************************************************/
WEAK(gic_send_sgi)
ldr x1, =GICD_BASE
mov w2, #0x8000
movk w2, #0x100, lsl #16
orr w2, w2, w0
str w2, [x1, GICD_SGIR]
ret
ENDPROC(gic_send_sgi)
/*************************************************************************
*
* void wait_for_wakeup(void) __attribute__((weak));
*
* Wait for SGI 0 from master.
*
*************************************************************************/
WEAK(wait_for_wakeup)
ldr x1, =GICC_BASE
0: wfi
ldr w0, [x1, GICC_AIAR]
str w0, [x1, GICC_AEOIR]
cbnz w0, 0b
ret
ENDPROC(wait_for_wakeup)
/*************************************************************************
*
* void smp_kick_all_cpus(void) __attribute__((weak));
*
*************************************************************************/
WEAK(smp_kick_all_cpus)
/* Kick secondary cpus up by SGI 0 interrupt */
mov x0, xzr /* SGI 0 */
mov x29, lr /* Save LR */
bl gic_send_sgi
mov lr, x29 /* Restore LR */
ret
ENDPROC(smp_kick_all_cpus)

164
arch/arm/cpu/armv8/start.S Normal file
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@ -0,0 +1,164 @@
/*
* (C) Copyright 2013
* David Feng <fenghua@phytium.com.cn>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <asm-offsets.h>
#include <config.h>
#include <version.h>
#include <linux/linkage.h>
#include <asm/macro.h>
#include <asm/armv8/mmu.h>
/*************************************************************************
*
* Startup Code (reset vector)
*
*************************************************************************/
.globl _start
_start:
b reset
.align 3
.globl _TEXT_BASE
_TEXT_BASE:
.quad CONFIG_SYS_TEXT_BASE
/*
* These are defined in the linker script.
*/
.globl _end_ofs
_end_ofs:
.quad _end - _start
.globl _bss_start_ofs
_bss_start_ofs:
.quad __bss_start - _start
.globl _bss_end_ofs
_bss_end_ofs:
.quad __bss_end - _start
reset:
/*
* Could be EL3/EL2/EL1, Initial State:
* Little Endian, MMU Disabled, i/dCache Disabled
*/
adr x0, vectors
switch_el x1, 3f, 2f, 1f
3: msr vbar_el3, x0
msr cptr_el3, xzr /* Enable FP/SIMD */
ldr x0, =COUNTER_FREQUENCY
msr cntfrq_el0, x0 /* Initialize CNTFRQ */
b 0f
2: msr vbar_el2, x0
mov x0, #0x33ff
msr cptr_el2, x0 /* Enable FP/SIMD */
b 0f
1: msr vbar_el1, x0
mov x0, #3 << 20
msr cpacr_el1, x0 /* Enable FP/SIMD */
0:
/* Cache/BPB/TLB Invalidate */
bl __asm_flush_dcache_all /* dCache clean&invalidate */
bl __asm_invalidate_icache_all /* iCache invalidate */
bl __asm_invalidate_tlb_all /* invalidate TLBs */
/* Processor specific initialization */
bl lowlevel_init
branch_if_master x0, x1, master_cpu
/*
* Slave CPUs
*/
slave_cpu:
wfe
ldr x1, =CPU_RELEASE_ADDR
ldr x0, [x1]
cbz x0, slave_cpu
br x0 /* branch to the given address */
/*
* Master CPU
*/
master_cpu:
bl _main
/*-----------------------------------------------------------------------*/
WEAK(lowlevel_init)
/* Initialize GIC Secure Bank Status */
mov x29, lr /* Save LR */
bl gic_init
branch_if_master x0, x1, 1f
/*
* Slave should wait for master clearing spin table.
* This sync prevent salves observing incorrect
* value of spin table and jumping to wrong place.
*/
bl wait_for_wakeup
/*
* All processors will enter EL2 and optionally EL1.
*/
bl armv8_switch_to_el2
#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
bl armv8_switch_to_el1
#endif
1:
mov lr, x29 /* Restore LR */
ret
ENDPROC(lowlevel_init)
/*-----------------------------------------------------------------------*/
ENTRY(c_runtime_cpu_setup)
/* If I-cache is enabled invalidate it */
#ifndef CONFIG_SYS_ICACHE_OFF
ic iallu /* I+BTB cache invalidate */
isb sy
#endif
#ifndef CONFIG_SYS_DCACHE_OFF
/*
* Setup MAIR and TCR.
*/
ldr x0, =MEMORY_ATTRIBUTES
ldr x1, =TCR_FLAGS
switch_el x2, 3f, 2f, 1f
3: orr x1, x1, TCR_EL3_IPS_BITS
msr mair_el3, x0
msr tcr_el3, x1
b 0f
2: orr x1, x1, TCR_EL2_IPS_BITS
msr mair_el2, x0
msr tcr_el2, x1
b 0f
1: orr x1, x1, TCR_EL1_IPS_BITS
msr mair_el1, x0
msr tcr_el1, x1
0:
#endif
/* Relocate vBAR */
adr x0, vectors
switch_el x1, 3f, 2f, 1f
3: msr vbar_el3, x0
b 0f
2: msr vbar_el2, x0
b 0f
1: msr vbar_el1, x0
0:
ret
ENDPROC(c_runtime_cpu_setup)

34
arch/arm/cpu/armv8/tlb.S Normal file
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@ -0,0 +1,34 @@
/*
* (C) Copyright 2013
* David Feng <fenghua@phytium.com.cn>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <asm-offsets.h>
#include <config.h>
#include <version.h>
#include <linux/linkage.h>
#include <asm/macro.h>
/*
* void __asm_invalidate_tlb_all(void)
*
* invalidate all tlb entries.
*/
ENTRY(__asm_invalidate_tlb_all)
switch_el x9, 3f, 2f, 1f
3: tlbi alle3
dsb sy
isb
b 0f
2: tlbi alle2
dsb sy
isb
b 0f
1: tlbi vmalle1
dsb sy
isb
0:
ret
ENDPROC(__asm_invalidate_tlb_all)

83
arch/arm/cpu/armv8/transition.S Normal file
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@ -0,0 +1,83 @@
/*
* (C) Copyright 2013
* David Feng <fenghua@phytium.com.cn>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <asm-offsets.h>
#include <config.h>
#include <version.h>
#include <linux/linkage.h>
#include <asm/macro.h>
ENTRY(armv8_switch_to_el2)
switch_el x0, 1f, 0f, 0f
0: ret
1:
mov x0, #0x5b1 /* Non-secure EL0/EL1 | HVC | 64bit EL2 */
msr scr_el3, x0
msr cptr_el3, xzr /* Disable coprocessor traps to EL3 */
mov x0, #0x33ff
msr cptr_el2, x0 /* Disable coprocessor traps to EL2 */
/* Initialize SCTLR_EL2 */
msr sctlr_el2, xzr
/* Return to the EL2_SP2 mode from EL3 */
mov x0, sp
msr sp_el2, x0 /* Migrate SP */
mrs x0, vbar_el3
msr vbar_el2, x0 /* Migrate VBAR */
mov x0, #0x3c9
msr spsr_el3, x0 /* EL2_SP2 | D | A | I | F */
msr elr_el3, lr
eret
ENDPROC(armv8_switch_to_el2)
ENTRY(armv8_switch_to_el1)
switch_el x0, 0f, 1f, 0f
0: ret
1:
/* Initialize Generic Timers */
mrs x0, cnthctl_el2
orr x0, x0, #0x3 /* Enable EL1 access to timers */
msr cnthctl_el2, x0
msr cntvoff_el2, x0
mrs x0, cntkctl_el1
orr x0, x0, #0x3 /* Enable EL0 access to timers */
msr cntkctl_el1, x0
/* Initilize MPID/MPIDR registers */
mrs x0, midr_el1
mrs x1, mpidr_el1
msr vpidr_el2, x0
msr vmpidr_el2, x1
/* Disable coprocessor traps */
mov x0, #0x33ff
msr cptr_el2, x0 /* Disable coprocessor traps to EL2 */
msr hstr_el2, xzr /* Disable coprocessor traps to EL2 */
mov x0, #3 << 20
msr cpacr_el1, x0 /* Enable FP/SIMD at EL1 */
/* Initialize HCR_EL2 */
mov x0, #(1 << 31) /* 64bit EL1 */
orr x0, x0, #(1 << 29) /* Disable HVC */
msr hcr_el2, x0
/* SCTLR_EL1 initialization */
mov x0, #0x0800
movk x0, #0x30d0, lsl #16
msr sctlr_el1, x0
/* Return to the EL1_SP1 mode from EL2 */
mov x0, sp
msr sp_el1, x0 /* Migrate SP */
mrs x0, vbar_el2
msr vbar_el1, x0 /* Migrate VBAR */
mov x0, #0x3c5
msr spsr_el2, x0 /* EL1_SP1 | D | A | I | F */
msr elr_el2, lr
eret
ENDPROC(armv8_switch_to_el1)

89
arch/arm/cpu/armv8/u-boot.lds Normal file
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@ -0,0 +1,89 @@
/*
* (C) Copyright 2013
* David Feng <fenghua@phytium.com.cn>
*
* (C) Copyright 2002
* Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
*
* SPDX-License-Identifier: GPL-2.0+
*/
OUTPUT_FORMAT("elf64-littleaarch64", "elf64-littleaarch64", "elf64-littleaarch64")
OUTPUT_ARCH(aarch64)
ENTRY(_start)
SECTIONS
{
. = 0x00000000;
. = ALIGN(8);
.text :
{
*(.__image_copy_start)
CPUDIR/start.o (.text*)
*(.text*)
}
. = ALIGN(8);
.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
. = ALIGN(8);
.data : {
*(.data*)
}
. = ALIGN(8);
. = .;
. = ALIGN(8);
.u_boot_list : {
KEEP(*(SORT(.u_boot_list*)));
}
. = ALIGN(8);
.image_copy_end :
{
*(.__image_copy_end)
}
. = ALIGN(8);
.rel_dyn_start :
{
*(.__rel_dyn_start)
}
.rela.dyn : {
*(.rela*)
}
.rel_dyn_end :
{
*(.__rel_dyn_end)
}
_end = .;
. = ALIGN(8);
.bss_start : {
KEEP(*(.__bss_start));
}
.bss : {
*(.bss*)
. = ALIGN(8);
}
.bss_end : {
KEEP(*(.__bss_end));
}
/DISCARD/ : { *(.dynsym) }
/DISCARD/ : { *(.dynstr*) }
/DISCARD/ : { *(.dynamic*) }
/DISCARD/ : { *(.plt*) }
/DISCARD/ : { *(.interp*) }
/DISCARD/ : { *(.gnu*) }
}

1
arch/arm/cpu/pxa/pxa2xx.c
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@ -279,6 +279,7 @@ void reset_cpu(ulong ignored)
tmp = readl(OSCR);
tmp += 0x1000;
writel(tmp, OSMR3);
writel(MDREFR_SLFRSH, MDREFR);
for (;;)
;

1
arch/arm/cpu/tegra-common/ap.c
View File

@ -71,6 +71,7 @@ int tegra_get_chip_sku(void)
switch (sku_id) {
case SKU_ID_T33:
case SKU_ID_T30:
case SKU_ID_TM30MQS_P_A3:
return TEGRA_SOC_T30;
}
break;

198
arch/arm/dts/exynos5.dtsi Normal file
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@ -0,0 +1,198 @@
/*
* Copyright (c) 2013 The Chromium OS Authors
* SAMSUNG EXYNOS5 SoC device tree source
*
* SPDX-License-Identifier: GPL-2.0+
*/
/include/ "skeleton.dtsi"
/ {
compatible = "samsung,exynos5";
sromc@12250000 {
compatible = "samsung,exynos-sromc";
reg = <0x12250000 0x20>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c@12c60000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x12C60000 0x100>;
interrupts = <0 56 0>;
};
i2c@12c70000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x12C70000 0x100>;
interrupts = <0 57 0>;
};
i2c@12c80000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x12C80000 0x100>;
interrupts = <0 58 0>;
};
i2c@12c90000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x12C90000 0x100>;
interrupts = <0 59 0>;
};
spi@12d20000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,exynos-spi";
reg = <0x12d20000 0x30>;
interrupts = <0 68 0>;
};
spi@12d30000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,exynos-spi";
reg = <0x12d30000 0x30>;
interrupts = <0 69 0>;
};
spi@12d40000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,exynos-spi";
reg = <0x12d40000 0x30>;
clock-frequency = <50000000>;
interrupts = <0 70 0>;
};
spi@131a0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,exynos-spi";
reg = <0x131a0000 0x30>;
interrupts = <0 129 0>;
};
spi@131b0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,exynos-spi";
reg = <0x131b0000 0x30>;
interrupts = <0 130 0>;
};
ehci@12110000 {
compatible = "samsung,exynos-ehci";
reg = <0x12110000 0x100>;
#address-cells = <1>;
#size-cells = <1>;
phy {
compatible = "samsung,exynos-usb-phy";
reg = <0x12130000 0x100>;
};
};
tmu@10060000 {
compatible = "samsung,exynos-tmu";
reg = <0x10060000 0x10000>;
};
fimd@14400000 {
compatible = "samsung,exynos-fimd";
reg = <0x14400000 0x10000>;
#address-cells = <1>;
#size-cells = <1>;
};
dp@145b0000 {
compatible = "samsung,exynos5-dp";
reg = <0x145b0000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
};
xhci0: xhci@12000000 {
compatible = "samsung,exynos5250-xhci";
reg = <0x12000000 0x10000>;
#address-cells = <1>;
#size-cells = <1>;
phy {
compatible = "samsung,exynos5250-usb3-phy";
reg = <0x12100000 0x100>;
};
};
mmc@12200000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,exynos5250-dwmmc";
reg = <0x12200000 0x1000>;
interrupts = <0 75 0>;
};
mmc@12210000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,exynos5250-dwmmc";
reg = <0x12210000 0x1000>;
interrupts = <0 76 0>;
};
mmc@12220000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,exynos5250-dwmmc";
reg = <0x12220000 0x1000>;
interrupts = <0 77 0>;
};
mmc@12230000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,exynos5250-dwmmc";
reg = <0x12230000 0x1000>;
interrupts = <0 78 0>;
};
serial@12C00000 {
compatible = "samsung,exynos4210-uart";
reg = <0x12C00000 0x100>;
interrupts = <0 51 0>;
id = <0>;
};
serial@12C10000 {
compatible = "samsung,exynos4210-uart";
reg = <0x12C10000 0x100>;
interrupts = <0 52 0>;
id = <1>;
};
serial@12C20000 {
compatible = "samsung,exynos4210-uart";
reg = <0x12C20000 0x100>;
interrupts = <0 53 0>;
id = <2>;
};
serial@12C30000 {
compatible = "samsung,exynos4210-uart";
reg = <0x12C30000 0x100>;
interrupts = <0 54 0>;
id = <3>;
};
gpio: gpio {
};
};

194
arch/arm/dts/exynos5250.dtsi
View File

@ -1,66 +1,13 @@
/*
* (C) Copyright 2012 SAMSUNG Electronics
* SAMSUNG EXYNOS5250 SoC device tree source
*
* Copyright (c) 2012 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* SAMSUNG EXYNOS5250 SoC device nodes are listed in this file.
* EXYNOS5250 based board files can include this file and provide
* values for board specfic bindings.
*
* Note: This file does not include device nodes for all the controllers in
* EXYNOS5250 SoC. As device tree coverage for EXYNOS5250 increases,
* additional nodes can be added to this file.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
* SPDX-License-Identifier: GPL-2.0+
*/
/include/ "skeleton.dtsi"
/include/ "exynos5.dtsi"
/ {
compatible = "samsung,exynos5250";
sromc@12250000 {
compatible = "samsung,exynos-sromc";
reg = <0x12250000 0x20>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c@12c60000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x12C60000 0x100>;
interrupts = <0 56 0>;
};
i2c@12c70000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x12C70000 0x100>;
interrupts = <0 57 0>;
};
i2c@12c80000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x12C80000 0x100>;
interrupts = <0 58 0>;
};
i2c@12c90000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x12C90000 0x100>;
interrupts = <0 59 0>;
};
i2c@12ca0000 {
#address-cells = <1>;
#size-cells = <0>;
@ -117,46 +64,6 @@
samsung,i2s-id = <1>;
};
spi@12d20000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,exynos-spi";
reg = <0x12d20000 0x30>;
interrupts = <0 68 0>;
};
spi@12d30000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,exynos-spi";
reg = <0x12d30000 0x30>;
interrupts = <0 69 0>;
};
spi@12d40000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,exynos-spi";
reg = <0x12d40000 0x30>;
clock-frequency = <50000000>;
interrupts = <0 70 0>;
};
spi@131a0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,exynos-spi";
reg = <0x131a0000 0x30>;
interrupts = <0 129 0>;
};
spi@131b0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,exynos-spi";
reg = <0x131b0000 0x30>;
interrupts = <0 130 0>;
};
xhci@12000000 {
compatible = "samsung,exynos5250-xhci";
@ -170,97 +77,4 @@
};
};
ehci@12110000 {
compatible = "samsung,exynos-ehci";
reg = <0x12110000 0x100>;
#address-cells = <1>;
#size-cells = <1>;
phy {
compatible = "samsung,exynos-usb-phy";
reg = <0x12130000 0x100>;
};
};
tmu@10060000 {
compatible = "samsung,exynos-tmu";
reg = <0x10060000 0x10000>;
};
fimd@14400000 {
compatible = "samsung,exynos-fimd";
reg = <0x14400000 0x10000>;
#address-cells = <1>;
#size-cells = <1>;
};
dp@145b0000 {
compatible = "samsung,exynos5-dp";
reg = <0x145b0000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
};
mmc@12200000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,exynos5250-dwmmc";
reg = <0x12200000 0x1000>;
interrupts = <0 75 0>;
};
mmc@12210000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,exynos5250-dwmmc";
reg = <0x12210000 0x1000>;
interrupts = <0 76 0>;
};
mmc@12220000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,exynos5250-dwmmc";
reg = <0x12220000 0x1000>;
interrupts = <0 77 0>;
};
mmc@12230000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,exynos5250-dwmmc";
reg = <0x12230000 0x1000>;
interrupts = <0 78 0>;
};
serial@12C00000 {
compatible = "samsung,exynos4210-uart";
reg = <0x12C00000 0x100>;
interrupts = <0 51 0>;
id = <0>;
};
serial@12C10000 {
compatible = "samsung,exynos4210-uart";
reg = <0x12C10000 0x100>;
interrupts = <0 52 0>;
id = <1>;
};
serial@12C20000 {
compatible = "samsung,exynos4210-uart";
reg = <0x12C20000 0x100>;
interrupts = <0 53 0>;
id = <2>;
};
serial@12C30000 {
compatible = "samsung,exynos4210-uart";
reg = <0x12C30000 0x100>;
interrupts = <0 54 0>;
id = <3>;
};
gpio: gpio {
};
};

70
arch/arm/dts/exynos5420.dtsi Normal file
View File

@ -0,0 +1,70 @@
/*
* (C) Copyright 2013 SAMSUNG Electronics
* SAMSUNG EXYNOS5420 SoC device tree source
*
* SPDX-License-Identifier: GPL-2.0+
*/
/include/ "exynos5.dtsi"
/ {
config {
machine-arch-id = <4151>;
};
i2c@12ca0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,exynos5-hsi2c";
reg = <0x12CA0000 0x100>;
interrupts = <0 60 0>;
};
i2c@12cb0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,exynos5-hsi2c";
reg = <0x12CB0000 0x100>;
interrupts = <0 61 0>;
};
i2c@12cc0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,exynos5-hsi2c";
reg = <0x12CC0000 0x100>;
interrupts = <0 62 0>;
};
i2c@12cd0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,exynos5-hsi2c";
reg = <0x12CD0000 0x100>;
interrupts = <0 63 0>;
};
i2c@12e00000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,exynos5-hsi2c";
reg = <0x12E00000 0x100>;
interrupts = <0 87 0>;
};
i2c@12e10000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,exynos5-hsi2c";
reg = <0x12E10000 0x100>;
interrupts = <0 88 0>;
};
i2c@12e20000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,exynos5-hsi2c";
reg = <0x12E20000 0x100>;
interrupts = <0 203 0>;
};
};

13
arch/arm/dts/zynq-7000.dtsi Normal file
View File

@ -0,0 +1,13 @@
/*
* Xilinx Zynq 7000 DTSI
* Describes the hardware common to all Zynq 7000-based boards.
*
* Copyright (C) 2013 Xilinx, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
/include/ "skeleton.dtsi"
/ {
compatible = "xlnx,zynq-7000";
};

3
arch/arm/imx-common/Makefile
View File

@ -17,6 +17,9 @@ endif
ifeq ($(SOC),$(filter $(SOC),mx6 mxs))
obj-y += misc.o
endif
ifeq ($(SOC),$(filter $(SOC),mx6))
obj-$(CONFIG_CMD_SATA) += sata.o
endif
obj-$(CONFIG_CMD_BMODE) += cmd_bmode.o
obj-$(CONFIG_CMD_HDMIDETECT) += cmd_hdmidet.o

4
arch/arm/imx-common/cpu.c
View File

@ -51,9 +51,9 @@ char *get_reset_cause(void)
#if defined(CONFIG_MX53) || defined(CONFIG_MX6)
#if defined(CONFIG_MX53)
#define MEMCTL_BASE ESDCTL_BASE_ADDR;
#define MEMCTL_BASE ESDCTL_BASE_ADDR
#else
#define MEMCTL_BASE MMDC_P0_BASE_ADDR;
#define MEMCTL_BASE MMDC_P0_BASE_ADDR
#endif
static const unsigned char col_lookup[] = {9, 10, 11, 8, 12, 9, 9, 9};
static const unsigned char bank_lookup[] = {3, 2};

34
arch/arm/imx-common/sata.c Normal file
View File

@ -0,0 +1,34 @@
/*
* Copyright 2011 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <asm/imx-common/iomux-v3.h>
#include <asm/arch/iomux.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
int setup_sata(void)
{
struct iomuxc_base_regs *const iomuxc_regs
= (struct iomuxc_base_regs *)IOMUXC_BASE_ADDR;
int ret = enable_sata_clock();
if (ret)
return ret;
clrsetbits_le32(&iomuxc_regs->gpr[13],
IOMUXC_GPR13_SATA_MASK,
IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB
|IOMUXC_GPR13_SATA_PHY_7_SATA2M
|IOMUXC_GPR13_SATA_SPEED_3G
|(3<<IOMUXC_GPR13_SATA_PHY_6_SHIFT)
|IOMUXC_GPR13_SATA_SATA_PHY_5_SS_DISABLED
|IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_9_16
|IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P00_DB
|IOMUXC_GPR13_SATA_PHY_2_TX_1P104V
|IOMUXC_GPR13_SATA_PHY_1_SLOW);
return 0;
}

7
arch/arm/include/asm/arch-am33xx/clock.h
View File

@ -98,13 +98,12 @@ extern const struct dpll_regs dpll_mpu_regs;
extern const struct dpll_regs dpll_core_regs;
extern const struct dpll_regs dpll_per_regs;
extern const struct dpll_regs dpll_ddr_regs;
extern const struct dpll_params dpll_mpu;
extern const struct dpll_params dpll_core;
extern const struct dpll_params dpll_per;
extern const struct dpll_params dpll_ddr;
extern struct cm_wkuppll *const cmwkup;
const struct dpll_params *get_dpll_mpu_params(void);
const struct dpll_params *get_dpll_core_params(void);
const struct dpll_params *get_dpll_per_params(void);
const struct dpll_params *get_dpll_ddr_params(void);
void do_setup_dpll(const struct dpll_regs *, const struct dpll_params *);
void prcm_init(void);

3
arch/arm/include/asm/arch-am33xx/clocks_am33xx.h
View File

@ -28,6 +28,9 @@
#define UART_CLK_RUNNING_MASK 0x1
#define UART_SMART_IDLE_EN (0x1 << 0x3)
#define CM_DLL_CTRL_NO_OVERRIDE 0x0
#define CM_DLL_READYST 0x4
extern void enable_dmm_clocks(void);
extern const struct dpll_params dpll_core_opp100;
extern struct dpll_params dpll_mpu_opp100;

26
arch/arm/include/asm/arch-am33xx/cpu.h
View File

@ -237,6 +237,14 @@ struct cm_perpll {
unsigned int cpswclkstctrl; /* offset 0x144 */
unsigned int lcdcclkstctrl; /* offset 0x148 */
};
/* Encapsulating Display pll registers */
struct cm_dpll {
unsigned int resv1[2];
unsigned int clktimer2clk; /* offset 0x08 */
unsigned int resv2[10];
unsigned int clklcdcpixelclk; /* offset 0x34 */
};
#else
/* Encapsulating core pll registers */
struct cm_wkuppll {
@ -392,16 +400,18 @@ struct cm_perpll {
unsigned int resv40[7];
unsigned int cpgmac0clkctrl; /* offset 0xB20 */
};
#endif /* CONFIG_AM43XX */
/* Encapsulating Display pll registers */
struct cm_dpll {
unsigned int resv1[2];
unsigned int clktimer2clk; /* offset 0x08 */
unsigned int resv2[10];
unsigned int clklcdcpixelclk; /* offset 0x34 */
struct cm_device_inst {
unsigned int cm_clkout1_ctrl;
unsigned int cm_dll_ctrl;
};
struct cm_dpll {
unsigned int resv1;
unsigned int clktimer2clk; /* offset 0x04 */
};
#endif /* CONFIG_AM43XX */
/* Control Module RTC registers */
struct cm_rtc {
unsigned int rtcclkctrl; /* offset 0x0 */
@ -475,6 +485,8 @@ struct ctrl_stat {
unsigned int statusreg; /* ofset 0x40 */
unsigned int resv2[51];
unsigned int secure_emif_sdram_config; /* offset 0x0110 */
unsigned int resv3[319];
unsigned int dev_attr;
};
/* AM33XX GPIO registers */

41
arch/arm/include/asm/arch-am33xx/ddr_defs.h
View File

@ -18,7 +18,11 @@
#define VTP_CTRL_READY (0x1 << 5)
#define VTP_CTRL_ENABLE (0x1 << 6)
#define VTP_CTRL_START_EN (0x1)
#ifdef CONFIG_AM43XX
#define DDR_CKE_CTRL_NORMAL 0x3
#else
#define DDR_CKE_CTRL_NORMAL 0x1
#endif
#define PHY_EN_DYN_PWRDN (0x1 << 20)
/* Micron MT47H128M16RT-25E */
@ -124,6 +128,22 @@
#define K4B2G1646EBIH9_PHY_WR_DATA 0x76
#define K4B2G1646EBIH9_IOCTRL_VALUE 0x18B
#define LPDDR2_ADDRCTRL_IOCTRL_VALUE 0x294
#define LPDDR2_ADDRCTRL_WD0_IOCTRL_VALUE 0x00000000
#define LPDDR2_ADDRCTRL_WD1_IOCTRL_VALUE 0x00000000
#define LPDDR2_DATA0_IOCTRL_VALUE 0x20000294
#define LPDDR2_DATA1_IOCTRL_VALUE 0x20000294
#define LPDDR2_DATA2_IOCTRL_VALUE 0x20000294
#define LPDDR2_DATA3_IOCTRL_VALUE 0x20000294
#define DDR3_ADDRCTRL_WD0_IOCTRL_VALUE 0x00000000
#define DDR3_ADDRCTRL_WD1_IOCTRL_VALUE 0x00000000
#define DDR3_ADDRCTRL_IOCTRL_VALUE 0x84
#define DDR3_DATA0_IOCTRL_VALUE 0x84
#define DDR3_DATA1_IOCTRL_VALUE 0x84
#define DDR3_DATA2_IOCTRL_VALUE 0x84
#define DDR3_DATA3_IOCTRL_VALUE 0x84
/**
* Configure DMM
*/
@ -133,6 +153,7 @@ void config_dmm(const struct dmm_lisa_map_regs *regs);
* Configure SDRAM
*/
void config_sdram(const struct emif_regs *regs, int nr);
void config_sdram_emif4d5(const struct emif_regs *regs, int nr);
/**
* Set SDRAM timings
@ -278,12 +299,27 @@ struct ddr_cmdtctrl {
unsigned int resv2[12];
unsigned int dt0ioctl;
unsigned int dt1ioctl;
unsigned int dt2ioctrl;
unsigned int dt3ioctrl;
unsigned int resv3[4];
unsigned int emif_sdram_config_ext;
};
struct ctrl_ioregs {
unsigned int cm0ioctl;
unsigned int cm1ioctl;
unsigned int cm2ioctl;
unsigned int dt0ioctl;
unsigned int dt1ioctl;
unsigned int dt2ioctrl;
unsigned int dt3ioctrl;
unsigned int emif_sdram_config_ext;
};
/**
* Configure DDR io control registers
*/
void config_io_ctrl(unsigned long val);
void config_io_ctrl(const struct ctrl_ioregs *ioregs);
struct ddr_ctrl {
unsigned int ddrioctrl;
@ -291,8 +327,9 @@ struct ddr_ctrl {
unsigned int ddrckectrl;
};
void config_ddr(unsigned int pll, unsigned int ioctrl,
void config_ddr(unsigned int pll, const struct ctrl_ioregs *ioregs,
const struct ddr_data *data, const struct cmd_control *ctrl,
const struct emif_regs *regs, int nr);
void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size);
#endif /* _DDR_DEFS_H */

12
arch/arm/include/asm/arch-am33xx/gpio.h
View File

@ -13,4 +13,16 @@
#define AM33XX_GPIO2_BASE 0x481AC000
#define AM33XX_GPIO3_BASE 0x481AE000
#define GPIO_22 22
/* GPIO CTRL register */
#define GPIO_CTRL_DISABLEMODULE_SHIFT 0
#define GPIO_CTRL_DISABLEMODULE_MASK (1 << 0)
#define GPIO_CTRL_ENABLEMODULE GPIO_CTRL_DISABLEMODULE_MASK
/* GPIO OUTPUT ENABLE register */
#define GPIO_OE_ENABLE(x) (1 << x)
/* GPIO SETDATAOUT register */
#define GPIO_SETDATAOUT(x) (1 << x)
#endif /* _GPIO_AM33xx_H */

7
arch/arm/include/asm/arch-am33xx/hardware.h
View File

@ -48,13 +48,6 @@
#define EMIF4_0_CFG_BASE 0x4C000000
#define EMIF4_1_CFG_BASE 0x4D000000
/* PLL related registers */
#define CM_DPLL 0x44E00500
#define CM_DEVICE 0x44E00700
#define CM_RTC 0x44E00800
#define CM_CEFUSE 0x44E00A00
#define PRM_DEVICE 0x44E00F00
/* DDR Base address */
#define DDR_CTRL_ADDR 0x44E10E04
#define DDR_CONTROL_BASE_ADDR 0x44E11404

2
arch/arm/include/asm/arch-am33xx/hardware_am33xx.h
View File

@ -30,6 +30,8 @@
#define PRCM_BASE 0x44E00000
#define CM_PER 0x44E00000
#define CM_WKUP 0x44E00400
#define CM_DPLL 0x44E00500
#define CM_RTC 0x44E00800
#define PRM_RSTCTRL (PRCM_BASE + 0x0F00)
#define PRM_RSTST (PRM_RSTCTRL + 8)

20
arch/arm/include/asm/arch-am33xx/hardware_am43xx.h
View File

@ -30,6 +30,8 @@
#define PRCM_BASE 0x44DF0000
#define CM_WKUP 0x44DF2800
#define CM_PER 0x44DF8800
#define CM_DPLL 0x44DF4200
#define CM_RTC 0x44DF8500
#define PRM_RSTCTRL (PRCM_BASE + 0x4000)
#define PRM_RSTST (PRM_RSTCTRL + 4)
@ -54,11 +56,25 @@
/* USB Clock Control */
#define PRM_PER_USB_OTG_SS0_CLKCTRL (CM_PER + 0x260)
#define PRM_PER_USB_OTG_SS1_CLKCTRL (CM_PER + 0x268)
#define USBOTGSSX_CLKCTRL_MODULE_EN (1 << 2)
#define USBOTGSSX_CLKCTRL_MODULE_EN (1 << 1)
#define USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960 (1 << 8)
#define PRM_PER_USBPHYOCP2SCP0_CLKCTRL (CM_PER + 0x5b8)
#define PRM_PER_USBPHYOCP2SCP1_CLKCTRL (CM_PER + 0x5c0)
#define USBPHYOCPSCP_MODULE_EN (1 << 2)
#define USBPHYOCPSCP_MODULE_EN (1 << 1)
#define CM_DEVICE_INST 0x44df4100
/* Control status register */
#define CTRL_CRYSTAL_FREQ_SRC_MASK (1 << 31)
#define CTRL_CRYSTAL_FREQ_SRC_SHIFT 31
#define CTRL_CRYSTAL_FREQ_SELECTION_MASK (0x3 << 29)
#define CTRL_CRYSTAL_FREQ_SELECTION_SHIFT 29
#define CTRL_SYSBOOT_15_14_MASK (0x3 << 22)
#define CTRL_SYSBOOT_15_14_SHIFT 22
#define CTRL_CRYSTAL_FREQ_SRC_SYSBOOT 0x0
#define CTRL_CRYSTAL_FREQ_SRC_EFUSE 0x1
#define NUM_CRYSTAL_FREQ 0x4
#endif /* __AM43XX_HARDWARE_AM43XX_H */

45
arch/arm/include/asm/arch-am33xx/mux_am43xx.h
View File

@ -137,6 +137,51 @@ struct pad_signals {
int mcasp0_fsr;
int mcasp0_axr1;
int mcasp0_ahclkx;
int xdma_event_intr0;
int xdma_event_intr1;
int nresetin_out;
int porz;
int nnmi;
int osc0_in;
int osc0_out;
int rsvd1;
int tms;
int tdi;
int tdo;
int tck;
int ntrst;
int emu0;
int emu1;
int osc1_in;
int osc1_out;
int pmic_power_en;
int rtc_porz;
int rsvd2;
int ext_wakeup;
int enz_kaldo_1p8v;
int usb0_dm;
int usb0_dp;
int usb0_ce;
int usb0_id;
int usb0_vbus;
int usb0_drvvbus;
int usb1_dm;
int usb1_dp;
int usb1_ce;
int usb1_id;
int usb1_vbus;
int usb1_drvvbus;
int ddr_resetn;
int ddr_csn0;
int ddr_cke;
int ddr_ck;
int ddr_nck;
int ddr_casn;
int ddr_rasn;
int ddr_wen;
int ddr_ba0;
int ddr_ba1;
int ddr_ba2;
};
#endif /* _MUX_AM43XX_H_ */

4
arch/arm/include/asm/arch-am33xx/omap.h
View File

@ -26,6 +26,8 @@
#elif defined(CONFIG_AM43XX)
#define NON_SECURE_SRAM_START 0x402F0400
#define NON_SECURE_SRAM_END 0x40340000
#define SRAM_SCRATCH_SPACE_ADDR 0x4033C000
#define SRAM_SCRATCH_SPACE_ADDR 0x40337C00
#define AM4372_BOARD_NAME_START SRAM_SCRATCH_SPACE_ADDR
#define AM4372_BOARD_NAME_END SRAM_SCRATCH_SPACE_ADDR + 0xC
#endif
#endif

13
arch/arm/include/asm/arch-am33xx/spl.h
View File

@ -13,11 +13,18 @@
#define BOOT_DEVICE_MMC1 6
#define BOOT_DEVICE_MMC2 5
#define BOOT_DEVICE_UART 0x43
#define BOOT_DEVICE_MMC2_2 0xFF
#elif defined(CONFIG_AM43XX)
#define BOOT_DEVICE_NOR 1
#define BOOT_DEVICE_NAND 5
#define BOOT_DEVICE_MMC1 7
#define BOOT_DEVICE_MMC2 8
#define BOOT_DEVICE_SPI 10
#define BOOT_DEVICE_UART 65
#define BOOT_DEVICE_CPGMAC 71
#else
#define BOOT_DEVICE_XIP 2
#define BOOT_DEVICE_NAND 5
#if defined(CONFIG_AM33XX) || defined(CONFIG_AM43XX)
#if defined(CONFIG_AM33XX)
#define BOOT_DEVICE_MMC1 8
#define BOOT_DEVICE_MMC2 9 /* eMMC or daughter card */
#elif defined(CONFIG_TI814X)
@ -28,8 +35,8 @@
#define BOOT_DEVICE_UART 65
#define BOOT_DEVICE_USBETH 68
#define BOOT_DEVICE_CPGMAC 70
#define BOOT_DEVICE_MMC2_2 0xFF
#endif
#define BOOT_DEVICE_MMC2_2 0xFF
#if defined(CONFIG_AM33XX) || defined(CONFIG_AM43XX)
#define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC1

17
arch/arm/include/asm/arch-exynos/board.h Normal file
View File

@ -0,0 +1,17 @@
/*
* (C) Copyright 2013 Samsung Electronics
* Rajeshwari Shinde <rajeshwari.s@samsung.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _EXYNOS_BOARD_H
#define _EXYNOS_BOARD_H
/*
* Exynos baord specific changes for
* board_init
*/
int exynos_init(void);
#endif /* EXYNOS_BOARD_H */

1
arch/arm/include/asm/arch-exynos/clk.h
View File

@ -14,6 +14,7 @@
#define HPLL 3
#define VPLL 4
#define BPLL 5
#define RPLL 6
enum pll_src_bit {
EXYNOS_SRC_MPLL = 6,

494
arch/arm/include/asm/arch-exynos/clock.h
View File

@ -858,6 +858,500 @@ struct exynos5_clock {
unsigned char res123[0xf5d8];
};
struct exynos5420_clock {
unsigned int apll_lock; /* 0x10010000 */
unsigned char res1[0xfc];
unsigned int apll_con0;
unsigned int apll_con1;
unsigned char res2[0xf8];
unsigned int src_cpu;
unsigned char res3[0x1fc];
unsigned int mux_stat_cpu;
unsigned char res4[0xfc];
unsigned int div_cpu0; /* 0x10010500 */
unsigned int div_cpu1;
unsigned char res5[0xf8];
unsigned int div_stat_cpu0;
unsigned int div_stat_cpu1;
unsigned char res6[0xf8];
unsigned int gate_bus_cpu;
unsigned char res7[0xfc];
unsigned int gate_sclk_cpu;
unsigned char res8[0x1fc];
unsigned int clkout_cmu_cpu; /* 0x10010a00 */
unsigned int clkout_cmu_cpu_div_stat;
unsigned char res9[0x5f8];
unsigned int armclk_stopctrl;
unsigned char res10[0x4];
unsigned int arm_ema_ctrl;
unsigned int arm_ema_status;
unsigned char res11[0x10];
unsigned int pwr_ctrl;
unsigned int pwr_ctrl2;
unsigned char res12[0xd8];
unsigned int apll_con0_l8; /* 0x1001100 */
unsigned int apll_con0_l7;
unsigned int apll_con0_l6;
unsigned int apll_con0_l5;
unsigned int apll_con0_l4;
unsigned int apll_con0_l3;
unsigned int apll_con0_l2;
unsigned int apll_con0_l1;
unsigned int iem_control;
unsigned char res13[0xdc];
unsigned int apll_con1_l8; /* 0x10011200 */
unsigned int apll_con1_l7;
unsigned int apll_con1_l6;
unsigned int apll_con1_l5;
unsigned int apll_con1_l4;
unsigned int apll_con1_l3;
unsigned int apll_con1_l2;
unsigned int apll_con1_l1;
unsigned char res14[0xe0];
unsigned int clkdiv_iem_l8;
unsigned int clkdiv_iem_l7; /* 0x10011304 */
unsigned int clkdiv_iem_l6;
unsigned int clkdiv_iem_l5;
unsigned int clkdiv_iem_l4;
unsigned int clkdiv_iem_l3;
unsigned int clkdiv_iem_l2;
unsigned int clkdiv_iem_l1;
unsigned char res15[0xe0];
unsigned int l2_status;
unsigned char res16[0x0c];
unsigned int cpu_status; /* 0x10011410 */
unsigned char res17[0x0c];
unsigned int ptm_status;
unsigned char res18[0xbdc];
unsigned int cmu_cpu_spare0;
unsigned int cmu_cpu_spare1;
unsigned int cmu_cpu_spare2;
unsigned int cmu_cpu_spare3;
unsigned int cmu_cpu_spare4;
unsigned char res19[0x1fdc];
unsigned int cmu_cpu_version;
unsigned char res20[0x20c];
unsigned int src_cperi0; /* 0x10014200 */
unsigned int src_cperi1;
unsigned char res21[0xf8];
unsigned int src_mask_cperi;
unsigned char res22[0x100];
unsigned int mux_stat_cperi1;
unsigned char res23[0xfc];
unsigned int div_cperi1;
unsigned char res24[0xfc];
unsigned int div_stat_cperi1;
unsigned char res25[0xf8];
unsigned int gate_bus_cperi0; /* 0x10014700 */
unsigned int gate_bus_cperi1;
unsigned char res26[0xf8];
unsigned int gate_sclk_cperi;
unsigned char res27[0xfc];
unsigned int gate_ip_cperi;
unsigned char res28[0xfc];
unsigned int clkout_cmu_cperi;
unsigned int clkout_cmu_cperi_div_stat;
unsigned char res29[0x5f8];
unsigned int dcgidx_map0; /* 0x10015000 */
unsigned int dcgidx_map1;
unsigned int dcgidx_map2;
unsigned char res30[0x14];
unsigned int dcgperf_map0;
unsigned int dcgperf_map1;
unsigned char res31[0x18];
unsigned int dvcidx_map;
unsigned char res32[0x1c];
unsigned int freq_cpu;
unsigned int freq_dpm;
unsigned char res33[0x18];
unsigned int dvsemclk_en; /* 0x10015080 */
unsigned int maxperf;
unsigned char res34[0x2e78];
unsigned int cmu_cperi_spare0;
unsigned int cmu_cperi_spare1;
unsigned int cmu_cperi_spare2;
unsigned int cmu_cperi_spare3;
unsigned int cmu_cperi_spare4;
unsigned int cmu_cperi_spare5;
unsigned int cmu_cperi_spare6;
unsigned int cmu_cperi_spare7;
unsigned int cmu_cperi_spare8;
unsigned char res35[0xcc];
unsigned int cmu_cperi_version; /* 0x10017ff0 */
unsigned char res36[0x50c];
unsigned int div_g2d;
unsigned char res37[0xfc];
unsigned int div_stat_g2d;
unsigned char res38[0xfc];
unsigned int gate_bus_g2d;
unsigned char res39[0xfc];
unsigned int gate_ip_g2d;
unsigned char res40[0x1fc];
unsigned int clkout_cmu_g2d;
unsigned int clkout_cmu_g2d_div_stat; /* 0x10018a04 */
unsigned char res41[0xf8];
unsigned int cmu_g2d_spare0;
unsigned int cmu_g2d_spare1;
unsigned int cmu_g2d_spare2;
unsigned int cmu_g2d_spare3;
unsigned int cmu_g2d_spare4;
unsigned char res42[0x34dc];
unsigned int cmu_g2d_version;
unsigned char res43[0x30c];
unsigned int div_cmu_isp0;
unsigned int div_cmu_isp1;
unsigned int div_isp2; /* 0x1001c308 */
unsigned char res44[0xf4];
unsigned int div_stat_cmu_isp0;
unsigned int div_stat_cmu_isp1;
unsigned int div_stat_isp2;
unsigned char res45[0x2f4];
unsigned int gate_bus_isp0;
unsigned int gate_bus_isp1;
unsigned int gate_bus_isp2;
unsigned int gate_bus_isp3;
unsigned char res46[0xf0];
unsigned int gate_ip_isp0;
unsigned int gate_ip_isp1;
unsigned char res47[0xf8];
unsigned int gate_sclk_isp;
unsigned char res48[0x0c];
unsigned int mcuisp_pwr_ctrl; /* 0x1001c910 */
unsigned char res49[0x0ec];
unsigned int clkout_cmu_isp;
unsigned int clkout_cmu_isp_div_stat;
unsigned char res50[0xf8];
unsigned int cmu_isp_spare0;
unsigned int cmu_isp_spare1;
unsigned int cmu_isp_spare2;
unsigned int cmu_isp_spare3;
unsigned char res51[0x34e0];
unsigned int cmu_isp_version;
unsigned char res52[0x2c];
unsigned int cpll_lock; /* 10020020 */
unsigned char res53[0xc];
unsigned int dpll_lock;
unsigned char res54[0xc];
unsigned int epll_lock;
unsigned char res55[0xc];
unsigned int rpll_lock;
unsigned char res56[0xc];
unsigned int ipll_lock;
unsigned char res57[0xc];
unsigned int spll_lock;
unsigned char res58[0xc];
unsigned int vpll_lock;
unsigned char res59[0xc];
unsigned int mpll_lock;
unsigned char res60[0x8c];
unsigned int cpll_con0; /* 10020120 */
unsigned int cpll_con1;
unsigned int dpll_con0;
unsigned int dpll_con1;
unsigned int epll_con0;
unsigned int epll_con1;
unsigned int epll_con2;
unsigned char res601[0x4];
unsigned int rpll_con0;
unsigned int rpll_con1;
unsigned int rpll_con2;
unsigned char res602[0x4];
unsigned int ipll_con0;
unsigned int ipll_con1;
unsigned char res61[0x8];
unsigned int spll_con0;
unsigned int spll_con1;
unsigned char res62[0x8];
unsigned int vpll_con0;
unsigned int vpll_con1;
unsigned char res63[0x8];
unsigned int mpll_con0;
unsigned int mpll_con1;
unsigned char res64[0x78];
unsigned int src_top0; /* 0x10020200 */
unsigned int src_top1;
unsigned int src_top2;
unsigned int src_top3;
unsigned int src_top4;
unsigned int src_top5;
unsigned int src_top6;
unsigned int src_top7;
unsigned char res65[0xc];
unsigned int src_disp10; /* 0x1002022c */
unsigned char res66[0x10];
unsigned int src_mau;
unsigned int src_fsys;
unsigned char res67[0x8];
unsigned int src_peric0;
unsigned int src_peric1;
unsigned char res68[0x18];
unsigned int src_isp;
unsigned char res69[0x0c];
unsigned int src_top10;
unsigned int src_top11;
unsigned int src_top12;
unsigned char res70[0x74];
unsigned int src_mask_top0;
unsigned int src_mask_top1;
unsigned int src_mask_top2;
unsigned char res71[0x10];
unsigned int src_mask_top7;
unsigned char res72[0xc];
unsigned int src_mask_disp10; /* 0x1002032c */
unsigned char res73[0x4];
unsigned int src_mask_mau;
unsigned char res74[0x8];
unsigned int src_mask_fsys;
unsigned char res75[0xc];
unsigned int src_mask_peric0;
unsigned int src_mask_peric1;
unsigned char res76[0x18];
unsigned int src_mask_isp;
unsigned char res77[0x8c];
unsigned int mux_stat_top0; /* 0x10020400 */
unsigned int mux_stat_top1;
unsigned int mux_stat_top2;
unsigned int mux_stat_top3;
unsigned int mux_stat_top4;
unsigned int mux_stat_top5;
unsigned int mux_stat_top6;
unsigned int mux_stat_top7;
unsigned char res78[0x60];
unsigned int mux_stat_top10;
unsigned int mux_stat_top11;
unsigned int mux_stat_top12;
unsigned char res79[0x74];
unsigned int div_top0; /* 0x10020500 */
unsigned int div_top1;
unsigned int div_top2;
unsigned char res80[0x20];
unsigned int div_disp10;
unsigned char res81[0x14];
unsigned int div_mau;
unsigned int div_fsys0;
unsigned int div_fsys1;
unsigned int div_fsys2;
unsigned char res82[0x4];
unsigned int div_peric0;
unsigned int div_peric1;
unsigned int div_peric2;
unsigned int div_peric3;
unsigned int div_peric4; /* 0x10020568 */
unsigned char res83[0x14];
unsigned int div_isp0;
unsigned int div_isp1;
unsigned char res84[0x8];
unsigned int clkdiv2_ratio;
unsigned char res850[0xc];
unsigned int clkdiv4_ratio;
unsigned char res85[0x5c];
unsigned int div_stat_top0;
unsigned int div_stat_top1;
unsigned int div_stat_top2;
unsigned char res86[0x20];
unsigned int div_stat_disp10;
unsigned char res87[0x14];
unsigned int div_stat_mau; /* 0x10020644 */
unsigned int div_stat_fsys0;
unsigned int div_stat_fsys1;
unsigned int div_stat_fsys2;
unsigned char res88[0x4];
unsigned int div_stat_peric0;
unsigned int div_stat_peric1;
unsigned int div_stat_peric2;
unsigned int div_stat_peric3;
unsigned int div_stat_peric4;
unsigned char res89[0x14];
unsigned int div_stat_isp0;
unsigned int div_stat_isp1;
unsigned char res90[0x8];
unsigned int clkdiv2_stat0;
unsigned char res91[0xc];
unsigned int clkdiv4_stat;
unsigned char res92[0x5c];
unsigned int gate_bus_top; /* 0x10020700 */
unsigned char res93[0xc];
unsigned int gate_bus_gscl0;
unsigned char res94[0xc];
unsigned int gate_bus_gscl1;
unsigned char res95[0x4];
unsigned int gate_bus_disp1;
unsigned char res96[0x4];
unsigned int gate_bus_wcore;
unsigned int gate_bus_mfc;
unsigned int gate_bus_g3d;
unsigned int gate_bus_gen;
unsigned int gate_bus_fsys0;
unsigned int gate_bus_fsys1;
unsigned int gate_bus_fsys2;
unsigned int gate_bus_mscl;
unsigned int gate_bus_peric;
unsigned int gate_bus_peric1;
unsigned char res97[0x8];
unsigned int gate_bus_peris0;
unsigned int gate_bus_peris1; /* 0x10020764 */
unsigned char res98[0x8];
unsigned int gate_bus_noc;
unsigned char res99[0xac];
unsigned int gate_top_sclk_gscl;
unsigned char res1000[0x4];
unsigned int gate_top_sclk_disp1;
unsigned char res100[0x10];
unsigned int gate_top_sclk_mau;
unsigned int gate_top_sclk_fsys;
unsigned char res101[0xc];
unsigned int gate_top_sclk_peric;
unsigned char res102[0xc];
unsigned int gate_top_sclk_cperi;
unsigned char res103[0xc];
unsigned int gate_top_sclk_isp;
unsigned char res104[0x9c];
unsigned int gate_ip_gscl0;
unsigned char res105[0xc];
unsigned int gate_ip_gscl1;
unsigned char res106[0x4];
unsigned int gate_ip_disp1;
unsigned int gate_ip_mfc;
unsigned int gate_ip_g3d;
unsigned int gate_ip_gen; /* 0x10020934 */
unsigned char res107[0xc];
unsigned int gate_ip_fsys;
unsigned char res108[0x8];
unsigned int gate_ip_peric;
unsigned char res109[0xc];
unsigned int gate_ip_peris;
unsigned char res110[0xc];
unsigned int gate_ip_mscl;
unsigned char res111[0xc];
unsigned int gate_ip_block;
unsigned char res112[0xc];
unsigned int bypass;
unsigned char res113[0x6c];
unsigned int clkout_cmu_top;
unsigned int clkout_cmu_top_div_stat;
unsigned char res114[0xf8];
unsigned int clkout_top_spare0;
unsigned int clkout_top_spare1;
unsigned int clkout_top_spare2;
unsigned int clkout_top_spare3;
unsigned char res115[0x34e0];
unsigned int clkout_top_version;
unsigned char res116[0xc01c];
unsigned int bpll_lock; /* 0x10030010 */
unsigned char res117[0xfc];
unsigned int bpll_con0;
unsigned int bpll_con1;
unsigned char res118[0xe8];
unsigned int src_cdrex;
unsigned char res119[0x1fc];
unsigned int mux_stat_cdrex;
unsigned char res120[0xfc];
unsigned int div_cdrex0;
unsigned int div_cdrex1;
unsigned char res121[0xf8];
unsigned int div_stat_cdrex;
unsigned char res1211[0xfc];
unsigned int gate_bus_cdrex;
unsigned int gate_bus_cdrex1;
unsigned char res122[0x1f8];
unsigned int gate_ip_cdrex;
unsigned char res123[0x10];
unsigned int dmc_freq_ctrl; /* 0x10030914 */
unsigned char res124[0x4];
unsigned int pause;
unsigned int ddrphy_lock_ctrl;
unsigned char res125[0xdc];
unsigned int clkout_cmu_cdrex;
unsigned int clkout_cmu_cdrex_div_stat;
unsigned char res126[0x8];
unsigned int lpddr3phy_ctrl;
unsigned int lpddr3phy_con0;
unsigned int lpddr3phy_con1;
unsigned int lpddr3phy_con2;
unsigned int lpddr3phy_con3;
unsigned int lpddr3phy_con4;
unsigned int lpddr3phy_con5; /* 0x10030a28 */
unsigned int pll_div2_sel;
unsigned char res127[0xd0];
unsigned int cmu_cdrex_spare0;
unsigned int cmu_cdrex_spare1;
unsigned int cmu_cdrex_spare2;
unsigned int cmu_cdrex_spare3;
unsigned int cmu_cdrex_spare4;
unsigned char res128[0x34dc];
unsigned int cmu_cdrex_version; /* 0x10033ff0 */
unsigned char res129[0x400c];
unsigned int kpll_lock;
unsigned char res130[0xfc];
unsigned int kpll_con0;
unsigned int kpll_con1;
unsigned char res131[0xf8];
unsigned int src_kfc;
unsigned char res132[0x1fc];
unsigned int mux_stat_kfc; /* 0x10038400 */
unsigned char res133[0xfc];
unsigned int div_kfc0;
unsigned char res134[0xfc];
unsigned int div_stat_kfc0;
unsigned char res135[0xfc];
unsigned int gate_bus_cpu_kfc;
unsigned char res136[0xfc];
unsigned int gate_sclk_cpu_kfc;
unsigned char res137[0x1fc];
unsigned int clkout_cmu_kfc;
unsigned int clkout_cmu_kfc_div_stat; /* 0x10038a04 */
unsigned char res138[0x5f8];
unsigned int armclk_stopctrl_kfc;
unsigned char res139[0x4];
unsigned int armclk_ema_ctrl_kfc;
unsigned int armclk_ema_status_kfc;
unsigned char res140[0x10];
unsigned int pwr_ctrl_kfc;
unsigned int pwr_ctrl2_kfc;
unsigned char res141[0xd8];
unsigned int kpll_con0_l8;
unsigned int kpll_con0_l7;
unsigned int kpll_con0_l6;
unsigned int kpll_con0_l5;
unsigned int kpll_con0_l4;
unsigned int kpll_con0_l3;
unsigned int kpll_con0_l2;
unsigned int kpll_con0_l1;
unsigned int iem_control_kfc; /* 0x10039120 */
unsigned char res142[0xdc];
unsigned int kpll_con1_l8;
unsigned int kpll_con1_l7;
unsigned int kpll_con1_l6;
unsigned int kpll_con1_l5;
unsigned int kpll_con1_l4;
unsigned int kpll_con1_l3;
unsigned int kpll_con1_l2;
unsigned int kpll_con1_l1;
unsigned char res143[0xe0];
unsigned int clkdiv_iem_l8_kfc; /* 0x10039300 */
unsigned int clkdiv_iem_l7_kfc;
unsigned int clkdiv_iem_l6_kfc;
unsigned int clkdiv_iem_l5_kfc;
unsigned int clkdiv_iem_l4_kfc;
unsigned int clkdiv_iem_l3_kfc;
unsigned int clkdiv_iem_l2_kfc;
unsigned int clkdiv_iem_l1_kfc;
unsigned char res144[0xe0];
unsigned int l2_status_kfc;
unsigned char res145[0xc];
unsigned int cpu_status_kfc; /* 0x10039410 */
unsigned char res146[0xc];
unsigned int ptm_status_kfc;
unsigned char res147[0xbdc];
unsigned int cmu_kfc_spare0;
unsigned int cmu_kfc_spare1;
unsigned int cmu_kfc_spare2;
unsigned int cmu_kfc_spare3;
unsigned int cmu_kfc_spare4;
unsigned char res148[0x1fdc];
unsigned int cmu_kfc_version; /* 0x1003bff0 */
};
/* structure for epll configuration used in audio clock configuration */
struct set_epll_con_val {
unsigned int freq_out; /* frequency out */

52
arch/arm/include/asm/arch-exynos/cpu.h
View File

@ -53,6 +53,7 @@
#define EXYNOS4_AUDIOSS_BASE DEVICE_NOT_AVAILABLE
#define EXYNOS4_USB_HOST_XHCI_BASE DEVICE_NOT_AVAILABLE
#define EXYNOS4_USB3PHY_BASE DEVICE_NOT_AVAILABLE
#define EXYNOS4_DMC_TZASC_BASE DEVICE_NOT_AVAILABLE
/* EXYNOS4X12 */
#define EXYNOS4X12_GPIO_PART3_BASE 0x03860000
@ -91,8 +92,9 @@
#define EXYNOS4X12_AUDIOSS_BASE DEVICE_NOT_AVAILABLE
#define EXYNOS4X12_USB_HOST_XHCI_BASE DEVICE_NOT_AVAILABLE
#define EXYNOS4X12_USB3PHY_BASE DEVICE_NOT_AVAILABLE
#define EXYNOS4X12_DMC_TZASC_BASE DEVICE_NOT_AVAILABLE
/* EXYNOS5 Common*/
/* EXYNOS5 */
#define EXYNOS5_I2C_SPACING 0x10000
#define EXYNOS5_AUDIOSS_BASE 0x03810000
@ -129,6 +131,46 @@
#define EXYNOS5_ADC_BASE DEVICE_NOT_AVAILABLE
#define EXYNOS5_MODEM_BASE DEVICE_NOT_AVAILABLE
#define EXYNOS5_DMC_TZASC_BASE DEVICE_NOT_AVAILABLE
/* EXYNOS5420 */
#define EXYNOS5420_AUDIOSS_BASE 0x03810000
#define EXYNOS5420_GPIO_PART5_BASE 0x03860000
#define EXYNOS5420_PRO_ID 0x10000000
#define EXYNOS5420_CLOCK_BASE 0x10010000
#define EXYNOS5420_POWER_BASE 0x10040000
#define EXYNOS5420_SWRESET 0x10040400
#define EXYNOS5420_SYSREG_BASE 0x10050000
#define EXYNOS5420_TZPC_BASE 0x100E0000
#define EXYNOS5420_WATCHDOG_BASE 0x101D0000
#define EXYNOS5420_ACE_SFR_BASE 0x10830000
#define EXYNOS5420_DMC_PHY_BASE 0x10C00000
#define EXYNOS5420_DMC_CTRL_BASE 0x10C20000
#define EXYNOS5420_DMC_TZASC_BASE 0x10D40000
#define EXYNOS5420_USB_HOST_EHCI_BASE 0x12110000
#define EXYNOS5420_MMC_BASE 0x12200000
#define EXYNOS5420_SROMC_BASE 0x12250000
#define EXYNOS5420_UART_BASE 0x12C00000
#define EXYNOS5420_I2C_BASE 0x12C60000
#define EXYNOS5420_I2C_8910_BASE 0x12E00000
#define EXYNOS5420_SPI_BASE 0x12D20000
#define EXYNOS5420_I2S_BASE 0x12D60000
#define EXYNOS5420_PWMTIMER_BASE 0x12DD0000
#define EXYNOS5420_SPI_ISP_BASE 0x131A0000
#define EXYNOS5420_GPIO_PART2_BASE 0x13400000
#define EXYNOS5420_GPIO_PART3_BASE 0x13410000
#define EXYNOS5420_GPIO_PART4_BASE 0x14000000
#define EXYNOS5420_GPIO_PART1_BASE 0x14010000
#define EXYNOS5420_MIPI_DSIM_BASE 0x14500000
#define EXYNOS5420_DP_BASE 0x145B0000
#define EXYNOS5420_USBPHY_BASE DEVICE_NOT_AVAILABLE
#define EXYNOS5420_USBOTG_BASE DEVICE_NOT_AVAILABLE
#define EXYNOS5420_FIMD_BASE DEVICE_NOT_AVAILABLE
#define EXYNOS5420_ADC_BASE DEVICE_NOT_AVAILABLE
#define EXYNOS5420_MODEM_BASE DEVICE_NOT_AVAILABLE
#define EXYNOS5420_USB3PHY_BASE DEVICE_NOT_AVAILABLE
#define EXYNOS5420_USB_HOST_XHCI_BASE DEVICE_NOT_AVAILABLE
#ifndef __ASSEMBLY__
#include <asm/io.h>
@ -163,6 +205,10 @@ static inline void s5p_set_cpu_id(void)
/* Exynos5250 */
s5p_cpu_id = 0x5250;
break;
case 0x420:
/* Exynos5420 */
s5p_cpu_id = 0x5420;
break;
}
}
@ -190,6 +236,7 @@ static inline int __attribute__((no_instrument_function)) \
IS_EXYNOS_TYPE(exynos4210, 0x4210)
IS_EXYNOS_TYPE(exynos4412, 0x4412)
IS_EXYNOS_TYPE(exynos5250, 0x5250)
IS_EXYNOS_TYPE(exynos5420, 0x5420)
#define SAMSUNG_BASE(device, base) \
static inline unsigned int __attribute__((no_instrument_function)) \
@ -200,6 +247,8 @@ static inline unsigned int __attribute__((no_instrument_function)) \
return EXYNOS4X12_##base; \
return EXYNOS4_##base; \
} else if (cpu_is_exynos5()) { \
if (proid_is_exynos5420()) \
return EXYNOS5420_##base; \
return EXYNOS5_##base; \
} \
return 0; \
@ -237,6 +286,7 @@ SAMSUNG_BASE(spi_isp, SPI_ISP_BASE)
SAMSUNG_BASE(tzpc, TZPC_BASE)
SAMSUNG_BASE(dmc_ctrl, DMC_CTRL_BASE)
SAMSUNG_BASE(dmc_phy, DMC_PHY_BASE)
SAMSUNG_BASE(dmc_tzasc, DMC_TZASC_BASE)
SAMSUNG_BASE(audio_ass, AUDIOSS_BASE)
#endif

177
arch/arm/include/asm/arch-exynos/dmc.h
View File

@ -205,6 +205,127 @@ struct exynos5_dmc {
unsigned int pmcnt3_ppc_a;
};
struct exynos5420_dmc {
unsigned int concontrol;
unsigned int memcontrol;
unsigned int cgcontrol;
unsigned char res500[0x4];
unsigned int directcmd;
unsigned int prechconfig0;
unsigned int phycontrol0;
unsigned int prechconfig1;
unsigned char res1[0x8];
unsigned int pwrdnconfig;
unsigned int timingpzq;
unsigned int timingref;
unsigned int timingrow0;
unsigned int timingdata0;
unsigned int timingpower0;
unsigned int phystatus;
unsigned int etctiming;
unsigned int chipstatus;
unsigned char res3[0x8];
unsigned int mrstatus;
unsigned char res4[0x8];
unsigned int qoscontrol0;
unsigned char resr5[0x4];
unsigned int qoscontrol1;
unsigned char res6[0x4];
unsigned int qoscontrol2;
unsigned char res7[0x4];
unsigned int qoscontrol3;
unsigned char res8[0x4];
unsigned int qoscontrol4;
unsigned char res9[0x4];
unsigned int qoscontrol5;
unsigned char res10[0x4];
unsigned int qoscontrol6;
unsigned char res11[0x4];
unsigned int qoscontrol7;
unsigned char res12[0x4];
unsigned int qoscontrol8;
unsigned char res13[0x4];
unsigned int qoscontrol9;
unsigned char res14[0x4];
unsigned int qoscontrol10;
unsigned char res15[0x4];
unsigned int qoscontrol11;
unsigned char res16[0x4];
unsigned int qoscontrol12;
unsigned char res17[0x4];
unsigned int qoscontrol13;
unsigned char res18[0x4];
unsigned int qoscontrol14;
unsigned char res19[0x4];
unsigned int qoscontrol15;
unsigned char res20[0x4];
unsigned int timing_set_sw;
unsigned int timingrow1;
unsigned int timingdata1;
unsigned int timingpower1;
unsigned char res300[0x4];
unsigned int wrtra_config;
unsigned int rdlvl_config;
unsigned char res21[0x4];
unsigned int brbrsvcontrol;
unsigned int brbrsvconfig;
unsigned int brbqosconfig;
unsigned char res301[0x14];
unsigned int wrlvl_config0;
unsigned int wrlvl_config1;
unsigned int wrlvl_status;
unsigned char res23[0x4];
unsigned int ppcclockon;
unsigned int perevconfig0;
unsigned int perevconfig1;
unsigned int perevconfig2;
unsigned int perevconfig3;
unsigned char res24[0xc];
unsigned int control_io_rdata;
unsigned char res240[0xc];
unsigned int cacal_config0;
unsigned int cacal_config1;
unsigned int cacal_status;
unsigned char res302[0xa4];
unsigned int bp_control0;
unsigned int bp_config0_r;
unsigned int bp_config0_w;
unsigned char res303[0x4];
unsigned int bp_control1;
unsigned int bp_config1_r;
unsigned int bp_config1_w;
unsigned char res304[0x4];
unsigned int bp_control2;
unsigned int bp_config2_r;
unsigned int bp_config2_w;
unsigned char res305[0x4];
unsigned int bp_control3;
unsigned int bp_config3_r;
unsigned int bp_config3_w;
unsigned char res306[0xddb4];
unsigned int pmnc_ppc;
unsigned char res25[0xc];
unsigned int cntens_ppc;
unsigned char res26[0xc];
unsigned int cntenc_ppc;
unsigned char res27[0xc];
unsigned int intens_ppc;
unsigned char res28[0xc];
unsigned int intenc_ppc;
unsigned char res29[0xc];
unsigned int flag_ppc;
unsigned char res30[0xac];
unsigned int ccnt_ppc;
unsigned char res31[0xc];
unsigned int pmcnt0_ppc;
unsigned char res32[0xc];
unsigned int pmcnt1_ppc;
unsigned char res33[0xc];
unsigned int pmcnt2_ppc;
unsigned char res34[0xc];
unsigned int pmcnt3_ppc;
};
struct exynos5_phy_control {
unsigned int phy_con0;
unsigned int phy_con1;
@ -252,6 +373,61 @@ struct exynos5_phy_control {
unsigned int phy_con42;
};
struct exynos5420_phy_control {
unsigned int phy_con0;
unsigned int phy_con1;
unsigned int phy_con2;
unsigned int phy_con3;
unsigned int phy_con4;
unsigned int phy_con5;
unsigned int phy_con6;
unsigned char res2[0x4];
unsigned int phy_con8;
unsigned char res5[0x4];
unsigned int phy_con10;
unsigned int phy_con11;
unsigned int phy_con12;
unsigned int phy_con13;
unsigned int phy_con14;
unsigned int phy_con15;
unsigned int phy_con16;
unsigned char res4[0x4];
unsigned int phy_con17;
unsigned int phy_con18;
unsigned int phy_con19;
unsigned int phy_con20;
unsigned int phy_con21;
unsigned int phy_con22;
unsigned int phy_con23;
unsigned int phy_con24;
unsigned int phy_con25;
unsigned int phy_con26;
unsigned int phy_con27;
unsigned int phy_con28;
unsigned int phy_con29;
unsigned int phy_con30;
unsigned int phy_con31;
unsigned int phy_con32;
unsigned int phy_con33;
unsigned int phy_con34;
unsigned char res6[0x8];
unsigned int phy_con37;
unsigned char res7[0x4];
unsigned int phy_con39;
unsigned int phy_con40;
unsigned int phy_con41;
unsigned int phy_con42;
};
struct exynos5420_tzasc {
unsigned char res1[0xf00];
unsigned int membaseconfig0;
unsigned int membaseconfig1;
unsigned char res2[0x8];
unsigned int memconfig0;
unsigned int memconfig1;
};
enum ddr_mode {
DDR_MODE_DDR2,
DDR_MODE_DDR3,
@ -286,6 +462,7 @@ enum mem_manuf {
#define PHY_CON0_T_WRRDCMD_SHIFT 17
#define PHY_CON0_T_WRRDCMD_MASK (0x7 << PHY_CON0_T_WRRDCMD_SHIFT)
#define PHY_CON0_CTRL_DDR_MODE_SHIFT 11
#define PHY_CON0_CTRL_DDR_MODE_MASK 0x3
/* PHY_CON1 register fields */
#define PHY_CON1_RDLVL_RDDATA_ADJ_SHIFT 0

143
arch/arm/include/asm/arch-exynos/gpio.h
View File

@ -127,6 +127,58 @@ struct exynos4x12_gpio_part4 {
struct s5p_gpio_bank v4;
};
struct exynos5420_gpio_part1 {
struct s5p_gpio_bank a0;
struct s5p_gpio_bank a1;
struct s5p_gpio_bank a2;
struct s5p_gpio_bank b0;
struct s5p_gpio_bank b1;
struct s5p_gpio_bank b2;
struct s5p_gpio_bank b3;
struct s5p_gpio_bank b4;
struct s5p_gpio_bank h0;
};
struct exynos5420_gpio_part2 {
struct s5p_gpio_bank y7; /* 0x1340_0000 */
struct s5p_gpio_bank res[0x5f]; /* */
struct s5p_gpio_bank x0; /* 0x1340_0C00 */
struct s5p_gpio_bank x1; /* 0x1340_0C20 */
struct s5p_gpio_bank x2; /* 0x1340_0C40 */
struct s5p_gpio_bank x3; /* 0x1340_0C60 */
};
struct exynos5420_gpio_part3 {
struct s5p_gpio_bank c0;
struct s5p_gpio_bank c1;
struct s5p_gpio_bank c2;
struct s5p_gpio_bank c3;
struct s5p_gpio_bank c4;
struct s5p_gpio_bank d1;
struct s5p_gpio_bank y0;
struct s5p_gpio_bank y1;
struct s5p_gpio_bank y2;
struct s5p_gpio_bank y3;
struct s5p_gpio_bank y4;
struct s5p_gpio_bank y5;
struct s5p_gpio_bank y6;
};
struct exynos5420_gpio_part4 {
struct s5p_gpio_bank e0; /* 0x1400_0000 */
struct s5p_gpio_bank e1; /* 0x1400_0020 */
struct s5p_gpio_bank f0; /* 0x1400_0040 */
struct s5p_gpio_bank f1; /* 0x1400_0060 */
struct s5p_gpio_bank g0; /* 0x1400_0080 */
struct s5p_gpio_bank g1; /* 0x1400_00A0 */
struct s5p_gpio_bank g2; /* 0x1400_00C0 */
struct s5p_gpio_bank j4; /* 0x1400_00E0 */
};
struct exynos5420_gpio_part5 {
struct s5p_gpio_bank z0; /* 0x0386_0000 */
};
struct exynos5_gpio_part1 {
struct s5p_gpio_bank a0;
struct s5p_gpio_bank a1;
@ -259,16 +311,67 @@ void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode);
- EXYNOS5_GPIO_PART3_BASE) / sizeof(struct s5p_gpio_bank)) \
* GPIO_PER_BANK) + pin) + EXYNOS5_GPIO_PART2_MAX)
/* EXYNOS5420 */
#define exynos5420_gpio_part1_get_nr(bank, pin) \
((((((unsigned int) &(((struct exynos5420_gpio_part1 *)\
EXYNOS5420_GPIO_PART1_BASE)->bank)) \
- EXYNOS5420_GPIO_PART1_BASE) / sizeof(struct s5p_gpio_bank)) \
* GPIO_PER_BANK) + pin)
#define EXYNOS5420_GPIO_PART1_MAX ((sizeof(struct exynos5420_gpio_part1) \
/ sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK)
#define exynos5420_gpio_part2_get_nr(bank, pin) \
(((((((unsigned int) &(((struct exynos5420_gpio_part2 *)\
EXYNOS5420_GPIO_PART2_BASE)->bank)) \
- EXYNOS5420_GPIO_PART2_BASE) / sizeof(struct s5p_gpio_bank)) \
* GPIO_PER_BANK) + pin) + EXYNOS5420_GPIO_PART1_MAX)
#define EXYNOS5420_GPIO_PART2_MAX ((sizeof(struct exynos5420_gpio_part2) \
/ sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK)
#define exynos5420_gpio_part3_get_nr(bank, pin) \
(((((((unsigned int) &(((struct exynos5420_gpio_part3 *)\
EXYNOS5420_GPIO_PART3_BASE)->bank)) \
- EXYNOS5420_GPIO_PART3_BASE) / sizeof(struct s5p_gpio_bank)) \
* GPIO_PER_BANK) + pin) + EXYNOS5420_GPIO_PART2_MAX)
#define EXYNOS5420_GPIO_PART3_MAX ((sizeof(struct exynos5420_gpio_part3) \
/ sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK)
#define exynos5420_gpio_part4_get_nr(bank, pin) \
(((((((unsigned int) &(((struct exynos5420_gpio_part4 *)\
EXYNOS5420_GPIO_PART4_BASE)->bank)) \
- EXYNOS5420_GPIO_PART4_BASE) / sizeof(struct s5p_gpio_bank)) \
* GPIO_PER_BANK) + pin) + EXYNOS5420_GPIO_PART3_MAX)
#define EXYNOS5420_GPIO_PART4_MAX ((sizeof(struct exynos5420_gpio_part4) \
/ sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK)
#define EXYNOS5420_GPIO_PART5_MAX ((sizeof(struct exynos5420_gpio_part5) \
/ sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK)
static inline unsigned int s5p_gpio_base(int nr)
{
if (cpu_is_exynos5()) {
if (nr < EXYNOS5_GPIO_PART1_MAX)
return EXYNOS5_GPIO_PART1_BASE;
else if (nr < EXYNOS5_GPIO_PART2_MAX)
return EXYNOS5_GPIO_PART2_BASE;
else
return EXYNOS5_GPIO_PART3_BASE;
if (proid_is_exynos5420()) {
if (nr < EXYNOS5420_GPIO_PART1_MAX)
return EXYNOS5420_GPIO_PART1_BASE;
else if (nr < EXYNOS5420_GPIO_PART2_MAX)
return EXYNOS5420_GPIO_PART2_BASE;
else if (nr < EXYNOS5420_GPIO_PART3_MAX)
return EXYNOS5420_GPIO_PART3_BASE;
else
return EXYNOS5420_GPIO_PART4_BASE;
} else {
if (nr < EXYNOS5_GPIO_PART1_MAX)
return EXYNOS5_GPIO_PART1_BASE;
else if (nr < EXYNOS5_GPIO_PART2_MAX)
return EXYNOS5_GPIO_PART2_BASE;
else
return EXYNOS5_GPIO_PART3_BASE;
}
} else if (cpu_is_exynos4()) {
if (nr < EXYNOS4_GPIO_PART1_MAX)
return EXYNOS4_GPIO_PART1_BASE;
@ -282,13 +385,25 @@ static inline unsigned int s5p_gpio_base(int nr)
static inline unsigned int s5p_gpio_part_max(int nr)
{
if (cpu_is_exynos5()) {
if (nr < EXYNOS5_GPIO_PART1_MAX)
return 0;
else if (nr < EXYNOS5_GPIO_PART2_MAX)
return EXYNOS5_GPIO_PART1_MAX;
else
return EXYNOS5_GPIO_PART2_MAX;
if (proid_is_exynos5420()) {
if (nr < EXYNOS5420_GPIO_PART1_MAX)
return 0;
else if (nr < EXYNOS5420_GPIO_PART2_MAX)
return EXYNOS5420_GPIO_PART1_MAX;
else if (nr < EXYNOS5420_GPIO_PART3_MAX)
return EXYNOS5420_GPIO_PART2_MAX;
else if (nr < EXYNOS5420_GPIO_PART4_MAX)
return EXYNOS5420_GPIO_PART3_MAX;
else
return EXYNOS5420_GPIO_PART4_MAX;
} else {
if (nr < EXYNOS5_GPIO_PART1_MAX)
return 0;
else if (nr < EXYNOS5_GPIO_PART2_MAX)
return EXYNOS5_GPIO_PART1_MAX;
else
return EXYNOS5_GPIO_PART2_MAX;
}
} else if (cpu_is_exynos4()) {
if (proid_is_exynos4412()) {
if (nr < EXYNOS4X12_GPIO_PART1_MAX)

3
arch/arm/include/asm/arch-exynos/periph.h
View File

@ -34,6 +34,9 @@ enum periph_id {
PERIPH_ID_SDMMC1,
PERIPH_ID_SDMMC2,
PERIPH_ID_SDMMC3,
PERIPH_ID_I2C8 = 87,
PERIPH_ID_I2C9,
PERIPH_ID_I2C10 = 203,
PERIPH_ID_I2S0 = 98,
PERIPH_ID_I2S1 = 99,

837
arch/arm/include/asm/arch-exynos/power.h
View File

@ -831,6 +831,843 @@ struct exynos5_power {
unsigned int cmu_reset_mau_option;
unsigned char res163[0x24];
};
struct exynos5420_power {
unsigned int om_stat;
unsigned int lpi_mask0;
unsigned int lpi_mask1;
unsigned char res1[0x10];
unsigned int rtc_clko_sel;
unsigned char res2[0x1e0];
unsigned int central_seq_configuration;
unsigned int central_seq_status;
unsigned int central_seq_option;
unsigned char res3[0x14];
unsigned int seq_transition0;
unsigned int seq_transition1;
unsigned int seq_transition2;
unsigned int seq_transition3;
unsigned int seq_transition4;
unsigned int seq_transition5;
unsigned int seq_transition6;
unsigned int seq_transition7;
unsigned int central_seq_coreblk_configuration;
unsigned int central_seq_coreblk_status;
unsigned int central_seq_coreblk_option;
unsigned char res4[0x14];
unsigned int seq_coreblk_transition0;
unsigned int seq_coreblk_transition1;
unsigned int seq_coreblk_transition2;
unsigned int seq_coreblk_transition3;
unsigned int seq_coreblk_transition4;
unsigned int seq_coreblk_transition5;
unsigned int seq_coreblk_transition6;
unsigned int seq_coreblk_transition7;
unsigned char res5[0x180];
unsigned int swreset;
unsigned int rst_stat;
unsigned int automatic_wdt_reset_disable;
unsigned int mask_wdt_reset_request;
unsigned int mask_wreset_request;
unsigned char res6[0xec];
unsigned int reset_sequencer_configuration;
unsigned int reset_sequencer_status;
unsigned int reset_sequencer_option;
unsigned char res7[0xf4];
unsigned int wakeup_stat;
unsigned int eint_wakeup_mask;
unsigned int wakeup_mask;
unsigned int wakeup_interrupt;
unsigned char res8[0x10];
unsigned int wakeup_stat_coreblk;
unsigned int eint_wakeup_mask_coreblk;
unsigned int wakeup_mask_coreblk;
unsigned int wakeup_interrupt_coreblk;
unsigned char res9[0xd0];
unsigned int hdmi_phy_control;
unsigned int usbdev_phy_control;
unsigned int usbdev1_phy_control;
unsigned int usbhost_phy_control;
unsigned char res104[0x4];
unsigned int mipi_phy0_control;
unsigned int mipi_phy1_control;
unsigned int mipi_phy2_control;
unsigned int adc_phy_control;
unsigned int mtcadc_phy_control;
unsigned int dptx_phy_control;
unsigned char res10[0xd4];
unsigned int inform0;
unsigned int inform1;
unsigned int inform2;
unsigned int inform3;
unsigned int sysip_dat0;
unsigned int sysip_dat1;
unsigned int sysip_dat2;
unsigned int sysip_dat3;
unsigned char res11[0xe0];
unsigned int pmu_spare0;
unsigned int pmu_spare1;
unsigned int pmu_spare2;
unsigned int pmu_spare3;
unsigned char res12[0x4];
unsigned int cg_status0;
unsigned int cg_status1;
unsigned int cg_status2;
unsigned int cg_status3;
unsigned int cg_status4;
unsigned char res200[0x58];
unsigned int irom_data_reg0;
unsigned int irom_data_reg1;
unsigned int irom_data_reg2;
unsigned int irom_data_reg3;
unsigned char res13[0x70];
unsigned int pmu_debug;
unsigned char res14[0x5fc];
unsigned int arm_core0_sys_pwr_reg;
unsigned char res500[0xc];
unsigned int arm_core1_sys_pwr_reg;
unsigned char res501[0xc];
unsigned int arm_core2_sys_pwr_reg;
unsigned char res502[0xc];
unsigned int arm_core3_sys_pwr_reg;
unsigned char res503[0xc];
unsigned int kfc_core0_sys_pwr_reg;
unsigned char res504[0xc];
unsigned int kfc_core1_sys_pwr_reg;
unsigned char res505[0xc];
unsigned int kfc_core2_sys_pwr_reg;
unsigned char res506[0xc];
unsigned int kfc_core3_sys_pwr_reg;
unsigned char res507[0x1c];
unsigned int isp_arm_sys_pwr_reg;
unsigned char res18[0xc];
unsigned int arm_common_sys_pwr_reg;
unsigned char res508[0xc];
unsigned int kfc_common_sys_pwr_reg;
unsigned char res19[0xc];
unsigned int arm_l2_sys_pwr_reg;
unsigned char res509[0xc];
unsigned int kfc_l2_sys_pwr_reg;
unsigned char res20[0xc];
unsigned int cmu_cpu_aclkstop_sys_pwr_reg;
unsigned int cmu_cpu_sclkstop_sys_pwr_reg;
unsigned char res510[0x8];
unsigned int cmu_kfc_aclkstop_sys_pwr_reg;
unsigned char res511[0xc];
unsigned int cmu_aclkstop_sys_pwr_reg;
unsigned int cmu_sclkstop_sys_pwr_reg;
unsigned char res21[0x4];
unsigned int cmu_reset_sys_pwr_reg;
unsigned char res22[0x10];
unsigned int cmu_aclkstop_coreblk_sys_pwr_reg;
unsigned int cmu_sclkstop_coreblk_sys_pwr_reg;
unsigned char res23[0x4];
unsigned int cmu_reset_coreblk_sys_pwr_reg;
unsigned int dram_freq_down_sys_pwr_reg;
unsigned int ddrphy_dlloff_sys_pwr_reg;
unsigned int ddrphy_dlllock_sys_pwr_reg;
unsigned char res25[0x4];
unsigned int apll_sysclk_sys_pwr_reg;
unsigned int mpll_sysclk_sys_pwr_reg;
unsigned int vpll_sysclk_sys_pwr_reg;
unsigned int epll_sysclk_sys_pwr_reg;
unsigned int bpll_sysclk_sys_pwr_reg;
unsigned int cpll_sysclk_sys_pwr_reg;
unsigned int dpll_sysclk_sys_pwr_reg;
unsigned int ipll_sysclk_sys_pwr_reg;
unsigned int kpll_sysclk_sys_pwr_reg;
unsigned int mplluser_sysclk_sys_pwr_reg;
unsigned char res512[0x8];
unsigned int bplluser_sysclk_sys_pwr_reg;
unsigned int rpll_sysclk_sys_pwr_reg;
unsigned int spll_sysclk_sys_pwr_reg;
unsigned char res26[0x4];
unsigned int top_bus_sys_pwr_reg;
unsigned int top_retention_sys_pwr_reg;
unsigned int top_pwr_sys_pwr_reg;
unsigned char res29[0x4];
unsigned int top_bus_coreblk_sys_pwr_reg;
unsigned int top_retention_coreblk_sys_pwr_reg;
unsigned int top_pwr_coreblk_sys_pwr_reg;
unsigned char res30[0x4];
unsigned int logic_reset_sys_pwr_reg;
unsigned int oscclk_gate_sys_pwr_reg;
unsigned char res31[0x8];
unsigned int logic_reset_coreblk_sys_pwr_reg;
unsigned int oscclk_gate_coreblk_sys_pwr_reg;
unsigned int intram_mem_sys_pwr_reg;
unsigned int introm_mem_sys_pwr_reg;
unsigned char res32[0x44];
unsigned int pad_retention_mau_sys_pwr_reg;
unsigned int pad_retention_jtag_sys_pwr_reg;
unsigned char res36[0x4];
unsigned int pad_retention_dram_sys_pwr_reg;
unsigned int pad_retention_uart_sys_pwr_reg;
unsigned int pad_retention_mmca_sys_pwr_reg;
unsigned int pad_retention_mmcb_sys_pwr_reg;
unsigned int pad_retention_mmcc_sys_pwr_reg;
unsigned int pad_retention_hsi_sys_pwr_reg;
unsigned int pad_retention_ebia_sys_pwr_reg;
unsigned int pad_retention_ebib_sys_pwr_reg;
unsigned int pad_retention_spi_sys_pwr_reg;
unsigned int pad_retention_dram_coreblk_sys_pwr_reg;
unsigned char res28[0x8];
unsigned int pad_isolation_sys_pwr_reg;
unsigned char res37[0xc];
unsigned int pad_isolation_coreblk_sys_pwr_reg;
unsigned char res38[0xc];
unsigned int pad_alv_sel_sys_pwr_reg;
unsigned char res39[0x1c];
unsigned int xusbxti_sys_pwr_reg;
unsigned int xxti_sys_pwr_reg;
unsigned char res40[0x38];
unsigned int ext_regulator_sys_pwr_reg;
unsigned char res41[0x3c];
unsigned int gpio_mode_sys_pwr_reg;
unsigned char res42[0x1c];
unsigned int gpio_mode_coreblk_sys_pwr_reg;
unsigned char res43[0x1c];
unsigned int gpio_mode_mau_sys_pwr_reg;
unsigned int top_asb_reset_sys_pwr_reg;
unsigned int top_asb_isolation_sys_pwr_reg;
unsigned char res44[0xb4];
unsigned int gscl_sys_pwr_reg;
unsigned int isp_sys_pwr_reg;
unsigned int mfc_sys_pwr_reg;
unsigned int g3d_sys_pwr_reg;
unsigned int disp1_sys_pwr_reg;
unsigned int mau_sys_pwr_reg;
unsigned int g2d_sys_pwr_reg;
unsigned int msc_sys_pwr_reg;
unsigned int fsys_sys_pwr_reg;
unsigned int fsys2_sys_pwr_reg;
unsigned int psgen_sys_pwr_reg;
unsigned int peric_sys_pwr_reg;
unsigned int wcore_sys_pwr_reg;
unsigned char res46[0x4c];
unsigned int cmu_clkstop_gscl_sys_pwr_reg;
unsigned int cmu_clkstop_isp_sys_pwr_reg;
unsigned int cmu_clkstop_mfc_sys_pwr_reg;
unsigned int cmu_clkstop_g3d_sys_pwr_reg;
unsigned int cmu_clkstop_disp1_sys_pwr_reg;
unsigned int cmu_clkstop_mau_sys_pwr_reg;
unsigned int cmu_clkstop_g2d_sys_pwr_reg;
unsigned int cmu_clkstop_msc_sys_pwr_reg;
unsigned int cmu_clkstop_fsys_sys_pwr_reg;
unsigned int cmu_clkstop_fsys2_sys_pwr_reg;
unsigned int cmu_clkstop_psgen_sys_pwr_reg;
unsigned int cmu_clkstop_peric_sys_pwr_reg;
unsigned int cmu_clkstop_wcore_sys_pwr_reg;
unsigned char res48[0x8];
unsigned int cmu_sysclk_toppwr_sys_pwr_reg;
unsigned int cmu_sysclk_gscl_sys_pwr_reg;
unsigned int cmu_sysclk_isp_sys_pwr_reg;
unsigned int cmu_sysclk_mfc_sys_pwr_reg;
unsigned int cmu_sysclk_g3d_sys_pwr_reg;
unsigned int cmu_sysclk_disp1_sys_pwr_reg;
unsigned int cmu_sysclk_mau_sys_pwr_reg;
unsigned int cmu_sysclk_g2d_sys_pwr_reg;
unsigned int cmu_sysclk_msc_sys_pwr_reg;
unsigned int cmu_sysclk_fsys_sys_pwr_reg;
unsigned int cmu_sysclk_fsys2_sys_pwr_reg;
unsigned int cmu_sysclk_psgen_sys_pwr_reg;
unsigned int cmu_sysclk_peric_sys_pwr_reg;
unsigned int cmu_sysclk_wcore_sys_pwr_reg;
unsigned int cmu_sysclk_coreblk_toppwr_sys_pwr_reg;
unsigned char res50[0x78];
unsigned int cmu_reset_fsys2_sys_pwr_reg;
unsigned int cmu_reset_psgen_sys_pwr_reg;
unsigned int cmu_reset_peric_sys_pwr_reg;
unsigned int cmu_reset_wcore_sys_pwr_reg;
unsigned int cmu_reset_gscl_sys_pwr_reg;
unsigned int cmu_reset_isp_sys_pwr_reg;
unsigned int cmu_reset_mfc_sys_pwr_reg;
unsigned int cmu_reset_g3d_sys_pwr_reg;
unsigned int cmu_reset_disp1_sys_pwr_reg;
unsigned int cmu_reset_mau_sys_pwr_reg;
unsigned int cmu_reset_g2d_sys_pwr_reg;
unsigned int cmu_reset_msc_sys_pwr_reg;
unsigned int cmu_reset_fsys_sys_pwr_reg;
unsigned char res52[0xa5c];
unsigned int arm_core0_configuration;
unsigned int arm_core0_status;
unsigned int arm_core0_option;
unsigned char res53[0x14];
unsigned int dis_irq_arm_core0_local_configuration;
unsigned int dis_irq_arm_core0_local_status;
unsigned int dis_irq_arm_core0_local_option;
unsigned char res54[0x14];
unsigned int dis_irq_arm_core0_central_configuration;
unsigned int dis_irq_arm_core0_central_status;
unsigned int dis_irq_arm_core0_central_option;
unsigned char res55[0x34];
unsigned int arm_core1_configuration;
unsigned int arm_core1_status;
unsigned int arm_core1_option;
unsigned char res56[0x14];
unsigned int dis_irq_arm_core1_local_configuration;
unsigned int dis_irq_arm_core1_local_status;
unsigned int dis_irq_arm_core1_local_option;
unsigned char res57[0x14];
unsigned int dis_irq_arm_core1_central_configuration;
unsigned int dis_irq_arm_core1_central_status;
unsigned int dis_irq_arm_core1_central_option;
unsigned char res600[0x34];
unsigned int arm_core2_configuration;
unsigned int arm_core2_status;
unsigned int arm_core2_option;
unsigned char res601[0x14];
unsigned int dis_irq_arm_core2_local_configuration;
unsigned int dis_irq_arm_core2_local_status;
unsigned int dis_irq_arm_core2_local_option;
unsigned char res602[0x14];
unsigned int dis_irq_arm_core2_central_configuration;
unsigned int dis_irq_arm_core2_central_status;
unsigned int dis_irq_arm_core2_central_option;
unsigned char res603[0x34];
unsigned int arm_core3_configuration;
unsigned int arm_core3_status;
unsigned int arm_core3_option;
unsigned char res900[0x14];
unsigned int dis_irq_arm_core3_local_configuration;
unsigned int dis_irq_arm_core3_local_status;
unsigned int dis_irq_arm_core3_local_option;
unsigned char res901[0x14];
unsigned int dis_irq_arm_core3_central_configuration;
unsigned int dis_irq_arm_core3_central_status;
unsigned int dis_irq_arm_core3_central_option;
unsigned char res604[0x34];
unsigned int kfc_core0_configuration;
unsigned int kfc_core0_status;
unsigned int kfc_core0_option;
unsigned char res605[0x14];
unsigned int dis_irq_kfc_core0_local_configuration;
unsigned int dis_irq_kfc_core0_local_status;
unsigned int dis_irq_kfc_core0_local_option;
unsigned char res606[0x14];
unsigned int dis_irq_kfc_core0_central_configuration;
unsigned int dis_irq_kfc_core0_central_status;
unsigned int dis_irq_kfc_core0_central_option;
unsigned char res607[0x34];
unsigned int kfc_core1_configuration;
unsigned int kfc_core1_status;
unsigned int kfc_core1_option;
unsigned char res608[0x14];
unsigned int dis_irq_kfc_core1_local_configuration;
unsigned int dis_irq_kfc_core1_local_status;
unsigned int dis_irq_kfc_core1_local_option;
unsigned char res609[0x14];
unsigned int dis_irq_kfc_core1_central_configuration;
unsigned int dis_irq_kfc_core1_central_status;
unsigned int dis_irq_kfc_core1_central_option;
unsigned char res610[0x34];
unsigned int kfc_core2_configuration;
unsigned int kfc_core2_status;
unsigned int kfc_core2_option;
unsigned char res611[0x14];
unsigned int dis_irq_kfc_core2_local_configuration;
unsigned int dis_irq_kfc_core2_local_status;
unsigned int dis_irq_kfc_core2_local_option;
unsigned char res612[0x14];
unsigned int dis_irq_kfc_core2_central_configuration;
unsigned int dis_irq_kfc_core2_central_status;
unsigned int dis_irq_kfc_core2_central_option;
unsigned char res613[0x34];
unsigned int kfc_core3_configuration;
unsigned int kfc_core3_status;
unsigned int kfc_core3_option;
unsigned char res614[0x14];
unsigned int dis_irq_kfc_core3_local_configuration;
unsigned int dis_irq_kfc_core3_local_status;
unsigned int dis_irq_kfc_core3_local_option;
unsigned char res615[0x14];
unsigned int dis_irq_kfc_core3_central_configuration;
unsigned int dis_irq_kfc_core3_central_status;
unsigned int dis_irq_kfc_core3_central_option;
unsigned char res61[0xb4];
unsigned int isp_arm_configuration;
unsigned int isp_arm_status;
unsigned int isp_arm_option;
unsigned char res62[0x14];
unsigned int dis_irq_isp_arm_local_configuration;
unsigned int dis_irq_isp_arm_local_status;
unsigned int dis_irq_isp_arm_local_option;
unsigned char res63[0x14];
unsigned int dis_irq_isp_arm_central_configuration;
unsigned int dis_irq_isp_arm_central_status;
unsigned int dis_irq_isp_arm_central_option;
unsigned char res64[0x34];
unsigned int arm_common_configuration;
unsigned int arm_common_status;
unsigned int arm_common_option;
unsigned char res616[0x74];
unsigned int kfc_common_configuration;
unsigned int kfc_common_status;
unsigned int kfc_common_option;
unsigned char res65[0x74];
unsigned int arm_l2_configuration;
unsigned int arm_l2_status;
unsigned int arm_l2_option;
unsigned char res617[0x74];
unsigned int kfc_l2_configuration;
unsigned int kfc_l2_status;
unsigned int kfc_l2_option;
unsigned char res66[0x74];
unsigned int cmu_cpu_aclkstop_configuration;
unsigned int cmu_cpu_aclkstop_status;
unsigned int cmu_cpu_aclkstop_option;
unsigned char res67[0x14];
unsigned int cmu_cpu_sclkstop_configuration;
unsigned int cmu_cpu_sclkstop_status;
unsigned int cmu_cpu_sclkstop_option;
unsigned char res618[0x4];
unsigned int cmu_kfc_aclkstop_configuration;
unsigned int cmu_kfc_aclkstop_status;
unsigned int cmu_kfc_aclkstop_option;
unsigned char res619[0xc4];
unsigned int cmu_aclkstop_configuration;
unsigned int cmu_aclkstop_status;
unsigned int cmu_aclkstop_option;
unsigned char res620[0x14];
unsigned int cmu_sclkstop_configuration;
unsigned int cmu_sclkstop_status;
unsigned int cmu_sclkstop_option;
unsigned char res68[0x34];
unsigned int cmu_reset_configuration;
unsigned int cmu_reset_status;
unsigned int cmu_reset_option;
unsigned char res69[0x94];
unsigned int cmu_aclkstop_coreblk_configuration;
unsigned int cmu_aclkstop_coreblk_status;
unsigned int cmu_aclkstop_coreblk_option;
unsigned char res70[0x14];
unsigned int cmu_sclkstop_coreblk_configuration;
unsigned int cmu_sclkstop_coreblk_status;
unsigned int cmu_sclkstop_coreblk_option;
unsigned char res71[0x34];
unsigned int cmu_reset_coreblk_configuration;
unsigned int cmu_reset_coreblk_status;
unsigned int cmu_reset_coreblk_option;
unsigned char res621[0x14];
unsigned int dram_freq_down_configuration;
unsigned int dram_freq_down_status;
unsigned int dram_freq_down_option;
unsigned char res622[0x14];
unsigned int ddrphy_dlloff_configuration;
unsigned int ddrphy_dlloff_status;
unsigned int ddrphy_dlloff_option;
unsigned char res72[0x14];
unsigned int ddrphy_dlllock_configuration;
unsigned int ddrphy_dlllock_status;
unsigned int ddrphy_dlllock_option;
unsigned char res73[0x34];
unsigned int apll_sysclk_configuration;
unsigned int apll_sysclk_status;
unsigned int apll_sysclk_option;
unsigned char res74[0x18];
unsigned int mpll_sysclk_status;
unsigned int mpll_sysclk_option;
unsigned char res75[0x14];
unsigned int vpll_sysclk_configuration;
unsigned int vpll_sysclk_status;
unsigned int vpll_sysclk_option;
unsigned char res76[0x14];
unsigned int epll_sysclk_configuration;
unsigned int epll_sysclk_status;
unsigned int epll_sysclk_option;
unsigned char res77[0x14];
unsigned int bpll_sysclk_configuration;
unsigned int bpll_sysclk_status;
unsigned int bpll_sysclk_option;
unsigned char res78[0x14];
unsigned int cpll_sysclk_configuration;
unsigned int cpll_sysclk_status;
unsigned int cpll_sysclk_option;
unsigned char res79[0x14];
unsigned int dpll_sysclk_configuration;
unsigned int dpll_sysclk_status;
unsigned int dpll_sysclk_option;
unsigned char res700[0x14];
unsigned int ipll_sysclk_configuration;
unsigned int ipll_sysclk_status;
unsigned int ipll_sysclk_option;
unsigned char res903[0x14];
unsigned int kpll_sysclk_configuration;
unsigned int kpll_sysclk_status;
unsigned int kpll_sysclk_option;
unsigned char res80[0x14];
unsigned int mplluser_sysclk_configuration;
unsigned int mplluser_sysclk_status;
unsigned int mplluser_sysclk_option;
unsigned char res81[0x54];
unsigned int bplluser_sysclk_configuration;
unsigned int bplluser_sysclk_status;
unsigned int bplluser_sysclk_option;
unsigned char res701[0x14];
unsigned int rplluser_sysclk_configuration;
unsigned int rplluser_sysclk_status;
unsigned int rplluser_sysclk_option;
unsigned char res702[0x14];
unsigned int splluser_sysclk_configuration;
unsigned int splluser_sysclk_status;
unsigned int splluser_sysclk_option;
unsigned char res82[0x34];
unsigned int top_bus_configuration;
unsigned int top_bus_status;
unsigned int top_bus_option;
unsigned char res83[0x14];
unsigned int top_retention_configuration;
unsigned int top_retention_status;
unsigned int top_retention_option;
unsigned char res84[0x14];
unsigned int top_pwr_configuration;
unsigned int top_pwr_status;
unsigned int top_pwr_option;
unsigned char res85[0x34];
unsigned int top_bus_coreblk_configuration;
unsigned int top_bus_coreblk_status;
unsigned int top_bus_coreblk_option;
unsigned char res86[0x14];
unsigned int top_retention_coreblk_configuration;
unsigned int top_retention_coreblk_status;
unsigned int top_retention_coreblk_option;
unsigned char res87[0x14];
unsigned int top_pwr_coreblk_configuration;
unsigned int top_pwr_coreblk_status;
unsigned int top_pwr_coreblk_option;
unsigned char res88[0x34];
unsigned int logic_reset_configuration;
unsigned int logic_reset_status;
unsigned int logic_reset_option;
unsigned char res89[0x14];
unsigned int oscclk_gate_configuration;
unsigned int oscclk_gate_status;
unsigned int oscclk_gate_option;
unsigned char res90[0x54];
unsigned int logic_reset_coreblk_configuration;
unsigned int logic_reset_coreblk_status;
unsigned int logic_reset_coreblk_option;
unsigned char res91[0x14];
unsigned int oscclk_gate_coreblk_configuration;
unsigned int oscclk_gate_coreblk_status;
unsigned int oscclk_gate_coreblk_option;
unsigned char res99[0x174];
unsigned int intram_mem_configuration;
unsigned int intram_mem_status;
unsigned int intram_mem_option;
unsigned char res100[0x14];
unsigned int introm_mem_configuration;
unsigned int introm_mem_status;
unsigned int introm_mem_option;
unsigned char res101[0xb4];
unsigned int pad_retention_dram_configuration;
unsigned int pad_retention_dram_status;
unsigned int pad_retention_dram_option;
unsigned char res106[0x14];
unsigned int pad_retention_mau_configuration;
unsigned int pad_retention_mau_status;
unsigned int pad_retention_mau_option;
unsigned char res107[0x14];
unsigned int pad_retention_jtag_configuration;
unsigned int pad_retention_jtag_status;
unsigned int pad_retention_jtag_option;
unsigned char res92[0x74];
unsigned int pad_retention_dram_configuration_2;
unsigned int pad_retention_dram_status_2;
unsigned int pad_retention_dram_option_2;
unsigned char res111[0x14];
unsigned int pad_retention_uart_configuration;
unsigned int pad_retention_uart_status;
unsigned int pad_retention_uart_option;
unsigned char res112[0x14];
unsigned int pad_retention_mmca_configuration;
unsigned int pad_retention_mmca_status;
unsigned int pad_retention_mmca_option;
unsigned char res113[0x14];
unsigned int pad_retention_mmcb_configuration;
unsigned int pad_retention_mmcb_status;
unsigned int pad_retention_mmcb_option;
unsigned char res93[0x14];
unsigned int pad_retention_mmcc_configuration;
unsigned int pad_retention_mmcc_status;
unsigned int pad_retention_mmcc_option;
unsigned char res94[0x14];
unsigned int pad_retention_hsi_configuration;
unsigned int pad_retention_hsi_status;
unsigned int pad_retention_hsi_option;
unsigned char res114[0x14];
unsigned int pad_retention_ebia_configuration;
unsigned int pad_retention_ebia_status;
unsigned int pad_retention_ebia_option;
unsigned char res115[0x14];
unsigned int pad_retention_ebib_configuration;
unsigned int pad_retention_ebib_status;
unsigned int pad_retention_ebib_option;
unsigned char res116[0x14];
unsigned int pad_retention_spi_configuration;
unsigned int pad_retention_spi_status;
unsigned int pad_retention_spi_option;
unsigned char res117[0x14];
unsigned int pad_retention_dram_coreblk_configuration;
unsigned int pad_retention_dram_coreblk_status;
unsigned int pad_retention_dram_coreblk_option;
unsigned char res118[0x14];
unsigned int pad_isolation_configuration;
unsigned int pad_isolation_status;
unsigned int pad_isolation_option;
unsigned char res119[0x74];
unsigned int pad_isolation_coreblk_configuration;
unsigned int pad_isolation_coreblk_status;
unsigned int pad_isolation_coreblk_option;
unsigned char res120[0x74];
unsigned int pad_alv_sel_configuration;
unsigned int pad_alv_sel_status;
unsigned int pad_alv_sel_option0;
unsigned int ps_hold_control;
unsigned char res130[0xf0];
unsigned int xusbxti_configuration;
unsigned int xusbxti_status;
unsigned int xusbxti_option;
unsigned char res910[0x10];
unsigned int xusbxti_duration3;
unsigned int xxti_configuration;
unsigned int xxti_status;
unsigned int xxti_option;
unsigned char res131[0x10];
unsigned int xxti_duration3;
unsigned char res132[0x1c0];
unsigned int ext_regulator_configuration;
unsigned int ext_regulator_status;
unsigned int ext_regulator_option;
unsigned char res133[0x10];
unsigned int ext_regulator_duration3;
unsigned char res134[0x1e0];
unsigned int gpio_mode_configuration;
unsigned int gpio_mode_status;
unsigned int gpio_mode_option;
unsigned char res135[0xf4];
unsigned int gpio_mode_coreblk_configuration;
unsigned int gpio_mode_coreblk_status;
unsigned int gpio_mode_coreblk_option;
unsigned char res136[0xd4];
unsigned int gpio_mode_mau_configuration;
unsigned int gpio_mode_mau_status;
unsigned int gpio_mode_mau_option;
unsigned char res137[0x14];
unsigned int top_asb_reset_configuration;
unsigned int top_asb_reset_status;
unsigned int top_asb_reset_option;
unsigned char res138[0x14];
unsigned int top_asb_isolation_configuration;
unsigned int top_asb_isolation_status;
unsigned int top_asb_isolation_option;
unsigned char res139[0x5d4];
unsigned int gscl_configuration;
unsigned int gscl_status;
unsigned int gscl_option;
unsigned char res140[0x14];
unsigned int isp_configuration;
unsigned int isp_status;
unsigned int isp_option;
unsigned char res141[0x34];
unsigned int mfc_configuration;
unsigned int mfc_status;
unsigned int mfc_option;
unsigned char res142[0x14];
unsigned int g3d_configuration;
unsigned int g3d_status;
unsigned int g3d_option;
unsigned char res143[0x34];
unsigned int disp1_configuration;
unsigned int disp1_status;
unsigned int disp1_option;
unsigned char res144[0x14];
unsigned int mau_configuration;
unsigned int mau_status;
unsigned int mau_option;
unsigned char res800[0x14];
unsigned int g2d_configuration;
unsigned int g2d_status;
unsigned int g2d_option;
unsigned char res801[0x14];
unsigned int msc_configuration;
unsigned int msc_status;
unsigned int msc_option;
unsigned char res802[0x14];
unsigned int fsys_configuration;
unsigned int fsys_status;
unsigned int fsys_option;
unsigned char res803[0x14];
unsigned int fsys2_configuration;
unsigned int fsys2_status;
unsigned int fsys2_option;
unsigned char res804[0x14];
unsigned int psgen_configuration;
unsigned int psgen_status;
unsigned int psgen_option;
unsigned char res805[0x14];
unsigned int peric_configuration;
unsigned int peric_status;
unsigned int peric_option;
unsigned char res806[0x14];
unsigned int wcore_configuration;
unsigned int wcore_status;
unsigned int wcore_option;
unsigned char res145[0x234];
unsigned int cmu_clkstop_gscl_configuration;
unsigned int cmu_clkstop_gscl_status;
unsigned int cmu_clkstop_gscl_option;
unsigned char res146[0x14];
unsigned int cmu_clkstop_isp_configuration;
unsigned int cmu_clkstop_isp_status;
unsigned int cmu_clkstop_isp_option;
unsigned char res147[0x34];
unsigned int cmu_clkstop_mfc_configuration;
unsigned int cmu_clkstop_mfc_status;
unsigned int cmu_clkstop_mfc_option;
unsigned char res148[0x14];
unsigned int cmu_clkstop_g3d_configuration;
unsigned int cmu_clkstop_g3d_status;
unsigned int cmu_clkstop_g3d_option;
unsigned char res149[0x34];
unsigned int cmu_clkstop_disp1_configuration;
unsigned int cmu_clkstop_disp1_status;
unsigned int cmu_clkstop_disp1_option;
unsigned char res150[0x14];
unsigned int cmu_clkstop_mau_configuration;
unsigned int cmu_clkstop_mau_status;
unsigned int cmu_clkstop_mau_option;
unsigned char res807[0x14];
unsigned int cmu_clkstop_g2d_configuration;
unsigned int cmu_clkstop_g2d_status;
unsigned int cmu_clkstop_g2d_option;
unsigned char res808[0x14];
unsigned int cmu_clkstop_msc_configuration;
unsigned int cmu_clkstop_msc_status;
unsigned int cmu_clkstop_msc_option;
unsigned char res809[0x14];
unsigned int cmu_clkstop_fsys_configuration;
unsigned int cmu_clkstop_fsys_status;
unsigned int cmu_clkstop_fsys_option;
unsigned char res810[0x14];
unsigned int cmu_clkstop_fsys2_configuration;
unsigned int cmu_clkstop_fsys2_status;
unsigned int cmu_clkstop_fsys2_option;
unsigned char res811[0x14];
unsigned int cmu_clkstop_psgen_configuration;
unsigned int cmu_clkstop_psgen_status;
unsigned int cmu_clkstop_psgen_option;
unsigned char res812[0x14];
unsigned int cmu_clkstop_peric_configuration;
unsigned int cmu_clkstop_peric_status;
unsigned int cmu_clkstop_peric_option;
unsigned char res813[0x14];
unsigned int cmu_clkstop_wcore_configuration;
unsigned int cmu_clkstop_wcore_status;
unsigned int cmu_clkstop_wcore_option;
unsigned char res151[0x14];
unsigned int cmu_sysclk_toppwr_configuration;
unsigned int cmu_sysclk_toppwr_status;
unsigned int cmu_sysclk_toppwr_option;
unsigned char res920[0x18];
unsigned int cmu_sysclk_gscl_status;
unsigned int cmu_sysclk_gscl_option;
unsigned char res152[0x18];
unsigned int cmu_sysclk_isp_status;
unsigned int cmu_sysclk_isp_option;
unsigned char res153[0x38];
unsigned int cmu_sysclk_mfc_status;
unsigned int cmu_sysclk_mfc_option;
unsigned char res154[0x18];
unsigned int cmu_sysclk_g3d_status;
unsigned int cmu_sysclk_g3d_option;
unsigned char res155[0x38];
unsigned int cmu_sysclk_disp1_status;
unsigned int cmu_sysclk_disp1_option;
unsigned char res156[0x18];
unsigned int cmu_sysclk_mau_status;
unsigned int cmu_sysclk_mau_option;
unsigned char res814[0x18];
unsigned int cmu_sysclk_g2d_status;
unsigned int cmu_sysclk_g2d_option;
unsigned char res815[0x18];
unsigned int cmu_sysclk_msc_status;
unsigned int cmu_sysclk_msc_option;
unsigned char res922[0x18];
unsigned int cmu_sysclk_fsys_status;
unsigned int cmu_sysclk_fsys_option;
unsigned char res816[0x18];
unsigned int cmu_sysclk_fsys2_status;
unsigned int cmu_sysclk_fsys2_option;
unsigned char res817[0x18];
unsigned int cmu_sysclk_psgen_status;
unsigned int cmu_sysclk_psgen_option;
unsigned char res950[0x18];
unsigned int cmu_sysclk_peric_status;
unsigned int cmu_sysclk_peric_option;
unsigned char res818[0x18];
unsigned int cmu_sysclk_wcore_status;
unsigned int cmu_sysclk_wcore_option;
unsigned char res819[0x18];
unsigned int cmu_sysclk_coreblk_toppwr_status;
unsigned int cmu_sysclk_coreblk_toppwr_option;
unsigned char res157[0x414];
unsigned int cmu_reset_gscl_configuration;
unsigned int cmu_reset_gscl_status;
unsigned int cmu_reset_gscl_option;
unsigned char res158[0x14];
unsigned int cmu_reset_isp_configuration;
unsigned int cmu_reset_isp_status;
unsigned int cmu_reset_isp_option;
unsigned char res159[0x34];
unsigned int cmu_reset_mfc_configuration;
unsigned int cmu_reset_mfc_status;
unsigned int cmu_reset_mfc_option;
unsigned char res160[0x14];
unsigned int cmu_reset_g3d_configuration;
unsigned int cmu_reset_g3d_status;
unsigned int cmu_reset_g3d_option;
unsigned char res161[0x34];
unsigned int cmu_reset_disp1_configuration;
unsigned int cmu_reset_disp1_status;
unsigned int cmu_reset_disp1_option;
unsigned char res162[0x14];
unsigned int cmu_reset_mau_configuration;
unsigned int cmu_reset_mau_status;
unsigned int cmu_reset_mau_option;
unsigned char res163[0x14];
unsigned int version_info;
unsigned int i2s_bypass;
unsigned int kfc_swreset_mask_from_eagle;
unsigned char res164[0xf4];
unsigned int cmu_reset_g2d_configuration;
unsigned int cmu_reset_g2d_status;
unsigned int cmu_reset_g2d_option;
unsigned char res165[0x14];
unsigned int cmu_reset_msc_configuration;
unsigned int cmu_reset_msc_status;
unsigned int cmu_reset_msc_option;
unsigned char res166[0x14];
unsigned int cmu_reset_fsys_configuration;
unsigned int cmu_reset_fsys_status;
unsigned int cmu_reset_fsys_option;
unsigned char res167[0x14];
unsigned int cmu_reset_fsys2_configuration;
unsigned int cmu_reset_fsys2_status;
unsigned int cmu_reset_fsys2_option;
unsigned char res168[0x14];
unsigned int cmu_reset_psgen_configuration;
unsigned int cmu_reset_psgen_status;
unsigned int cmu_reset_psgen_option;
unsigned char res169[0x14];
unsigned int cmu_reset_peric_configuration;
unsigned int cmu_reset_peric_status;
unsigned int cmu_reset_peric_option;
unsigned char res170[0x14];
unsigned int cmu_reset_wcore_configuration;
unsigned int cmu_reset_wcore_status;
unsigned int cmu_reset_wcore_option;
};
#endif /* __ASSEMBLY__ */
void set_mipi_phy_ctrl(unsigned int dev_index, unsigned int enable);

1
arch/arm/include/asm/arch-mx5/clock.h
View File

@ -53,5 +53,6 @@ void enable_usboh3_clk(bool enable);
void mxc_set_sata_internal_clock(void);
int enable_i2c_clk(unsigned char enable, unsigned i2c_num);
void enable_nfc_clk(unsigned char enable);
void enable_efuse_prog_supply(bool enable);
#endif /* __ASM_ARCH_CLOCK_H */

3
arch/arm/include/asm/arch-mx5/crm_regs.h
View File

@ -305,6 +305,9 @@ struct mxc_ccm_reg {
/* Define the bits in register CCDR */
#define MXC_CCM_CCDR_IPU_HS_MASK (0x1 << 17)
/* Define the bits in register CGPR */
#define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (1 << 4)
/* Define the bits in register CCGRx */
#define MXC_CCM_CCGR_CG_MASK 0x3
#define MXC_CCM_CCGR_CG_OFF 0x0

1
arch/arm/include/asm/arch-mx6/crm_regs.h
View File

@ -890,4 +890,5 @@ struct mxc_ccm_reg {
#define BF_ANADIG_PFD_528_PFD0_FRAC(v) \
(((v) << 0) & BM_ANADIG_PFD_528_PFD0_FRAC)
#define ANADIG_ANA_MISC2_REG1_BO_EN (1 << 13)
#endif /*__ARCH_ARM_MACH_MX6_CCM_REGS_H__ */

23
arch/arm/include/asm/arch-mx6/imx-regs.h
View File

@ -659,5 +659,28 @@ struct wdog_regs {
u16 wmcr; /* Miscellaneous Control */
};
struct gpc_regs {
u32 ctrl; /* 0x000 */
u32 pgr; /* 0x004 */
u32 imr1; /* 0x008 */
u32 imr2; /* 0x00c */
u32 imr3; /* 0x010 */
u32 imr4; /* 0x014 */
u32 isr1; /* 0x018 */
u32 isr2; /* 0x01c */
u32 isr3; /* 0x020 */
u32 isr4; /* 0x024 */
u32 reserved1[0x86];
u32 gpu_ctrl; /* 0x260 */
u32 gpu_pupscr; /* 0x264 */
u32 gpu_pdnscr; /* 0x268 */
u32 gpu_sr; /* 0x26c */
u32 reserved2[0xc];
u32 cpu_ctrl; /* 0x2a0 */
u32 cpu_pupscr; /* 0x2a4 */
u32 cpu_pdnscr; /* 0x2a8 */
u32 cpu_sr; /* 0x2ac */
};
#endif /* __ASSEMBLER__*/
#endif /* __ASM_ARCH_MX6_IMX_REGS_H__ */

33
arch/arm/include/asm/arch-mx6/mx6-pins.h
View File

@ -6,18 +6,37 @@
#ifndef __ASM_ARCH_MX6_PINS_H__
#define __ASM_ARCH_MX6_PINS_H__
#ifdef CONFIG_MX6Q
#include <asm/imx-common/iomux-v3.h>
#define MX6_PAD_DECLARE(prefix, name, pco, mc, mm, sio, si, pc) \
prefix##name = IOMUX_PAD(pco, mc, mm, sio, si, pc)
#ifdef CONFIG_MX6QDL
enum {
#define MX6_PAD_DECL(name, pco, mc, mm, sio, si, pc) \
MX6_PAD_DECLARE(MX6Q_PAD_,name, pco, mc, mm, sio, si, pc),
#include "mx6q_pins.h"
#else
#if defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
#undef MX6_PAD_DECL
#define MX6_PAD_DECL(name, pco, mc, mm, sio, si, pc) \
MX6_PAD_DECLARE(MX6DL_PAD_,name, pco, mc, mm, sio, si, pc),
#include "mx6dl_pins.h"
#else
#if defined(CONFIG_MX6SL)
};
#elif defined(CONFIG_MX6Q)
enum {
#define MX6_PAD_DECL(name, pco, mc, mm, sio, si, pc) \
MX6_PAD_DECLARE(MX6_PAD_,name, pco, mc, mm, sio, si, pc),
#include "mx6q_pins.h"
};
#elif defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
enum {
#define MX6_PAD_DECL(name, pco, mc, mm, sio, si, pc) \
MX6_PAD_DECLARE(MX6_PAD_,name, pco, mc, mm, sio, si, pc),
#include "mx6dl_pins.h"
};
#elif defined(CONFIG_MX6SL)
#include "mx6sl_pins.h"
#else
#error "Please select cpu"
#endif /* CONFIG_MX6SL */
#endif /* CONFIG_MX6DL or CONFIG_MX6S */
#endif /* CONFIG_MX6Q */
#endif /*__ASM_ARCH_MX6_PINS_H__ */

2728
arch/arm/include/asm/arch-mx6/mx6dl_pins.h
View File

File diff suppressed because it is too large Load Diff

2642
arch/arm/include/asm/arch-mx6/mx6q_pins.h
View File

File diff suppressed because it is too large Load Diff

2
arch/arm/include/asm/arch-mx6/sys_proto.h
View File

@ -29,8 +29,6 @@ u32 get_cpu_rev(void);
const char *get_imx_type(u32 imxtype);
unsigned imx_ddr_size(void);
void set_vddsoc(u32 mv);
/*
* Initializes on-chip ethernet controllers.
* to override, implement board_eth_init()

2
arch/arm/include/asm/arch-omap4/omap.h
View File

@ -116,7 +116,7 @@ struct s32ktimer {
*/
#define NON_SECURE_SRAM_START 0x40304000
#define NON_SECURE_SRAM_END 0x4030E000 /* Not inclusive */
#define SRAM_SCRATCH_SPACE_ADDR NON_SECURE_SRAM_START
#define SRAM_SCRATCH_SPACE_ADDR 0x4030C000
/* base address for indirect vectors (internal boot mode) */
#define SRAM_ROM_VECT_BASE 0x4030D000

6
arch/arm/include/asm/arch-tegra/clock.h
View File

@ -113,9 +113,9 @@ void reset_set_enable(enum periph_id periph_id, int enable);
enum crc_reset_id {
/* Things we can hold in reset for each CPU */
crc_rst_cpu = 1,
crc_rst_de = 1 << 2, /* What is de? */
crc_rst_watchdog = 1 << 3,
crc_rst_debug = 1 << 4,
crc_rst_de = 1 << 4, /* What is de? */
crc_rst_watchdog = 1 << 8,
crc_rst_debug = 1 << 12,
};
/**

1
arch/arm/include/asm/arch-tegra/tegra.h
View File

@ -65,6 +65,7 @@ enum {
SKU_ID_T25E = 0x1c,
SKU_ID_T33 = 0x80,
SKU_ID_T30 = 0x81, /* Cardhu value */
SKU_ID_TM30MQS_P_A3 = 0xb1,
SKU_ID_T114_ENG = 0x00, /* Dalmore value, unfused */
SKU_ID_T114_1 = 0x01,
};

25
arch/arm/include/asm/arch-zynq/gpio.h Normal file
View File

@ -0,0 +1,25 @@
/*
* Copyright (c) 2013 Xilinx, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _ZYNQ_GPIO_H
#define _ZYNQ_GPIO_H
inline int gpio_get_value(unsigned gpio)
{
return 0;
}
inline int gpio_set_value(unsigned gpio, int val)
{
return 0;
}
inline int gpio_request(unsigned gpio, const char *label)
{
return 0;
}
#endif /* _ZYNQ_GPIO_H */

1
arch/arm/include/asm/arch-zynq/sys_proto.h
View File

@ -13,6 +13,7 @@ extern void zynq_slcr_cpu_reset(void);
extern void zynq_slcr_gem_clk_setup(u32 gem_id, u32 rclk, u32 clk);
extern void zynq_slcr_devcfg_disable(void);
extern void zynq_slcr_devcfg_enable(void);
extern u32 zynq_slcr_get_boot_mode(void);
extern u32 zynq_slcr_get_idcode(void);
extern void zynq_ddrc_init(void);

111
arch/arm/include/asm/armv8/mmu.h Normal file
View File

@ -0,0 +1,111 @@
/*
* (C) Copyright 2013
* David Feng <fenghua@phytium.com.cn>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _ASM_ARMV8_MMU_H_
#define _ASM_ARMV8_MMU_H_
#ifdef __ASSEMBLY__
#define _AC(X, Y) X
#else
#define _AC(X, Y) (X##Y)
#endif
#define UL(x) _AC(x, UL)
/***************************************************************/
/*
* The following definitions are related each other, shoud be
* calculated specifically.
*/
#define VA_BITS (42) /* 42 bits virtual address */
/* PAGE_SHIFT determines the page size */
#undef PAGE_SIZE
#define PAGE_SHIFT 16
#define PAGE_SIZE (1 << PAGE_SHIFT)
#define PAGE_MASK (~(PAGE_SIZE-1))
/*
* section address mask and size definitions.
*/
#define SECTION_SHIFT 29
#define SECTION_SIZE (UL(1) << SECTION_SHIFT)
#define SECTION_MASK (~(SECTION_SIZE-1))
/***************************************************************/
/*
* Memory types
*/
#define MT_DEVICE_NGNRNE 0
#define MT_DEVICE_NGNRE 1
#define MT_DEVICE_GRE 2
#define MT_NORMAL_NC 3
#define MT_NORMAL 4
#define MEMORY_ATTRIBUTES ((0x00 << (MT_DEVICE_NGNRNE*8)) | \
(0x04 << (MT_DEVICE_NGNRE*8)) | \
(0x0c << (MT_DEVICE_GRE*8)) | \
(0x44 << (MT_NORMAL_NC*8)) | \
(UL(0xff) << (MT_NORMAL*8)))
/*
* Hardware page table definitions.
*
* Level 2 descriptor (PMD).
*/
#define PMD_TYPE_MASK (3 << 0)
#define PMD_TYPE_FAULT (0 << 0)
#define PMD_TYPE_TABLE (3 << 0)
#define PMD_TYPE_SECT (1 << 0)
/*
* Section
*/
#define PMD_SECT_S (3 << 8)
#define PMD_SECT_AF (1 << 10)
#define PMD_SECT_NG (1 << 11)
#define PMD_SECT_PXN (UL(1) << 53)
#define PMD_SECT_UXN (UL(1) << 54)
/*
* AttrIndx[2:0]
*/
#define PMD_ATTRINDX(t) ((t) << 2)
#define PMD_ATTRINDX_MASK (7 << 2)
/*
* TCR flags.
*/
#define TCR_T0SZ(x) ((64 - (x)) << 0)
#define TCR_IRGN_NC (0 << 8)
#define TCR_IRGN_WBWA (1 << 8)
#define TCR_IRGN_WT (2 << 8)
#define TCR_IRGN_WBNWA (3 << 8)
#define TCR_IRGN_MASK (3 << 8)
#define TCR_ORGN_NC (0 << 10)
#define TCR_ORGN_WBWA (1 << 10)
#define TCR_ORGN_WT (2 << 10)
#define TCR_ORGN_WBNWA (3 << 10)
#define TCR_ORGN_MASK (3 << 10)
#define TCR_SHARED_NON (0 << 12)
#define TCR_SHARED_OUTER (1 << 12)
#define TCR_SHARED_INNER (2 << 12)
#define TCR_TG0_4K (0 << 14)
#define TCR_TG0_64K (1 << 14)
#define TCR_TG0_16K (2 << 14)
#define TCR_EL1_IPS_BITS (UL(3) << 32) /* 42 bits physical address */
#define TCR_EL2_IPS_BITS (3 << 16) /* 42 bits physical address */
#define TCR_EL3_IPS_BITS (3 << 16) /* 42 bits physical address */
/* PTWs cacheable, inner/outer WBWA and non-shareable */
#define TCR_FLAGS (TCR_TG0_64K | \
TCR_SHARED_NON | \
TCR_ORGN_WBWA | \
TCR_IRGN_WBWA | \
TCR_T0SZ(VA_BITS))
#endif /* _ASM_ARMV8_MMU_H_ */

2
arch/arm/include/asm/byteorder.h
View File

@ -23,7 +23,7 @@
# define __SWAB_64_THRU_32__
#endif
#ifdef __ARMEB__
#if defined(__ARMEB__) || defined(__AARCH64EB__)
#include <linux/byteorder/big_endian.h>
#else
#include <linux/byteorder/little_endian.h>

5
arch/arm/include/asm/cache.h
View File

@ -11,6 +11,8 @@
#include <asm/system.h>
#ifndef CONFIG_ARM64
/*
* Invalidate L2 Cache using co-proc instruction
*/
@ -28,6 +30,9 @@ void l2_cache_disable(void);
void set_section_dcache(int section, enum dcache_option option);
void dram_bank_mmu_setup(int bank);
#endif
/*
* The current upper bound for ARM L1 data cache line sizes is 64 bytes. We
* use that value for aligning DMA buffers unless the board config has specified

6
arch/arm/include/asm/config.h
View File

@ -9,4 +9,10 @@
#define CONFIG_LMB
#define CONFIG_SYS_BOOT_RAMDISK_HIGH
#ifdef CONFIG_ARM64
#define CONFIG_PHYS_64BIT
#define CONFIG_STATIC_RELA
#endif
#endif

26
arch/arm/include/asm/emif.h
View File

@ -14,11 +14,15 @@
#define _EMIF_H_
#include <asm/types.h>
#include <common.h>
#include <asm/io.h>
/* Base address */
#define EMIF1_BASE 0x4c000000
#define EMIF2_BASE 0x4d000000
#define EMIF_4D 0x4
#define EMIF_4D5 0x5
/* Registers shifts, masks and values */
/* EMIF_MOD_ID_REV */
@ -1148,6 +1152,28 @@ struct read_write_regs {
u32 write_reg;
};
static inline u32 get_emif_rev(u32 base)
{
struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
return (readl(&emif->emif_mod_id_rev) & EMIF_REG_MAJOR_REVISION_MASK)
>> EMIF_REG_MAJOR_REVISION_SHIFT;
}
/*
* Get SDRAM type connected to EMIF.
* Assuming similar SDRAM parts are connected to both EMIF's
* which is typically the case. So it is sufficient to get
* SDRAM type from EMIF1.
*/
static inline u32 emif_sdram_type(void)
{
struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE;
return (readl(&emif->emif_sdram_config) &
EMIF_REG_SDRAM_TYPE_MASK) >> EMIF_REG_SDRAM_TYPE_SHIFT;
}
/* assert macros */
#if defined(DEBUG)
#define emif_assert(c) ({ if (!(c)) for (;;); })

53
arch/arm/include/asm/gic.h
View File

@ -1,19 +1,54 @@
#ifndef __GIC_V2_H__
#define __GIC_V2_H__
#ifndef __GIC_H__
#define __GIC_H__
/* register offsets for the ARM generic interrupt controller (GIC) */
/* Register offsets for the ARM generic interrupt controller (GIC) */
#define GIC_DIST_OFFSET 0x1000
#define GICD_CTLR 0x0000
#define GICD_TYPER 0x0004
#define GICD_IGROUPRn 0x0080
#define GICD_SGIR 0x0F00
#define GIC_CPU_OFFSET_A9 0x0100
#define GIC_CPU_OFFSET_A15 0x2000
/* Distributor Registers */
#define GICD_CTLR 0x0000
#define GICD_TYPER 0x0004
#define GICD_IIDR 0x0008
#define GICD_STATUSR 0x0010
#define GICD_SETSPI_NSR 0x0040
#define GICD_CLRSPI_NSR 0x0048
#define GICD_SETSPI_SR 0x0050
#define GICD_CLRSPI_SR 0x0058
#define GICD_SEIR 0x0068
#define GICD_IGROUPRn 0x0080
#define GICD_ISENABLERn 0x0100
#define GICD_ICENABLERn 0x0180
#define GICD_ISPENDRn 0x0200
#define GICD_ICPENDRn 0x0280
#define GICD_ISACTIVERn 0x0300
#define GICD_ICACTIVERn 0x0380
#define GICD_IPRIORITYRn 0x0400
#define GICD_ITARGETSRn 0x0800
#define GICD_ICFGR 0x0c00
#define GICD_IGROUPMODRn 0x0d00
#define GICD_NSACRn 0x0e00
#define GICD_SGIR 0x0f00
#define GICD_CPENDSGIRn 0x0f10
#define GICD_SPENDSGIRn 0x0f20
#define GICD_IROUTERn 0x6000
/* Cpu Interface Memory Mapped Registers */
#define GICC_CTLR 0x0000
#define GICC_PMR 0x0004
#define GICC_BPR 0x0008
#define GICC_IAR 0x000C
#define GICC_EOIR 0x0010
#define GICC_RPR 0x0014
#define GICC_HPPIR 0x0018
#define GICC_ABPR 0x001c
#define GICC_AIAR 0x0020
#define GICC_AEOIR 0x0024
#define GICC_AHPPIR 0x0028
#define GICC_APRn 0x00d0
#define GICC_NSAPRn 0x00e0
#define GICC_IIDR 0x00fc
#define GICC_DIR 0x1000
#endif
#endif /* __GIC_H__ */

6
arch/arm/include/asm/global_data.h
View File

@ -47,6 +47,10 @@ struct arch_global_data {
#include <asm-generic/global_data.h>
#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r9")
#ifdef CONFIG_ARM64
#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("x18")
#else
#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r9")
#endif
#endif /* __ASM_GBL_DATA_H */

2
arch/arm/include/asm/imx-common/iomux-v3.h
View File

@ -63,6 +63,8 @@ typedef u64 iomux_v3_cfg_t;
#define MUX_SEL_INPUT_SHIFT 59
#define MUX_SEL_INPUT_MASK ((iomux_v3_cfg_t)0xf << MUX_SEL_INPUT_SHIFT)
#define MUX_MODE_SION ((iomux_v3_cfg_t)IOMUX_CONFIG_SION << \
MUX_MODE_SHIFT)
#define MUX_PAD_CTRL(x) ((iomux_v3_cfg_t)(x) << MUX_PAD_CTRL_SHIFT)
#define IOMUX_PAD(pad_ctrl_ofs, mux_ctrl_ofs, mux_mode, sel_input_ofs, \

16
arch/arm/include/asm/imx-common/sata.h Normal file
View File

@ -0,0 +1,16 @@
/*
* Copyright 2011 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __IMX_SATA_H_
#define __IMX_SATA_H_
/*
* SATA setup for i.mx6 quad based platform
*/
int setup_sata(void);
#endif

15
arch/arm/include/asm/io.h
View File

@ -75,42 +75,45 @@ static inline phys_addr_t virt_to_phys(void * vaddr)
#define __arch_putw(v,a) (*(volatile unsigned short *)(a) = (v))
#define __arch_putl(v,a) (*(volatile unsigned int *)(a) = (v))
extern inline void __raw_writesb(unsigned int addr, const void *data, int bytelen)
extern inline void __raw_writesb(unsigned long addr, const void *data,
int bytelen)
{
uint8_t *buf = (uint8_t *)data;
while(bytelen--)
__arch_putb(*buf++, addr);
}
extern inline void __raw_writesw(unsigned int addr, const void *data, int wordlen)
extern inline void __raw_writesw(unsigned long addr, const void *data,
int wordlen)
{
uint16_t *buf = (uint16_t *)data;
while(wordlen--)
__arch_putw(*buf++, addr);
}
extern inline void __raw_writesl(unsigned int addr, const void *data, int longlen)
extern inline void __raw_writesl(unsigned long addr, const void *data,
int longlen)
{
uint32_t *buf = (uint32_t *)data;
while(longlen--)
__arch_putl(*buf++, addr);
}
extern inline void __raw_readsb(unsigned int addr, void *data, int bytelen)
extern inline void __raw_readsb(unsigned long addr, void *data, int bytelen)
{
uint8_t *buf = (uint8_t *)data;
while(bytelen--)
*buf++ = __arch_getb(addr);
}
extern inline void __raw_readsw(unsigned int addr, void *data, int wordlen)
extern inline void __raw_readsw(unsigned long addr, void *data, int wordlen)
{
uint16_t *buf = (uint16_t *)data;
while(wordlen--)
*buf++ = __arch_getw(addr);
}
extern inline void __raw_readsl(unsigned int addr, void *data, int longlen)
extern inline void __raw_readsl(unsigned long addr, void *data, int longlen)
{
uint32_t *buf = (uint32_t *)data;
while(longlen--)

53
arch/arm/include/asm/macro.h
View File

@ -54,5 +54,58 @@
bcs 1b
.endm
#ifdef CONFIG_ARM64
/*
* Register aliases.
*/
lr .req x30
/*
* Branch according to exception level
*/
.macro switch_el, xreg, el3_label, el2_label, el1_label
mrs \xreg, CurrentEL
cmp \xreg, 0xc
b.eq \el3_label
cmp \xreg, 0x8
b.eq \el2_label
cmp \xreg, 0x4
b.eq \el1_label
.endm
/*
* Branch if current processor is a slave,
* choose processor with all zero affinity value as the master.
*/
.macro branch_if_slave, xreg, slave_label
mrs \xreg, mpidr_el1
tst \xreg, #0xff /* Test Affinity 0 */
b.ne \slave_label
lsr \xreg, \xreg, #8
tst \xreg, #0xff /* Test Affinity 1 */
b.ne \slave_label
lsr \xreg, \xreg, #8
tst \xreg, #0xff /* Test Affinity 2 */
b.ne \slave_label
lsr \xreg, \xreg, #16
tst \xreg, #0xff /* Test Affinity 3 */
b.ne \slave_label
.endm
/*
* Branch if current processor is a master,
* choose processor with all zero affinity value as the master.
*/
.macro branch_if_master, xreg1, xreg2, master_label
mrs \xreg1, mpidr_el1
lsr \xreg2, \xreg1, #32
lsl \xreg1, \xreg1, #40
lsr \xreg1, \xreg1, #40
orr \xreg1, \xreg1, \xreg2
cbz \xreg1, \master_label
.endm
#endif /* CONFIG_ARM64 */
#endif /* __ASSEMBLY__ */
#endif /* __ASM_ARM_MACRO_H__ */

8
arch/arm/include/asm/posix_types.h
View File

@ -28,9 +28,17 @@ typedef int __kernel_pid_t;
typedef unsigned short __kernel_ipc_pid_t;
typedef unsigned short __kernel_uid_t;
typedef unsigned short __kernel_gid_t;
#ifdef __aarch64__
typedef unsigned long __kernel_size_t;
typedef long __kernel_ssize_t;
typedef long __kernel_ptrdiff_t;
#else
typedef unsigned int __kernel_size_t;
typedef int __kernel_ssize_t;
typedef int __kernel_ptrdiff_t;
#endif
typedef long __kernel_time_t;
typedef long __kernel_suseconds_t;
typedef long __kernel_clock_t;

21
arch/arm/include/asm/proc-armv/ptrace.h
View File

@ -10,6 +10,25 @@
#ifndef __ASM_PROC_PTRACE_H
#define __ASM_PROC_PTRACE_H
#ifdef CONFIG_ARM64
#define PCMASK 0
#ifndef __ASSEMBLY__
/*
* This struct defines the way the registers are stored
* on the stack during an exception.
*/
struct pt_regs {
unsigned long elr;
unsigned long regs[31];
};
#endif /* __ASSEMBLY__ */
#else /* CONFIG_ARM64 */
#define USR26_MODE 0x00
#define FIQ26_MODE 0x01
#define IRQ26_MODE 0x02
@ -104,4 +123,6 @@ static inline int valid_user_regs(struct pt_regs *regs)
#endif /* __ASSEMBLY__ */
#endif /* CONFIG_ARM64 */
#endif

59
arch/arm/include/asm/proc-armv/system.h
View File

@ -13,6 +13,60 @@
/*
* Save the current interrupt enable state & disable IRQs
*/
#ifdef CONFIG_ARM64
/*
* Save the current interrupt enable state
* and disable IRQs/FIQs
*/
#define local_irq_save(flags) \
({ \
asm volatile( \
"mrs %0, daif" \
"msr daifset, #3" \
: "=r" (flags) \
: \
: "memory"); \
})
/*
* restore saved IRQ & FIQ state
*/
#define local_irq_restore(flags) \
({ \
asm volatile( \
"msr daif, %0" \
: \
: "r" (flags) \
: "memory"); \
})
/*
* Enable IRQs/FIQs
*/
#define local_irq_enable() \
({ \
asm volatile( \
"msr daifclr, #3" \
: \
: \
: "memory"); \
})
/*
* Disable IRQs/FIQs
*/
#define local_irq_disable() \
({ \
asm volatile( \
"msr daifset, #3" \
: \
: \
: "memory"); \
})
#else /* CONFIG_ARM64 */
#define local_irq_save(x) \
({ \
unsigned long temp; \
@ -107,7 +161,10 @@
: "r" (x) \
: "memory")
#if defined(CONFIG_CPU_SA1100) || defined(CONFIG_CPU_SA110)
#endif /* CONFIG_ARM64 */
#if defined(CONFIG_CPU_SA1100) || defined(CONFIG_CPU_SA110) || \
defined(CONFIG_ARM64)
/*
* On the StrongARM, "swp" is terminally broken since it bypasses the
* cache totally. This means that the cache becomes inconsistent, and,

84
arch/arm/include/asm/system.h
View File

@ -1,6 +1,86 @@
#ifndef __ASM_ARM_SYSTEM_H
#define __ASM_ARM_SYSTEM_H
#ifdef CONFIG_ARM64
/*
* SCTLR_EL1/SCTLR_EL2/SCTLR_EL3 bits definitions
*/
#define CR_M (1 << 0) /* MMU enable */
#define CR_A (1 << 1) /* Alignment abort enable */
#define CR_C (1 << 2) /* Dcache enable */
#define CR_SA (1 << 3) /* Stack Alignment Check Enable */
#define CR_I (1 << 12) /* Icache enable */
#define CR_WXN (1 << 19) /* Write Permision Imply XN */
#define CR_EE (1 << 25) /* Exception (Big) Endian */
#define PGTABLE_SIZE (0x10000)
#ifndef __ASSEMBLY__
#define isb() \
({asm volatile( \
"isb" : : : "memory"); \
})
#define wfi() \
({asm volatile( \
"wfi" : : : "memory"); \
})
static inline unsigned int current_el(void)
{
unsigned int el;
asm volatile("mrs %0, CurrentEL" : "=r" (el) : : "cc");
return el >> 2;
}
static inline unsigned int get_sctlr(void)
{
unsigned int el, val;
el = current_el();
if (el == 1)
asm volatile("mrs %0, sctlr_el1" : "=r" (val) : : "cc");
else if (el == 2)
asm volatile("mrs %0, sctlr_el2" : "=r" (val) : : "cc");
else
asm volatile("mrs %0, sctlr_el3" : "=r" (val) : : "cc");
return val;
}
static inline void set_sctlr(unsigned int val)
{
unsigned int el;
el = current_el();
if (el == 1)
asm volatile("msr sctlr_el1, %0" : : "r" (val) : "cc");
else if (el == 2)
asm volatile("msr sctlr_el2, %0" : : "r" (val) : "cc");
else
asm volatile("msr sctlr_el3, %0" : : "r" (val) : "cc");
asm volatile("isb");
}
void __asm_flush_dcache_all(void);
void __asm_flush_dcache_range(u64 start, u64 end);
void __asm_invalidate_tlb_all(void);
void __asm_invalidate_icache_all(void);
void armv8_switch_to_el2(void);
void armv8_switch_to_el1(void);
void gic_init(void);
void gic_send_sgi(unsigned long sgino);
void wait_for_wakeup(void);
void smp_kick_all_cpus(void);
#endif /* __ASSEMBLY__ */
#else /* CONFIG_ARM64 */
#ifdef __KERNEL__
#define CPU_ARCH_UNKNOWN 0
@ -45,6 +125,8 @@
#define CR_AFE (1 << 29) /* Access flag enable */
#define CR_TE (1 << 30) /* Thumb exception enable */
#define PGTABLE_SIZE (4096 * 4)
/*
* This is used to ensure the compiler did actually allocate the register we
* asked it for some inline assembly sequences. Apparently we can't trust
@ -132,4 +214,6 @@ void mmu_page_table_flush(unsigned long start, unsigned long stop);
#endif /* __KERNEL__ */
#endif /* CONFIG_ARM64 */
#endif

4
arch/arm/include/asm/types.h
View File

@ -39,7 +39,11 @@ typedef unsigned int u32;
typedef signed long long s64;
typedef unsigned long long u64;
#ifdef CONFIG_ARM64
#define BITS_PER_LONG 64
#else /* CONFIG_ARM64 */
#define BITS_PER_LONG 32
#endif /* CONFIG_ARM64 */
/* Dma addresses are 32-bits wide. */

4
arch/arm/include/asm/u-boot.h
View File

@ -44,6 +44,10 @@ typedef struct bd_info {
#endif /* !CONFIG_SYS_GENERIC_BOARD */
/* For image.h:image_check_target_arch() */
#ifndef CONFIG_ARM64
#define IH_ARCH_DEFAULT IH_ARCH_ARM
#else
#define IH_ARCH_DEFAULT IH_ARCH_ARM64
#endif
#endif /* _U_BOOT_H_ */

2
arch/arm/include/asm/unaligned.h
View File

@ -8,7 +8,7 @@
/*
* Select endianness
*/
#ifndef __ARMEB__
#if __BYTE_ORDER == __LITTLE_ENDIAN
#define get_unaligned __get_unaligned_le
#define put_unaligned __put_unaligned_le
#else

20
arch/arm/lib/Makefile
View File

@ -17,14 +17,22 @@ lib-y += _umodsi3.o
lib-y += div0.o
endif
obj-y += crt0.o
ifdef CONFIG_ARM64
obj-y += crt0_64.o
else
obj-y += crt0.o
endif
ifndef CONFIG_SPL_BUILD
obj-y += relocate.o
ifdef CONFIG_ARM64
obj-y += relocate_64.o
else
obj-y += relocate.o
endif
ifndef CONFIG_SYS_GENERIC_BOARD
obj-y += board.o
endif
obj-y += sections.o
obj-y += sections.o
obj-$(CONFIG_OF_LIBFDT) += bootm-fdt.o
obj-$(CONFIG_CMD_BOOTM) += bootm.o
@ -35,11 +43,17 @@ else
obj-$(CONFIG_SPL_FRAMEWORK) += spl.o
endif
ifdef CONFIG_ARM64
obj-y += interrupts_64.o
else
obj-y += interrupts.o
endif
obj-y += reset.o
obj-y += cache.o
ifndef CONFIG_ARM64
obj-y += cache-cp15.o
endif
# For EABI conformant tool chains, provide eabi_compat()
ifneq (,$(findstring -mabi=aapcs-linux,$(PLATFORM_CPPFLAGS)))

10
arch/arm/lib/board.c
View File

@ -344,7 +344,7 @@ void board_init_f(ulong bootflag)
#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
/* reserve TLB table */
gd->arch.tlb_size = 4096 * 4;
gd->arch.tlb_size = PGTABLE_SIZE;
addr -= gd->arch.tlb_size;
/* round down to next 64 kB limit */
@ -419,6 +419,7 @@ void board_init_f(ulong bootflag)
}
#endif
#ifndef CONFIG_ARM64
/* setup stackpointer for exeptions */
gd->irq_sp = addr_sp;
#ifdef CONFIG_USE_IRQ
@ -431,11 +432,14 @@ void board_init_f(ulong bootflag)
/* 8-byte alignment for ABI compliance */
addr_sp &= ~0x07;
#else /* CONFIG_ARM64 */
/* 16-byte alignment for ABI compliance */
addr_sp &= ~0x0f;
#endif /* CONFIG_ARM64 */
#else
addr_sp += 128; /* leave 32 words for abort-stack */
gd->irq_sp = addr_sp;
#endif
interrupt_init();
debug("New Stack Pointer is: %08lx\n", addr_sp);
@ -637,6 +641,8 @@ void board_init_r(gd_t *id, ulong dest_addr)
misc_init_r();
#endif
/* set up exceptions */
interrupt_init();
/* enable exceptions */
enable_interrupts();

24
arch/arm/lib/bootm.c
View File

@ -196,6 +196,14 @@ static void do_nonsec_virt_switch(void)
debug("entered non-secure state\n");
#endif
#endif
#ifdef CONFIG_ARM64
smp_kick_all_cpus();
armv8_switch_to_el2();
#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
armv8_switch_to_el1();
#endif
#endif
}
/* Subcommand: PREP */
@ -240,6 +248,21 @@ static void boot_prep_linux(bootm_headers_t *images)
/* Subcommand: GO */
static void boot_jump_linux(bootm_headers_t *images, int flag)
{
#ifdef CONFIG_ARM64
void (*kernel_entry)(void *fdt_addr);
int fake = (flag & BOOTM_STATE_OS_FAKE_GO);
kernel_entry = (void (*)(void *fdt_addr))images->ep;
debug("## Transferring control to Linux (at address %lx)...\n",
(ulong) kernel_entry);
bootstage_mark(BOOTSTAGE_ID_RUN_OS);
announce_and_cleanup(fake);
if (!fake)
kernel_entry(images->ft_addr);
#else
unsigned long machid = gd->bd->bi_arch_number;
char *s;
void (*kernel_entry)(int zero, int arch, uint params);
@ -266,6 +289,7 @@ static void boot_jump_linux(bootm_headers_t *images, int flag)
if (!fake)
kernel_entry(0, machid, r2);
#endif
}
/* Main Entry point for arm bootm implementation

113
arch/arm/lib/crt0_64.S Normal file
View File

@ -0,0 +1,113 @@
/*
* crt0 - C-runtime startup Code for AArch64 U-Boot
*
* (C) Copyright 2013
* David Feng <fenghua@phytium.com.cn>
*
* (C) Copyright 2012
* Albert ARIBAUD <albert.u.boot@aribaud.net>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <config.h>
#include <asm-offsets.h>
#include <asm/macro.h>
#include <linux/linkage.h>
/*
* This file handles the target-independent stages of the U-Boot
* start-up where a C runtime environment is needed. Its entry point
* is _main and is branched into from the target's start.S file.
*
* _main execution sequence is:
*
* 1. Set up initial environment for calling board_init_f().
* This environment only provides a stack and a place to store
* the GD ('global data') structure, both located in some readily
* available RAM (SRAM, locked cache...). In this context, VARIABLE
* global data, initialized or not (BSS), are UNAVAILABLE; only
* CONSTANT initialized data are available.
*
* 2. Call board_init_f(). This function prepares the hardware for
* execution from system RAM (DRAM, DDR...) As system RAM may not
* be available yet, , board_init_f() must use the current GD to
* store any data which must be passed on to later stages. These
* data include the relocation destination, the future stack, and
* the future GD location.
*
* (the following applies only to non-SPL builds)
*
* 3. Set up intermediate environment where the stack and GD are the
* ones allocated by board_init_f() in system RAM, but BSS and
* initialized non-const data are still not available.
*
* 4. Call relocate_code(). This function relocates U-Boot from its
* current location into the relocation destination computed by
* board_init_f().
*
* 5. Set up final environment for calling board_init_r(). This
* environment has BSS (initialized to 0), initialized non-const
* data (initialized to their intended value), and stack in system
* RAM. GD has retained values set by board_init_f(). Some CPUs
* have some work left to do at this point regarding memory, so
* call c_runtime_cpu_setup.
*
* 6. Branch to board_init_r().
*/
ENTRY(_main)
/*
* Set up initial C runtime environment and call board_init_f(0).
*/
ldr x0, =(CONFIG_SYS_INIT_SP_ADDR)
sub x0, x0, #GD_SIZE /* allocate one GD above SP */
bic sp, x0, #0xf /* 16-byte alignment for ABI compliance */
mov x18, sp /* GD is above SP */
mov x0, #0
bl board_init_f
/*
* Set up intermediate environment (new sp and gd) and call
* relocate_code(addr_moni). Trick here is that we'll return
* 'here' but relocated.
*/
ldr x0, [x18, #GD_START_ADDR_SP] /* x0 <- gd->start_addr_sp */
bic sp, x0, #0xf /* 16-byte alignment for ABI compliance */
ldr x18, [x18, #GD_BD] /* x18 <- gd->bd */
sub x18, x18, #GD_SIZE /* new GD is below bd */
adr lr, relocation_return
ldr x9, [x18, #GD_RELOC_OFF] /* x9 <- gd->reloc_off */
add lr, lr, x9 /* new return address after relocation */
ldr x0, [x18, #GD_RELOCADDR] /* x0 <- gd->relocaddr */
b relocate_code
relocation_return:
/*
* Set up final (full) environment
*/
bl c_runtime_cpu_setup /* still call old routine */
/*
* Clear BSS section
*/
ldr x0, =__bss_start /* this is auto-relocated! */
ldr x1, =__bss_end /* this is auto-relocated! */
mov x2, #0
clear_loop:
str x2, [x0]
add x0, x0, #8
cmp x0, x1
b.lo clear_loop
/* call board_init_r(gd_t *id, ulong dest_addr) */
mov x0, x18 /* gd_t */
ldr x1, [x18, #GD_RELOCADDR] /* dest_addr */
b board_init_r /* PC relative jump */
/* NOTREACHED - board_init_r() does not return */
ENDPROC(_main)

120
arch/arm/lib/interrupts_64.c Normal file
View File

@ -0,0 +1,120 @@
/*
* (C) Copyright 2013
* David Feng <fenghua@phytium.com.cn>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <linux/compiler.h>
int interrupt_init(void)
{
return 0;
}
void enable_interrupts(void)
{
return;
}
int disable_interrupts(void)
{
return 0;
}
void show_regs(struct pt_regs *regs)
{
int i;
printf("ELR: %lx\n", regs->elr);
printf("LR: %lx\n", regs->regs[30]);
for (i = 0; i < 29; i += 2)
printf("x%-2d: %016lx x%-2d: %016lx\n",
i, regs->regs[i], i+1, regs->regs[i+1]);
printf("\n");
}
/*
* do_bad_sync handles the impossible case in the Synchronous Abort vector.
*/
void do_bad_sync(struct pt_regs *pt_regs, unsigned int esr)
{
printf("Bad mode in \"Synchronous Abort\" handler, esr 0x%08x\n", esr);
show_regs(pt_regs);
panic("Resetting CPU ...\n");
}
/*
* do_bad_irq handles the impossible case in the Irq vector.
*/
void do_bad_irq(struct pt_regs *pt_regs, unsigned int esr)
{
printf("Bad mode in \"Irq\" handler, esr 0x%08x\n", esr);
show_regs(pt_regs);
panic("Resetting CPU ...\n");
}
/*
* do_bad_fiq handles the impossible case in the Fiq vector.
*/
void do_bad_fiq(struct pt_regs *pt_regs, unsigned int esr)
{
printf("Bad mode in \"Fiq\" handler, esr 0x%08x\n", esr);
show_regs(pt_regs);
panic("Resetting CPU ...\n");
}
/*
* do_bad_error handles the impossible case in the Error vector.
*/
void do_bad_error(struct pt_regs *pt_regs, unsigned int esr)
{
printf("Bad mode in \"Error\" handler, esr 0x%08x\n", esr);
show_regs(pt_regs);
panic("Resetting CPU ...\n");
}
/*
* do_sync handles the Synchronous Abort exception.
*/
void do_sync(struct pt_regs *pt_regs, unsigned int esr)
{
printf("\"Synchronous Abort\" handler, esr 0x%08x\n", esr);
show_regs(pt_regs);
panic("Resetting CPU ...\n");
}
/*
* do_irq handles the Irq exception.
*/
void do_irq(struct pt_regs *pt_regs, unsigned int esr)
{
printf("\"Irq\" handler, esr 0x%08x\n", esr);
show_regs(pt_regs);
panic("Resetting CPU ...\n");
}
/*
* do_fiq handles the Fiq exception.
*/
void do_fiq(struct pt_regs *pt_regs, unsigned int esr)
{
printf("\"Fiq\" handler, esr 0x%08x\n", esr);
show_regs(pt_regs);
panic("Resetting CPU ...\n");
}
/*
* do_error handles the Error exception.
* Errors are more likely to be processor specific,
* it is defined with weak attribute and can be redefined
* in processor specific code.
*/
void __weak do_error(struct pt_regs *pt_regs, unsigned int esr)
{
printf("\"Error\" handler, esr 0x%08x\n", esr);
show_regs(pt_regs);
panic("Resetting CPU ...\n");
}

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