mips: xburst: remove remainders of dead board
Commit 54e458de
deleted qi_lb60 board support
because of the incompatible license issue.
There is no board with XBurst CPU.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
This commit is contained in:
parent
79fd7e649e
commit
7e3d473b5e
1
README
1
README
@ -164,7 +164,6 @@ Directory Hierarchy:
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/mips Files generic to MIPS architecture
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/cpu CPU specific files
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/mips32 Files specific to MIPS32 CPUs
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/xburst Files specific to Ingenic XBurst CPUs
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/lib Architecture specific library files
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/nds32 Files generic to NDS32 architecture
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/cpu CPU specific files
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@ -1,9 +0,0 @@
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#
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# Copyright (C) 2011 Xiangfu Liu <xiangfu@openmobilefree.net>
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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extra-y = start.o
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obj-y = cpu.o timer.o jz_serial.o
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obj-$(CONFIG_JZ4740) += jz4740.o
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@ -1,16 +0,0 @@
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#
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# Copyright (C) 2011 Xiangfu Liu <xiangfu@openmobilefree.net>
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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PLATFORM_CPPFLAGS += -march=mips32
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PLATFORM_CPPFLAGS += -mabi=32 -DCONFIG_32BIT
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ifdef CONFIG_SYS_BIG_ENDIAN
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PLATFORM_LDFLAGS += -m elf32btsmip
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else
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PLATFORM_LDFLAGS += -m elf32ltsmip
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endif
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CONFIG_STANDALONE_LOAD_ADDR ?= 0x80200000 \
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-T $(srctree)/examples/standalone/mips.lds
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@ -1,136 +0,0 @@
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/*
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* (C) Copyright 2003
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* Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
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* (C) Copyright 2011
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* Xiangfu Liu <xiangfu@openmobilefree.net>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <command.h>
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#include <netdev.h>
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#include <asm/mipsregs.h>
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#include <asm/cacheops.h>
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#include <asm/reboot.h>
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#include <asm/io.h>
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#include <asm/jz4740.h>
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#define cache_op(op, addr) \
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__asm__ __volatile__( \
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".set push\n" \
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".set noreorder\n" \
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".set mips3\n" \
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"cache %0, %1\n" \
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".set pop\n" \
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: \
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: "i" (op), "R" (*(unsigned char *)(addr)))
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void __attribute__((weak)) _machine_restart(void)
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{
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struct jz4740_wdt *wdt = (struct jz4740_wdt *)JZ4740_WDT_BASE;
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struct jz4740_tcu *tcu = (struct jz4740_tcu *)JZ4740_TCU_BASE;
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u16 tmp;
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/* wdt_select_extalclk() */
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tmp = readw(&wdt->tcsr);
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tmp &= ~(WDT_TCSR_EXT_EN | WDT_TCSR_RTC_EN | WDT_TCSR_PCK_EN);
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tmp |= WDT_TCSR_EXT_EN;
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writew(tmp, &wdt->tcsr);
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/* wdt_select_clk_div64() */
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tmp = readw(&wdt->tcsr);
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tmp &= ~WDT_TCSR_PRESCALE_MASK;
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tmp |= WDT_TCSR_PRESCALE64,
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writew(tmp, &wdt->tcsr);
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writew(100, &wdt->tdr); /* wdt_set_data(100) */
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writew(0, &wdt->tcnt); /* wdt_set_count(0); */
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writel(TCU_TSSR_WDTSC, &tcu->tscr); /* tcu_start_wdt_clock */
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writeb(readb(&wdt->tcer) | WDT_TCER_TCEN, &wdt->tcer); /* wdt start */
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while (1)
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;
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}
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int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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_machine_restart();
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fprintf(stderr, "*** reset failed ***\n");
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return 0;
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}
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void flush_cache(ulong start_addr, ulong size)
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{
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unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
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unsigned long addr = start_addr & ~(lsize - 1);
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unsigned long aend = (start_addr + size - 1) & ~(lsize - 1);
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for (; addr <= aend; addr += lsize) {
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cache_op(HIT_WRITEBACK_INV_D, addr);
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cache_op(HIT_INVALIDATE_I, addr);
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}
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}
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void flush_dcache_range(ulong start_addr, ulong stop)
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{
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unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
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unsigned long addr = start_addr & ~(lsize - 1);
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unsigned long aend = (stop - 1) & ~(lsize - 1);
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for (; addr <= aend; addr += lsize)
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cache_op(HIT_WRITEBACK_INV_D, addr);
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}
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void invalidate_dcache_range(ulong start_addr, ulong stop)
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{
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unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
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unsigned long addr = start_addr & ~(lsize - 1);
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unsigned long aend = (stop - 1) & ~(lsize - 1);
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for (; addr <= aend; addr += lsize)
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cache_op(HIT_INVALIDATE_D, addr);
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}
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void flush_icache_all(void)
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{
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u32 addr, t = 0;
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__asm__ __volatile__("mtc0 $0, $28"); /* Clear Taglo */
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__asm__ __volatile__("mtc0 $0, $29"); /* Clear TagHi */
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for (addr = CKSEG0; addr < CKSEG0 + CONFIG_SYS_ICACHE_SIZE;
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addr += CONFIG_SYS_CACHELINE_SIZE) {
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cache_op(INDEX_STORE_TAG_I, addr);
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}
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/* invalidate btb */
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__asm__ __volatile__(
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".set mips32\n\t"
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"mfc0 %0, $16, 7\n\t"
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"nop\n\t"
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"ori %0,2\n\t"
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"mtc0 %0, $16, 7\n\t"
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".set mips2\n\t"
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:
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: "r" (t));
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}
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void flush_dcache_all(void)
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{
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u32 addr;
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for (addr = CKSEG0; addr < CKSEG0 + CONFIG_SYS_DCACHE_SIZE;
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addr += CONFIG_SYS_CACHELINE_SIZE) {
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cache_op(INDEX_WRITEBACK_INV_D, addr);
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}
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__asm__ __volatile__("sync");
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}
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void flush_cache_all(void)
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{
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flush_dcache_all();
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flush_icache_all();
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}
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@ -1,235 +0,0 @@
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/*
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* Jz4740 common routines
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* Copyright (c) 2006 Ingenic Semiconductor, <jlwei@ingenic.cn>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <config.h>
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#include <common.h>
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#include <asm/io.h>
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#include <asm/jz4740.h>
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void enable_interrupts(void)
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{
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}
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int disable_interrupts(void)
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{
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return 0;
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}
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/*
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* PLL output clock = EXTAL * NF / (NR * NO)
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* NF = FD + 2, NR = RD + 2
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* NO = 1 (if OD = 0), NO = 2 (if OD = 1 or 2), NO = 4 (if OD = 3)
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*/
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void pll_init(void)
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{
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struct jz4740_cpm *cpm = (struct jz4740_cpm *)JZ4740_CPM_BASE;
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register unsigned int cfcr, plcr1;
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int n2FR[33] = {
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0, 0, 1, 2, 3, 0, 4, 0, 5, 0, 0, 0, 6, 0, 0, 0,
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7, 0, 0, 0, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0,
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9
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};
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int div[5] = {1, 3, 3, 3, 3}; /* divisors of I:S:P:L:M */
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int nf, pllout2;
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cfcr = CPM_CPCCR_CLKOEN |
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CPM_CPCCR_PCS |
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(n2FR[div[0]] << CPM_CPCCR_CDIV_BIT) |
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(n2FR[div[1]] << CPM_CPCCR_HDIV_BIT) |
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(n2FR[div[2]] << CPM_CPCCR_PDIV_BIT) |
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(n2FR[div[3]] << CPM_CPCCR_MDIV_BIT) |
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(n2FR[div[4]] << CPM_CPCCR_LDIV_BIT);
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pllout2 = (cfcr & CPM_CPCCR_PCS) ?
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CONFIG_SYS_CPU_SPEED : (CONFIG_SYS_CPU_SPEED / 2);
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/* Init USB Host clock, pllout2 must be n*48MHz */
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writel(pllout2 / 48000000 - 1, &cpm->uhccdr);
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nf = CONFIG_SYS_CPU_SPEED * 2 / CONFIG_SYS_EXTAL;
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plcr1 = ((nf - 2) << CPM_CPPCR_PLLM_BIT) | /* FD */
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(0 << CPM_CPPCR_PLLN_BIT) | /* RD=0, NR=2 */
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(0 << CPM_CPPCR_PLLOD_BIT) | /* OD=0, NO=1 */
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(0x20 << CPM_CPPCR_PLLST_BIT) | /* PLL stable time */
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CPM_CPPCR_PLLEN; /* enable PLL */
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/* init PLL */
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writel(cfcr, &cpm->cpccr);
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writel(plcr1, &cpm->cppcr);
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}
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void sdram_init(void)
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{
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struct jz4740_emc *emc = (struct jz4740_emc *)JZ4740_EMC_BASE;
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register unsigned int dmcr0, dmcr, sdmode, tmp, cpu_clk, mem_clk, ns;
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unsigned int cas_latency_sdmr[2] = {
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EMC_SDMR_CAS_2,
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EMC_SDMR_CAS_3,
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};
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unsigned int cas_latency_dmcr[2] = {
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1 << EMC_DMCR_TCL_BIT, /* CAS latency is 2 */
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2 << EMC_DMCR_TCL_BIT /* CAS latency is 3 */
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};
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int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
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cpu_clk = CONFIG_SYS_CPU_SPEED;
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mem_clk = cpu_clk * div[__cpm_get_cdiv()] / div[__cpm_get_mdiv()];
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writel(0, &emc->bcr); /* Disable bus release */
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writew(0, &emc->rtcsr); /* Disable clock for counting */
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/* Fault DMCR value for mode register setting*/
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#define SDRAM_ROW0 11
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#define SDRAM_COL0 8
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#define SDRAM_BANK40 0
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dmcr0 = ((SDRAM_ROW0 - 11) << EMC_DMCR_RA_BIT) |
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((SDRAM_COL0 - 8) << EMC_DMCR_CA_BIT) |
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(SDRAM_BANK40 << EMC_DMCR_BA_BIT) |
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(SDRAM_BW16 << EMC_DMCR_BW_BIT) |
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EMC_DMCR_EPIN |
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cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)];
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/* Basic DMCR value */
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dmcr = ((SDRAM_ROW - 11) << EMC_DMCR_RA_BIT) |
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((SDRAM_COL - 8) << EMC_DMCR_CA_BIT) |
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(SDRAM_BANK4 << EMC_DMCR_BA_BIT) |
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(SDRAM_BW16 << EMC_DMCR_BW_BIT) |
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EMC_DMCR_EPIN |
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cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)];
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/* SDRAM timimg */
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ns = 1000000000 / mem_clk;
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tmp = SDRAM_TRAS / ns;
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if (tmp < 4)
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tmp = 4;
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if (tmp > 11)
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tmp = 11;
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dmcr |= (tmp - 4) << EMC_DMCR_TRAS_BIT;
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tmp = SDRAM_RCD / ns;
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if (tmp > 3)
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tmp = 3;
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dmcr |= tmp << EMC_DMCR_RCD_BIT;
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tmp = SDRAM_TPC / ns;
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if (tmp > 7)
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tmp = 7;
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dmcr |= tmp << EMC_DMCR_TPC_BIT;
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tmp = SDRAM_TRWL / ns;
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if (tmp > 3)
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tmp = 3;
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dmcr |= tmp << EMC_DMCR_TRWL_BIT;
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tmp = (SDRAM_TRAS + SDRAM_TPC) / ns;
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if (tmp > 14)
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tmp = 14;
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dmcr |= ((tmp + 1) >> 1) << EMC_DMCR_TRC_BIT;
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/* SDRAM mode value */
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sdmode = EMC_SDMR_BT_SEQ |
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EMC_SDMR_OM_NORMAL |
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EMC_SDMR_BL_4 |
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cas_latency_sdmr[((SDRAM_CASL == 3) ? 1 : 0)];
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/* Stage 1. Precharge all banks by writing SDMR with DMCR.MRSET=0 */
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writel(dmcr, &emc->dmcr);
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writeb(0, JZ4740_EMC_SDMR0 | sdmode);
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/* Wait for precharge, > 200us */
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tmp = (cpu_clk / 1000000) * 1000;
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while (tmp--)
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;
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/* Stage 2. Enable auto-refresh */
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writel(dmcr | EMC_DMCR_RFSH, &emc->dmcr);
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tmp = SDRAM_TREF / ns;
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tmp = tmp / 64 + 1;
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if (tmp > 0xff)
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tmp = 0xff;
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writew(tmp, &emc->rtcor);
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writew(0, &emc->rtcnt);
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/* Divisor is 64, CKO/64 */
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writew(EMC_RTCSR_CKS_64, &emc->rtcsr);
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/* Wait for number of auto-refresh cycles */
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tmp = (cpu_clk / 1000000) * 1000;
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while (tmp--)
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;
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/* Stage 3. Mode Register Set */
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writel(dmcr0 | EMC_DMCR_RFSH | EMC_DMCR_MRSET, &emc->dmcr);
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writeb(0, JZ4740_EMC_SDMR0 | sdmode);
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/* Set back to basic DMCR value */
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writel(dmcr | EMC_DMCR_RFSH | EMC_DMCR_MRSET, &emc->dmcr);
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/* everything is ok now */
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}
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DECLARE_GLOBAL_DATA_PTR;
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void calc_clocks(void)
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{
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unsigned int pllout;
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unsigned int div[10] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
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pllout = __cpm_get_pllout();
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gd->cpu_clk = pllout / div[__cpm_get_cdiv()];
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gd->arch.sys_clk = pllout / div[__cpm_get_hdiv()];
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gd->arch.per_clk = pllout / div[__cpm_get_pdiv()];
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gd->mem_clk = pllout / div[__cpm_get_mdiv()];
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gd->arch.dev_clk = CONFIG_SYS_EXTAL;
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}
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void rtc_init(void)
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{
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struct jz4740_rtc *rtc = (struct jz4740_rtc *)JZ4740_RTC_BASE;
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while (!(readl(&rtc->rcr) & RTC_RCR_WRDY))
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;
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writel(readl(&rtc->rcr) | RTC_RCR_AE, &rtc->rcr); /* enable alarm */
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while (!(readl(&rtc->rcr) & RTC_RCR_WRDY))
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;
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writel(0x00007fff, &rtc->rgr); /* type value */
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while (!(readl(&rtc->rcr) & RTC_RCR_WRDY))
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;
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writel(0x0000ffe0, &rtc->hwfcr); /* Power on delay 2s */
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while (!(readl(&rtc->rcr) & RTC_RCR_WRDY))
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;
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writel(0x00000fe0, &rtc->hrcr); /* reset delay 125ms */
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}
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/* U-Boot common routines */
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phys_size_t initdram(int board_type)
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{
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struct jz4740_emc *emc = (struct jz4740_emc *)JZ4740_EMC_BASE;
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u32 dmcr;
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u32 rows, cols, dw, banks;
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ulong size;
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dmcr = readl(&emc->dmcr);
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rows = 11 + ((dmcr & EMC_DMCR_RA_MASK) >> EMC_DMCR_RA_BIT);
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cols = 8 + ((dmcr & EMC_DMCR_CA_MASK) >> EMC_DMCR_CA_BIT);
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dw = (dmcr & EMC_DMCR_BW) ? 2 : 4;
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banks = (dmcr & EMC_DMCR_BA) ? 4 : 2;
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size = (1 << (rows + cols)) * dw * banks;
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return size;
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}
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@ -1,118 +0,0 @@
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/*
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* Jz4740 UART support
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* Copyright (c) 2011
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* Qi Hardware, Xiangfu Liu <xiangfu@sharism.cc>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <config.h>
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#include <common.h>
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#include <asm/io.h>
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#include <asm/jz4740.h>
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#include <serial.h>
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#include <linux/compiler.h>
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/*
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* serial_init - initialize a channel
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*
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* This routine initializes the number of data bits, parity
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* and set the selected baud rate. Interrupts are disabled.
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* Set the modem control signals if the option is selected.
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*
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* RETURNS: N/A
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*/
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struct jz4740_uart *uart = (struct jz4740_uart *)CONFIG_SYS_UART_BASE;
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static int jz_serial_init(void)
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{
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/* Disable port interrupts while changing hardware */
|
||||
writeb(0, &uart->dlhr_ier);
|
||||
|
||||
/* Disable UART unit function */
|
||||
writeb(~UART_FCR_UUE, &uart->iir_fcr);
|
||||
|
||||
/* Set both receiver and transmitter in UART mode (not SIR) */
|
||||
writeb(~(SIRCR_RSIRE | SIRCR_TSIRE), &uart->isr);
|
||||
|
||||
/*
|
||||
* Set databits, stopbits and parity.
|
||||
* (8-bit data, 1 stopbit, no parity)
|
||||
*/
|
||||
writeb(UART_LCR_WLEN_8 | UART_LCR_STOP_1, &uart->lcr);
|
||||
|
||||
/* Set baud rate */
|
||||
serial_setbrg();
|
||||
|
||||
/* Enable UART unit, enable and clear FIFO */
|
||||
writeb(UART_FCR_UUE | UART_FCR_FE | UART_FCR_TFLS | UART_FCR_RFLS,
|
||||
&uart->iir_fcr);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void jz_serial_setbrg(void)
|
||||
{
|
||||
u32 baud_div, tmp;
|
||||
|
||||
baud_div = CONFIG_SYS_EXTAL / 16 / CONFIG_BAUDRATE;
|
||||
|
||||
tmp = readb(&uart->lcr);
|
||||
tmp |= UART_LCR_DLAB;
|
||||
writeb(tmp, &uart->lcr);
|
||||
|
||||
writeb((baud_div >> 8) & 0xff, &uart->dlhr_ier);
|
||||
writeb(baud_div & 0xff, &uart->rbr_thr_dllr);
|
||||
|
||||
tmp &= ~UART_LCR_DLAB;
|
||||
writeb(tmp, &uart->lcr);
|
||||
}
|
||||
|
||||
static int jz_serial_tstc(void)
|
||||
{
|
||||
if (readb(&uart->lsr) & UART_LSR_DR)
|
||||
return 1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void jz_serial_putc(const char c)
|
||||
{
|
||||
if (c == '\n')
|
||||
serial_putc('\r');
|
||||
|
||||
/* Wait for fifo to shift out some bytes */
|
||||
while (!((readb(&uart->lsr) & (UART_LSR_TDRQ | UART_LSR_TEMT)) == 0x60))
|
||||
;
|
||||
|
||||
writeb((u8)c, &uart->rbr_thr_dllr);
|
||||
}
|
||||
|
||||
static int jz_serial_getc(void)
|
||||
{
|
||||
while (!serial_tstc())
|
||||
;
|
||||
|
||||
return readb(&uart->rbr_thr_dllr);
|
||||
}
|
||||
|
||||
static struct serial_device jz_serial_drv = {
|
||||
.name = "jz_serial",
|
||||
.start = jz_serial_init,
|
||||
.stop = NULL,
|
||||
.setbrg = jz_serial_setbrg,
|
||||
.putc = jz_serial_putc,
|
||||
.puts = default_serial_puts,
|
||||
.getc = jz_serial_getc,
|
||||
.tstc = jz_serial_tstc,
|
||||
};
|
||||
|
||||
void jz_serial_initialize(void)
|
||||
{
|
||||
serial_register(&jz_serial_drv);
|
||||
}
|
||||
|
||||
__weak struct serial_device *default_serial_console(void)
|
||||
{
|
||||
return &jz_serial_drv;
|
||||
}
|
@ -1,179 +0,0 @@
|
||||
/*
|
||||
* Startup Code for MIPS32 XBURST CPU-core
|
||||
*
|
||||
* Copyright (c) 2010 Xiangfu Liu <xiangfu@sharism.cc>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <config.h>
|
||||
#include <version.h>
|
||||
#include <asm/regdef.h>
|
||||
#include <asm/mipsregs.h>
|
||||
#include <asm/addrspace.h>
|
||||
#include <asm/cacheops.h>
|
||||
|
||||
.set noreorder
|
||||
|
||||
.globl _start
|
||||
.text
|
||||
_start:
|
||||
/* Initialize $gp */
|
||||
bal 1f
|
||||
nop
|
||||
.word _gp
|
||||
1:
|
||||
lw gp, 0(ra)
|
||||
|
||||
/* Set up temporary stack */
|
||||
li sp, CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET
|
||||
|
||||
la t9, board_init_f
|
||||
jr t9
|
||||
nop
|
||||
|
||||
/*
|
||||
* void relocate_code (addr_sp, gd, addr_moni)
|
||||
*
|
||||
* This "function" does not return, instead it continues in RAM
|
||||
* after relocating the monitor code.
|
||||
*
|
||||
* a0 = addr_sp
|
||||
* a1 = gd
|
||||
* a2 = destination address
|
||||
*/
|
||||
.globl relocate_code
|
||||
.ent relocate_code
|
||||
relocate_code:
|
||||
move sp, a0 # set new stack pointer
|
||||
|
||||
move s0, a1 # save gd in s0
|
||||
move s2, a2 # save destination address in s2
|
||||
|
||||
li t0, CONFIG_SYS_MONITOR_BASE
|
||||
sub s1, s2, t0 # s1 <-- relocation offset
|
||||
|
||||
la t3, in_ram
|
||||
lw t2, -12(t3) # t2 <-- __image_copy_end
|
||||
move t1, a2
|
||||
|
||||
add gp, s1 # adjust gp
|
||||
|
||||
/*
|
||||
* t0 = source address
|
||||
* t1 = target address
|
||||
* t2 = source end address
|
||||
*/
|
||||
1:
|
||||
lw t3, 0(t0)
|
||||
sw t3, 0(t1)
|
||||
addu t0, 4
|
||||
blt t0, t2, 1b
|
||||
addu t1, 4
|
||||
|
||||
/* If caches were enabled, we would have to flush them here. */
|
||||
|
||||
/* flush d-cache */
|
||||
li t0, KSEG0
|
||||
addi t1, t0, CONFIG_SYS_DCACHE_SIZE
|
||||
2:
|
||||
cache INDEX_WRITEBACK_INV_D, 0(t0)
|
||||
bne t0, t1, 2b
|
||||
addi t0, CONFIG_SYS_CACHELINE_SIZE
|
||||
|
||||
sync
|
||||
|
||||
/* flush i-cache */
|
||||
li t0, KSEG0
|
||||
addi t1, t0, CONFIG_SYS_ICACHE_SIZE
|
||||
3:
|
||||
cache INDEX_INVALIDATE_I, 0(t0)
|
||||
bne t0, t1, 3b
|
||||
addi t0, CONFIG_SYS_CACHELINE_SIZE
|
||||
|
||||
/* Invalidate BTB */
|
||||
mfc0 t0, CP0_CONFIG, 7
|
||||
nop
|
||||
ori t0, 2
|
||||
mtc0 t0, CP0_CONFIG, 7
|
||||
nop
|
||||
|
||||
/* Jump to where we've relocated ourselves */
|
||||
addi t0, s2, in_ram - _start
|
||||
jr t0
|
||||
nop
|
||||
|
||||
.word __rel_dyn_end
|
||||
.word __rel_dyn_start
|
||||
.word __image_copy_end
|
||||
.word _GLOBAL_OFFSET_TABLE_
|
||||
.word num_got_entries
|
||||
|
||||
in_ram:
|
||||
/*
|
||||
* Now we want to update GOT.
|
||||
*
|
||||
* GOT[0] is reserved. GOT[1] is also reserved for the dynamic object
|
||||
* generated by GNU ld. Skip these reserved entries from relocation.
|
||||
*/
|
||||
lw t3, -4(t0) # t3 <-- num_got_entries
|
||||
lw t8, -8(t0) # t8 <-- _GLOBAL_OFFSET_TABLE_
|
||||
add t8, s1 # t8 now holds relocated _G_O_T_
|
||||
addi t8, t8, 8 # skipping first two entries
|
||||
li t2, 2
|
||||
1:
|
||||
lw t1, 0(t8)
|
||||
beqz t1, 2f
|
||||
add t1, s1
|
||||
sw t1, 0(t8)
|
||||
2:
|
||||
addi t2, 1
|
||||
blt t2, t3, 1b
|
||||
addi t8, 4
|
||||
|
||||
/* Update dynamic relocations */
|
||||
lw t1, -16(t0) # t1 <-- __rel_dyn_start
|
||||
lw t2, -20(t0) # t2 <-- __rel_dyn_end
|
||||
|
||||
b 2f # skip first reserved entry
|
||||
addi t1, 8
|
||||
|
||||
1:
|
||||
lw t8, -4(t1) # t8 <-- relocation info
|
||||
|
||||
li t3, 3
|
||||
bne t8, t3, 2f # skip non R_MIPS_REL32 entries
|
||||
nop
|
||||
|
||||
lw t3, -8(t1) # t3 <-- location to fix up in FLASH
|
||||
|
||||
lw t8, 0(t3) # t8 <-- original pointer
|
||||
add t8, s1 # t8 <-- adjusted pointer
|
||||
|
||||
add t3, s1 # t3 <-- location to fix up in RAM
|
||||
sw t8, 0(t3)
|
||||
|
||||
2:
|
||||
blt t1, t2, 1b
|
||||
addi t1, 8 # each rel.dyn entry is 8 bytes
|
||||
|
||||
/*
|
||||
* Clear BSS
|
||||
*
|
||||
* GOT is now relocated. Thus __bss_start and __bss_end can be
|
||||
* accessed directly via $gp.
|
||||
*/
|
||||
la t1, __bss_start # t1 <-- __bss_start
|
||||
la t2, __bss_end # t2 <-- __bss_end
|
||||
|
||||
1:
|
||||
sw zero, 0(t1)
|
||||
blt t1, t2, 1b
|
||||
addi t1, 4
|
||||
|
||||
move a0, s0 # a0 <-- gd
|
||||
la t9, board_init_r
|
||||
jr t9
|
||||
move a1, s2
|
||||
|
||||
.end relocate_code
|
@ -1,149 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2006
|
||||
* Ingenic Semiconductor, <jlwei@ingenic.cn>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <config.h>
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
#include <asm/jz4740.h>
|
||||
|
||||
#define TIMER_CHAN 0
|
||||
#define TIMER_FDATA 0xffff /* Timer full data value */
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
static struct jz4740_tcu *tcu = (struct jz4740_tcu *)JZ4740_TCU_BASE;
|
||||
|
||||
void reset_timer_masked(void)
|
||||
{
|
||||
/* reset time */
|
||||
gd->arch.lastinc = readl(&tcu->tcnt0);
|
||||
gd->arch.tbl = 0;
|
||||
}
|
||||
|
||||
ulong get_timer_masked(void)
|
||||
{
|
||||
ulong now = readl(&tcu->tcnt0);
|
||||
|
||||
if (gd->arch.lastinc <= now)
|
||||
gd->arch.tbl += now - gd->arch.lastinc; /* normal mode */
|
||||
else {
|
||||
/* we have an overflow ... */
|
||||
gd->arch.tbl += TIMER_FDATA + now - gd->arch.lastinc;
|
||||
}
|
||||
|
||||
gd->arch.lastinc = now;
|
||||
|
||||
return gd->arch.tbl;
|
||||
}
|
||||
|
||||
void udelay_masked(unsigned long usec)
|
||||
{
|
||||
ulong tmo;
|
||||
ulong endtime;
|
||||
signed long diff;
|
||||
|
||||
/* normalize */
|
||||
if (usec >= 1000) {
|
||||
tmo = usec / 1000;
|
||||
tmo *= CONFIG_SYS_HZ;
|
||||
tmo /= 1000;
|
||||
} else {
|
||||
if (usec > 1) {
|
||||
tmo = usec * CONFIG_SYS_HZ;
|
||||
tmo /= 1000*1000;
|
||||
} else
|
||||
tmo = 1;
|
||||
}
|
||||
|
||||
endtime = get_timer_masked() + tmo;
|
||||
|
||||
do {
|
||||
ulong now = get_timer_masked();
|
||||
diff = endtime - now;
|
||||
} while (diff >= 0);
|
||||
}
|
||||
|
||||
int timer_init(void)
|
||||
{
|
||||
writel(TCU_TCSR_PRESCALE256 | TCU_TCSR_EXT_EN, &tcu->tcsr0);
|
||||
|
||||
writel(0, &tcu->tcnt0);
|
||||
writel(0, &tcu->tdhr0);
|
||||
writel(TIMER_FDATA, &tcu->tdfr0);
|
||||
|
||||
/* mask irqs */
|
||||
writel((1 << TIMER_CHAN) | (1 << (TIMER_CHAN + 16)), &tcu->tmsr);
|
||||
writel(1 << TIMER_CHAN, &tcu->tscr); /* enable timer clock */
|
||||
writeb(1 << TIMER_CHAN, &tcu->tesr); /* start counting up */
|
||||
|
||||
gd->arch.lastinc = 0;
|
||||
gd->arch.tbl = 0;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void reset_timer(void)
|
||||
{
|
||||
reset_timer_masked();
|
||||
}
|
||||
|
||||
ulong get_timer(ulong base)
|
||||
{
|
||||
return get_timer_masked() - base;
|
||||
}
|
||||
|
||||
void set_timer(ulong t)
|
||||
{
|
||||
gd->arch.tbl = t;
|
||||
}
|
||||
|
||||
void __udelay(unsigned long usec)
|
||||
{
|
||||
ulong tmo, tmp;
|
||||
|
||||
/* normalize */
|
||||
if (usec >= 1000) {
|
||||
tmo = usec / 1000;
|
||||
tmo *= CONFIG_SYS_HZ;
|
||||
tmo /= 1000;
|
||||
} else {
|
||||
if (usec >= 1) {
|
||||
tmo = usec * CONFIG_SYS_HZ;
|
||||
tmo /= 1000 * 1000;
|
||||
} else
|
||||
tmo = 1;
|
||||
}
|
||||
|
||||
/* check for rollover during this delay */
|
||||
tmp = get_timer(0);
|
||||
if ((tmp + tmo) < tmp)
|
||||
reset_timer_masked(); /* timer would roll over */
|
||||
else
|
||||
tmo += tmp;
|
||||
|
||||
while (get_timer_masked() < tmo)
|
||||
;
|
||||
}
|
||||
|
||||
/*
|
||||
* This function is derived from PowerPC code (read timebase as long long).
|
||||
* On MIPS it just returns the timer value.
|
||||
*/
|
||||
unsigned long long get_ticks(void)
|
||||
{
|
||||
return get_timer(0);
|
||||
}
|
||||
|
||||
/*
|
||||
* This function is derived from PowerPC code (timebase clock frequency).
|
||||
* On MIPS it returns the number of timer ticks per second.
|
||||
*/
|
||||
ulong get_tbclk(void)
|
||||
{
|
||||
return CONFIG_SYS_HZ;
|
||||
}
|
Loading…
Reference in New Issue
Block a user