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mpc83xx: MPC837XEMDS: Initialize SerDes before negating PCIE reset signal

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The SerDes initialization should be finished before negating the reset
signal according to the reference manual. This isn't an issue on real
hardware, but we'd better stick to the specifications anyway.

Suggested-by: Liu Dave <DaveLiu@freescale.com>
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
This commit is contained in:
Anton Vorontsov 2009-02-19 18:20:39 +03:00 committed by Kim Phillips
parent 7e91558032
commit 7e2ec1de1d
1 changed files with 7 additions and 7 deletions
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14
board/freescale/mpc837xemds/pci.c
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@ -115,6 +115,13 @@ skip_pci:
if (PARTID_NO_E(spridr) == SPR_8379)
return;
if (pex2)
fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX_X2,
FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
else
fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX,
FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
/* Configure the clock for PCIE controller */
clrsetbits_be32(&clk->sccr, SCCR_PCIEXP1CM | SCCR_PCIEXP2CM,
SCCR_PCIEXP1CM_1 | SCCR_PCIEXP2CM_1);
@ -132,13 +139,6 @@ skip_pci:
out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR);
out_be32(&pcie_law[1].ar, LBLAWAR_EN | LBLAWAR_512MB);
if (pex2)
fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX_X2,
FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
else
fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX,
FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
mpc83xx_pcie_init(pex2 ? 1 : 2, pcie_reg, 0);
}