arm: mvebu: Support for 98DX25xx/98DX35xx SoC
Add support for the Allecat5/Alleycat5X SoC. These are L3 switches with an integrated CPU (referred to as the CnM block in Marvell's documentation). These have dual ARMv8.2 CPUs (Cortex-A55). This support has been ported from Marvell's SDK which is based on a much older version of U-Boot. Signed-off-by: Chris Packham <judge.packham@gmail.com>
This commit is contained in:
Chris Packham
Stefan Roese
parent
c249938214
commit
7d7bb99e22
277
arch/arm/dts/ac5-98dx25xx.dtsi
Normal file
277
arch/arm/dts/ac5-98dx25xx.dtsi
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@ -0,0 +1,277 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Device Tree For AC5.
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*
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* Copyright (C) 2021 Marvell
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* Copyright (C) 2022 Allied Telesis Labs
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*/
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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model = "Marvell AC5 SoC";
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compatible = "marvell,ac5";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&cpu0>;
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};
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core1 {
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cpu = <&cpu1>;
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};
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};
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};
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x0 0x0>;
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enable-method = "psci";
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next-level-cache = <&l2>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x0 0x100>;
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enable-method = "psci";
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next-level-cache = <&l2>;
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};
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l2: l2-cache {
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compatible = "cache";
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};
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};
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psci {
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compatible = "arm,psci-0.2";
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method = "smc";
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_PPI 8 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
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};
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pmu {
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compatible = "arm,armv8-pmuv3";
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interrupts = <GIC_PPI 12 IRQ_TYPE_LEVEL_HIGH>;
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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dma-ranges;
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internal-regs@7f000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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/* 16M internal register @ 0x7f00_0000 */
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ranges = <0x0 0x0 0x7f000000 0x1000000>;
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dma-coherent;
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uart0: serial@12000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x12000 0x100>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
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reg-io-width = <1>;
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clocks = <&cnm_clock>;
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status = "okay";
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};
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uart1: serial@12100 {
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compatible = "snps,dw-apb-uart";
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reg = <0x12100 0x100>;
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reg-shift = <2>;
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reg-io-width = <1>;
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clocks = <&cnm_clock>;
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status = "disabled";
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};
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uart2: serial@12200 {
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compatible = "snps,dw-apb-uart";
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reg = <0x12200 0x100>;
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reg-shift = <2>;
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reg-io-width = <1>;
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clocks = <&cnm_clock>;
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status = "disabled";
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};
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uart3: serial@12300 {
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compatible = "snps,dw-apb-uart";
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reg = <0x12300 0x100>;
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reg-shift = <2>;
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reg-io-width = <1>;
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clocks = <&cnm_clock>;
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status = "disabled";
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};
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mdio: mdio@22004 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "marvell,orion-mdio";
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reg = <0x22004 0x4>;
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clocks = <&cnm_clock>;
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};
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i2c0: i2c@11000 {
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compatible = "marvell,mv78230-i2c";
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reg = <0x11000 0x20>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&cnm_clock>;
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clock-names = "core";
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interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency=<100000>;
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status = "disabled";
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};
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i2c1: i2c@11100 {
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compatible = "marvell,mv78230-i2c";
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reg = <0x11100 0x20>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&cnm_clock>;
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clock-names = "core";
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interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency=<100000>;
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status = "disabled";
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};
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gpio0: gpio@18100 {
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compatible = "marvell,orion-gpio";
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reg = <0x18100 0x40>;
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ngpios = <32>;
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gpio-controller;
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#gpio-cells = <2>;
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status = "okay";
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};
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gpio1: gpio@18140 {
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reg = <0x18140 0x40>;
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compatible = "marvell,orion-gpio";
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ngpios = <14>;
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gpio-controller;
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#gpio-cells = <2>;
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status = "okay";
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};
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};
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/*
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* Dedicated section for devices behind 32bit controllers so we
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* can configure specific DMA mapping for them
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*/
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behind-32bit-controller@7f000000 {
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compatible = "simple-bus";
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#address-cells = <0x2>;
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#size-cells = <0x2>;
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ranges = <0x0 0x0 0x0 0x7f000000 0x0 0x1000000>;
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/* Host phy ram starts at 0x200M */
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dma-ranges = <0x0 0x0 0x2 0x0 0x1 0x0>;
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dma-coherent;
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eth0: ethernet@20000 {
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compatible = "marvell,armada-ac5-neta";
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reg = <0x0 0x20000 0x0 0x4000>;
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interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cnm_clock>;
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phy-mode = "sgmii";
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status = "disabled";
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};
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eth1: ethernet@24000 {
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compatible = "marvell,armada-ac5-neta";
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reg = <0x0 0x24000 0x0 0x4000>;
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interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cnm_clock>;
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phy-mode = "sgmii";
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status = "disabled";
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};
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usb0: usb@80000 {
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compatible = "marvell,ac5-ehci";
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reg = <0x0 0x80000 0x0 0x500>;
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interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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usb1: usb@a0000 {
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compatible = "marvell,ac5-ehci";
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reg = <0x0 0xa0000 0x0 0x500>;
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interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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};
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pinctrl0: pinctrl@80020100 {
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compatible = "marvell,mvebu-pinctrl";
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reg = <0 0x80020100 0 0x20>;
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pin-count = <46>;
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max-func = <0xf>;
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status = "okay";
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};
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spi0: spi@805a0000 {
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compatible = "marvell,armada-3700-spi";
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reg = <0x0 0x805a0000 0x0 0x50>;
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#address-cells = <0x1>;
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#size-cells = <0x0>;
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clocks = <&spi_clock>;
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interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
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num-cs = <1>;
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status = "disabled";
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};
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spi1: spi@805a8000 {
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compatible = "marvell,armada-3700-spi";
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reg = <0x0 0x805a8000 0x0 0x50>;
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#address-cells = <0x1>;
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#size-cells = <0x0>;
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clocks = <&spi_clock>;
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interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
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num-cs = <1>;
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status = "disabled";
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};
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gic: interrupt-controller@80600000 {
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compatible = "arm,gic-v3";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0x0 0x80600000 0x0 0x10000>, /* GICD */
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<0x0 0x80660000 0x0 0x40000>; /* GICR */
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interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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clocks {
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cnm_clock: cnm-clock {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <328000000>;
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};
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spi_clock: spi-clock {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <200000000>;
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};
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};
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};
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17
arch/arm/dts/ac5-98dx35xx.dtsi
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17
arch/arm/dts/ac5-98dx35xx.dtsi
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@ -0,0 +1,17 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Device Tree For AC5X.
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*
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* Copyright (C) 2022 Allied Telesis Labs
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*/
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#include "ac5-98dx25xx.dtsi"
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/ {
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model = "Marvell AC5X SoC";
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compatible = "marvell,ac5x", "marvell,ac5";
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};
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&cnm_clock {
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clock-frequency = <325000000>;
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};
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@ -50,6 +50,10 @@ config ARMADA_8K
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bool
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select ARM64
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config ALLEYCAT_5
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bool
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select ARM64
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# Armada PLL frequency (used for NAND clock generation)
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config SYS_MVEBU_PLL_CLOCK
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int
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@ -6,6 +6,7 @@ ifdef CONFIG_ARM64
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obj-$(CONFIG_ARMADA_3700) += armada3700/
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obj-$(CONFIG_ARMADA_8K) += armada8k/
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obj-$(CONFIG_ALLEYCAT_5) += alleycat5/
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obj-y += arm64-common.o
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else # CONFIG_ARM64
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8
arch/arm/mach-mvebu/alleycat5/Makefile
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8
arch/arm/mach-mvebu/alleycat5/Makefile
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@ -0,0 +1,8 @@
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#
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# Copyright (C) 2016 Stefan Roese <sr@denx.de>
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y = cpu.o
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obj-y += soc.o
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124
arch/arm/mach-mvebu/alleycat5/cpu.c
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124
arch/arm/mach-mvebu/alleycat5/cpu.c
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@ -0,0 +1,124 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2018 Marvell International Ltd.
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*/
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#include <common.h>
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#include <dm.h>
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#include <fdtdec.h>
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#include <linux/libfdt.h>
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#include <asm/io.h>
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#include <asm/system.h>
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#include <asm/arch/cpu.h>
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#include <linux/sizes.h>
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#include <asm/armv8/mmu.h>
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#include "soc.h"
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DECLARE_GLOBAL_DATA_PTR;
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#define RAM_SIZE SZ_1G
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static struct mm_region ac5_mem_map[] = {
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{
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/* RAM */
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.phys = CONFIG_SYS_SDRAM_BASE,
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.virt = CONFIG_SYS_SDRAM_BASE,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE
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},
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{
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/* MMIO regions */
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.phys = 0x00000000,
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.virt = 0xa0000000,
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.size = 0x100000,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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},
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{
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/* MMIO regions */
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.phys = 0x100000,
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.virt = 0x100000,
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.size = 0x3ff00000,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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},
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{
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/* MMIO regions */
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.phys = 0x7F000000,
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.virt = 0x7F000000,
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.size = 0x21000000,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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},
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{
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0,
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}
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};
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struct mm_region *mem_map = ac5_mem_map;
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void reset_cpu(void)
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{
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}
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int print_cpuinfo(void)
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{
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soc_print_device_info();
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soc_print_clock_info();
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return 0;
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}
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int alleycat5_dram_init(void)
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{
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#define SCRATCH_PAD_REG 0x80010018
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int ret;
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/* override DDR_FW size if DTS is set with size */
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ret = fdtdec_setup_mem_size_base();
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if (ret == -EINVAL)
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gd->ram_size = readl(SCRATCH_PAD_REG) * 4ULL;
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/* if DRAM size == 0, print error message */
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if (gd->ram_size == 0) {
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pr_err("DRAM size not initialized - check DRAM configuration\n");
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printf("\n Using temporary DRAM size of 512MB.\n\n");
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gd->ram_size = SZ_512M;
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}
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ac5_mem_map[0].size = gd->ram_size;
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return 0;
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}
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int alleycat5_dram_init_banksize(void)
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{
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/*
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* Config single DRAM bank
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*/
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gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
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gd->bd->bi_dram[0].size = gd->ram_size;
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return 0;
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}
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int timer_init(void)
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{
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return 0;
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}
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/*
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* get_ref_clk
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*
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* return: reference clock in MHz
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*/
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u32 get_ref_clk(void)
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{
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return 25;
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}
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298
arch/arm/mach-mvebu/alleycat5/soc.c
Normal file
298
arch/arm/mach-mvebu/alleycat5/soc.c
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@ -0,0 +1,298 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2018 Marvell International Ltd.
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*/
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#include <common.h>
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#include <asm/arch-armada8k/cache_llc.h>
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#include <asm/io.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/soc.h>
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#include <dm/device.h>
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#define DEVICE_ID_REG 0x7F90004C
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#define DEVICE_ID_MASK 0xffff0
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#define REV_ID_MASK 0xf
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#define DEVICE_ID_OFFSET 4
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#define REV_ID_OFFSET 0
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#define DEVICE_SAR_REG 0x944F8204
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#define DEVICE_ID_SUB_REV (MVEBU_REGISTER(0x2400230))
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#define DEVICE_ID_SUB_REV_OFFSET 7
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#define DEVICE_ID_SUB_REV_MASK (0xffff << DEVICE_ID_SUB_REV_OFFSET)
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#define AC5X_DEV_ID 0x9800
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struct soc_info {
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u32 dev_id;
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u32 rev_id;
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char *soc_name;
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};
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static struct soc_info soc_info_table[] = {
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/* Two reserved entries for unidentified devices - don't change */
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{ 0xB4FF, 0x0, "Unidentified Alleycat5"},
|
||||
{ 0x98FF, 0x0, "Unidentified Alleycat5x"},
|
||||
|
||||
{ 0xB400, 0x2, "Alleycat5-plus 98DX2538-A2"},
|
||||
{ 0xB401, 0x2, "Alleycat5-plus 98DX2535-A2"},
|
||||
{ 0xB402, 0x2, "Alleycat5-plus 98DX2532-A2"},
|
||||
{ 0xB403, 0x2, "Alleycat5-plus 98DX2531-A2"},
|
||||
{ 0xB408, 0x2, "Alleycat5 98DX2528-A2"},
|
||||
{ 0xB409, 0x2, "Alleycat5 98DX2525-A2"},
|
||||
{ 0xB40A, 0x2, "Alleycat5 98DX2522-A2"},
|
||||
{ 0xB40B, 0x2, "Alleycat5 98DX2521-A2"},
|
||||
{ 0xB410, 0x2, "Alleycat5-lite 98DX2518-A2"},
|
||||
{ 0xB411, 0x2, "Alleycat5-lite 98DX2515-A2"},
|
||||
{ 0xB412, 0x2, "Alleycat5-lite 98DX2512-A2"},
|
||||
{ 0xB413, 0x2, "Alleycat5-lite 98DX2511-A2"},
|
||||
|
||||
{ 0xB400, 0x1, "Alleycat5-plus 98DX2538-A1"},
|
||||
{ 0xB401, 0x1, "Alleycat5-plus 98DX2535-A1"},
|
||||
{ 0xB402, 0x1, "Alleycat5-plus 98DX2532-A1"},
|
||||
{ 0xB403, 0x1, "Alleycat5-plus 98DX2531-A1"},
|
||||
{ 0xB408, 0x1, "Alleycat5 98DX2528-A1"},
|
||||
{ 0xB409, 0x1, "Alleycat5 98DX2525-A1"},
|
||||
{ 0xB40A, 0x1, "Alleycat5 98DX2522-A1"},
|
||||
{ 0xB40B, 0x1, "Alleycat5 98DX2521-A1"},
|
||||
{ 0xB410, 0x1, "Alleycat5-lite 98DX2518-A1"},
|
||||
{ 0xB411, 0x1, "Alleycat5-lite 98DX2515-A1"},
|
||||
{ 0xB412, 0x1, "Alleycat5-lite 98DX2512-A1"},
|
||||
{ 0xB413, 0x1, "Alleycat5-lite 98DX2511-A1"},
|
||||
{ 0x9800, 0x1, "Alleycat5X 98DX3500M-A1"},
|
||||
{ 0x9806, 0x1, "Alleycat5X 98DX3501M-A1"},
|
||||
{ 0x9801, 0x1, "Alleycat5X 98DX3510M-A1"},
|
||||
{ 0x9802, 0x1, "Alleycat5X 98DX3520M-A1"},
|
||||
{ 0x9803, 0x1, "Alleycat5X 98DX3530M-A1"},
|
||||
{ 0x9804, 0x1, "Alleycat5X 98DX3540M-A1"},
|
||||
{ 0x9805, 0x1, "Alleycat5X 98DX3550M-A1"},
|
||||
{ 0x9820, 0x1, "Alleycat5X 98DX3500-A1"},
|
||||
{ 0x9826, 0x1, "Alleycat5X 98DX3501-A1"},
|
||||
{ 0x9821, 0x1, "Alleycat5X 98DX3510-A1"},
|
||||
{ 0x9861, 0x1, "Alleycat5X 98DX3510H-A1"},
|
||||
{ 0x9841, 0x1, "Alleycat5X 98DX3510MH-A1"},
|
||||
{ 0x9822, 0x1, "Alleycat5X 98DX3520-A1"},
|
||||
{ 0x9823, 0x1, "Alleycat5X 98DX3530-A1"},
|
||||
{ 0x9863, 0x1, "Alleycat5X 98DX3530H-A1"},
|
||||
{ 0x9824, 0x1, "Alleycat5X 98DX3540-A1"},
|
||||
{ 0x9825, 0x1, "Alleycat5X 98DX3550-A1"},
|
||||
|
||||
{ 0xB400, 0x0, "Alleycat5-plus 98DX2538-A0"},
|
||||
{ 0xB401, 0x0, "Alleycat5-plus 98DX2535-A0"},
|
||||
{ 0xB402, 0x0, "Alleycat5-plus 98DX2532-A0"},
|
||||
{ 0xB403, 0x0, "Alleycat5-plus 98DX2531-A0"},
|
||||
{ 0xB408, 0x0, "Alleycat5 98DX2528-A0"},
|
||||
{ 0xB409, 0x0, "Alleycat5 98DX2525-A0"},
|
||||
{ 0xB40A, 0x0, "Alleycat5 98DX2522-A0"},
|
||||
{ 0xB40B, 0x0, "Alleycat5 98DX2521-A0"},
|
||||
{ 0xB410, 0x0, "Alleycat5-lite 98DX2518-A0"},
|
||||
{ 0xB411, 0x0, "Alleycat5-lite 98DX2515-A0"},
|
||||
{ 0xB412, 0x0, "Alleycat5-lite 98DX2512-A0"},
|
||||
{ 0xB413, 0x0, "Alleycat5-lite 98DX2511-A0"},
|
||||
{ 0x9800, 0x0, "Alleycat5X 98DX3500M-A0"},
|
||||
{ 0x9806, 0x0, "Alleycat5X 98DX3501M-A0"},
|
||||
{ 0x9801, 0x0, "Alleycat5X 98DX3510M-A0"},
|
||||
{ 0x9802, 0x0, "Alleycat5X 98DX3520M-A0"},
|
||||
{ 0x9803, 0x0, "Alleycat5X 98DX3530M-A0"},
|
||||
{ 0x9804, 0x0, "Alleycat5X 98DX3540M-A0"},
|
||||
{ 0x9805, 0x0, "Alleycat5X 98DX3550M-A0"},
|
||||
{ 0x9820, 0x0, "Alleycat5X 98DX3500-A0"},
|
||||
{ 0x9826, 0x0, "Alleycat5X 98DX3501-A0"},
|
||||
{ 0x9821, 0x0, "Alleycat5X 98DX3510-A0"},
|
||||
{ 0x9861, 0x0, "Alleycat5X 98DX3510H-A0"},
|
||||
{ 0x9841, 0x0, "Alleycat5X 98DX3510MH-A0"},
|
||||
{ 0x9822, 0x0, "Alleycat5X 98DX3520-A0"},
|
||||
{ 0x9823, 0x0, "Alleycat5X 98DX3530-A0"},
|
||||
{ 0x9863, 0x0, "Alleycat5X 98DX3530H-A0"},
|
||||
{ 0x9824, 0x0, "Alleycat5X 98DX3540-A0"},
|
||||
{ 0x9825, 0x0, "Alleycat5X 98DX3550-A0"},
|
||||
};
|
||||
|
||||
#define BIT_VAL(b) ((1ULL << ((b) + 1)) - 1)
|
||||
#define BIT_RANGE(bl, bh) (BIT_VAL(bh) - BIT_VAL((bl) - 1))
|
||||
|
||||
#define PLL_MAX_CHOICE 4
|
||||
|
||||
#define CPU_TYPE_AC5 0
|
||||
#define CPU_TYPE_AC5x 1
|
||||
#define CPU_TYPE_LAST 2
|
||||
|
||||
enum mvebu_sar_opts {
|
||||
SAR_CPU_FREQ = 0,
|
||||
SAR_DDR_FREQ,
|
||||
SAR_AP_FABRIC_FREQ,
|
||||
SAR_CP_FABRIC_FREQ,
|
||||
SAR_CP0_PCIE0_CLK,
|
||||
SAR_CP0_PCIE1_CLK,
|
||||
SAR_CP1_PCIE0_CLK,
|
||||
SAR_CP1_PCIE1_CLK,
|
||||
SAR_BOOT_SRC,
|
||||
SAR_MAX_IDX
|
||||
};
|
||||
|
||||
static const u32 pll_freq_tbl[CPU_TYPE_LAST][SAR_AP_FABRIC_FREQ + 1][PLL_MAX_CHOICE] = {
|
||||
[CPU_TYPE_AC5] = {
|
||||
[SAR_CPU_FREQ] = {
|
||||
800, 1200, 1400, 1000
|
||||
},
|
||||
[SAR_DDR_FREQ] = {
|
||||
1200, 800, 0, 0
|
||||
},
|
||||
[SAR_AP_FABRIC_FREQ] = {
|
||||
396, 290, 197, 0
|
||||
},
|
||||
},
|
||||
[CPU_TYPE_AC5x] = {
|
||||
[SAR_CPU_FREQ] = {
|
||||
800, 1200, 1500, 1600
|
||||
},
|
||||
[SAR_DDR_FREQ] = {
|
||||
1200, 800, 0, 0
|
||||
},
|
||||
[SAR_AP_FABRIC_FREQ] = {
|
||||
0, 0, 0, 0
|
||||
}
|
||||
}
|
||||
};
|
||||
|
||||
static const u32 soc_sar_masks_tbl[CPU_TYPE_LAST][SAR_AP_FABRIC_FREQ + 1] = {
|
||||
[CPU_TYPE_AC5] = {
|
||||
[SAR_CPU_FREQ] = BIT_RANGE(18, 20),
|
||||
[SAR_DDR_FREQ] = BIT_RANGE(16, 17),
|
||||
[SAR_AP_FABRIC_FREQ] = BIT_RANGE(22, 23),
|
||||
},
|
||||
[CPU_TYPE_AC5x] = {
|
||||
[SAR_CPU_FREQ] = BIT_RANGE(8, 10),
|
||||
[SAR_DDR_FREQ] = BIT_RANGE(6, 7),
|
||||
[SAR_AP_FABRIC_FREQ] = 1,
|
||||
},
|
||||
};
|
||||
|
||||
static int get_soc_type_rev(u32 *type, u32 *rev)
|
||||
{
|
||||
*type = (readl(DEVICE_ID_REG) & DEVICE_ID_MASK) >> DEVICE_ID_OFFSET;
|
||||
*rev = (readl(DEVICE_ID_REG) & REV_ID_MASK) >> REV_ID_OFFSET;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void get_one_sar_freq(int cpu_type, u32 sar_reg_val, enum mvebu_sar_opts sar_opt, u32 *freq)
|
||||
{
|
||||
u32 mask;
|
||||
unsigned char choice;
|
||||
|
||||
mask = soc_sar_masks_tbl[cpu_type][sar_opt];
|
||||
choice = (sar_reg_val & mask) >> (__builtin_ffs(mask) - 1);
|
||||
*freq = pll_freq_tbl[cpu_type][sar_opt][choice];
|
||||
}
|
||||
|
||||
void get_sar_freq(struct sar_freq_modes *sar_freq)
|
||||
{
|
||||
int cpu_type;
|
||||
u32 soc_type, rev;
|
||||
u32 sar_reg_val = readl(DEVICE_SAR_REG);
|
||||
|
||||
get_soc_type_rev(&soc_type, &rev);
|
||||
cpu_type = (soc_type & 0xFF00) == AC5X_DEV_ID ? CPU_TYPE_AC5x : CPU_TYPE_AC5;
|
||||
|
||||
get_one_sar_freq(cpu_type, sar_reg_val, SAR_CPU_FREQ, &sar_freq->p_clk);
|
||||
get_one_sar_freq(cpu_type, sar_reg_val, SAR_AP_FABRIC_FREQ, &sar_freq->nb_clk);
|
||||
get_one_sar_freq(cpu_type, sar_reg_val, SAR_DDR_FREQ, &sar_freq->d_clk);
|
||||
}
|
||||
|
||||
static int get_soc_table_index(u32 *index)
|
||||
{
|
||||
u32 soc_type;
|
||||
u32 rev, i, ret = 1;
|
||||
|
||||
*index = 0;
|
||||
get_soc_type_rev(&soc_type, &rev);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(soc_info_table) && ret != 0; i++) {
|
||||
if (soc_type != soc_info_table[i].dev_id ||
|
||||
rev != soc_info_table[i].rev_id)
|
||||
continue;
|
||||
|
||||
*index = i;
|
||||
ret = 0;
|
||||
}
|
||||
|
||||
if (ret && ((soc_type & 0xFF00) == AC5X_DEV_ID))
|
||||
*index = 1;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int get_soc_name(char **soc_name)
|
||||
{
|
||||
u32 index;
|
||||
|
||||
get_soc_table_index(&index);
|
||||
*soc_name = soc_info_table[index].soc_name;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Print device's SoC name and AP & CP information */
|
||||
void soc_print_device_info(void)
|
||||
{
|
||||
char *soc_name = NULL;
|
||||
|
||||
get_soc_name(&soc_name);
|
||||
|
||||
printf("SoC: %s\n", soc_name);
|
||||
}
|
||||
|
||||
void soc_print_clock_info(void)
|
||||
{
|
||||
struct sar_freq_modes sar_freq;
|
||||
|
||||
get_sar_freq(&sar_freq);
|
||||
printf("Clock: CPU %4d MHz\n", sar_freq.p_clk);
|
||||
printf("\tDDR %4d MHz\n", sar_freq.d_clk);
|
||||
printf("\tFABRIC %4d MHz\n", sar_freq.nb_clk);
|
||||
printf("\tMSS %4d MHz\n", 200);
|
||||
}
|
||||
|
||||
/*
|
||||
* Override of __weak int mach_cpu_init(void) :
|
||||
* SoC/machine dependent CPU setup
|
||||
*/
|
||||
int mach_cpu_init(void)
|
||||
{
|
||||
u32 phy_i;
|
||||
u64 new_val, phy_base = 0x7F080800;
|
||||
|
||||
/* Init USB PHY */
|
||||
#define USB_STEPPING 0x20000
|
||||
#define WRITE_MASK(addr, mask, val) \
|
||||
{ new_val = (readl(addr) & (~(mask))) | (val);\
|
||||
writel(new_val, addr); }
|
||||
|
||||
for (phy_i = 0; phy_i < 2; phy_i++, phy_base += USB_STEPPING) {
|
||||
WRITE_MASK(phy_base + 0x4, 0x3, 0x2);
|
||||
WRITE_MASK(phy_base + 0xC, 0x3000000, 0x2000000);
|
||||
WRITE_MASK(phy_base + 0x1C, 0x3, 0x2);
|
||||
WRITE_MASK(phy_base + 0x0, 0x1FF007F, 0x600005);
|
||||
WRITE_MASK(phy_base + 0xC, 0x000F000, 0x0002000);
|
||||
/* Calibration Threshold Setting = 4*/
|
||||
WRITE_MASK(phy_base + 0x8, 0x700, 0x400)
|
||||
WRITE_MASK(phy_base + 0x14, 0x000000F, 0x000000a);
|
||||
/* Change AMP to 4*/
|
||||
WRITE_MASK(phy_base + 0xC, 0x3700000, 0x3400000);
|
||||
WRITE_MASK(phy_base + 0x4, 0x3, 0x3);
|
||||
/* Impedance calibration triggering is performed by USB probe */
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int arch_misc_init(void)
|
||||
{
|
||||
u32 type, rev;
|
||||
|
||||
get_soc_type_rev(&type, &rev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
7
arch/arm/mach-mvebu/alleycat5/soc.h
Normal file
7
arch/arm/mach-mvebu/alleycat5/soc.h
Normal file
@ -0,0 +1,7 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
|
||||
#ifndef _ALLEYCAT5_SOC_H
|
||||
#define _ALLEYCAT5_SOC_H
|
||||
void soc_print_device_info(void);
|
||||
void soc_print_clock_info(void);
|
||||
#endif /* _ALLEYCAT5_SOC_H */
|
||||
@ -53,6 +53,8 @@ __weak int dram_init_banksize(void)
|
||||
return a8k_dram_init_banksize();
|
||||
else if (CONFIG_IS_ENABLED(ARMADA_3700))
|
||||
return a3700_dram_init_banksize();
|
||||
else if (CONFIG_IS_ENABLED(ALLEYCAT_5))
|
||||
return alleycat5_dram_init_banksize();
|
||||
else
|
||||
return fdtdec_setup_memory_banksize();
|
||||
}
|
||||
@ -68,6 +70,9 @@ __weak int dram_init(void)
|
||||
if (CONFIG_IS_ENABLED(ARMADA_3700))
|
||||
return a3700_dram_init();
|
||||
|
||||
if (CONFIG_IS_ENABLED(ALLEYCAT_5))
|
||||
return alleycat5_dram_init();
|
||||
|
||||
if (fdtdec_setup_mem_size_base() != 0)
|
||||
return -EINVAL;
|
||||
|
||||
|
||||
@ -174,6 +174,10 @@ int a3700_dram_init_banksize(void);
|
||||
/* A3700 PCIe regions fixer for device tree */
|
||||
int a3700_fdt_fix_pcie_regions(void *blob);
|
||||
|
||||
/* Alleycat5 dram functions */
|
||||
int alleycat5_dram_init(void);
|
||||
int alleycat5_dram_init_banksize(void);
|
||||
|
||||
/*
|
||||
* get_ref_clk
|
||||
*
|
||||
|
||||
Loading…
Reference in New Issue
Block a user